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add spi & touch screen driver

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This commit is contained in:
cmc-ubuntu 2010-11-11 22:02:39 +08:00
commit cba07fe4a2
99 changed files with 47451 additions and 644 deletions
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2
Makefile
View File

@ -184,7 +184,7 @@ export KBUILD_BUILDHOST := $(SUBARCH)
#CROSS_COMPILE ?=
ARCH ?= arm
#CROSS_COMPILE :=/opt/android0320/mydroid/prebuilt/linux-x86/toolchain/arm-eabi-4.2.1/bin/arm-eabi-
CROSS_COMPILE ?=../toolchain/arm-eabi-4.4.0/bin/arm-eabi-
CROSS_COMPILE ?=../../google/myandroid/prebuilt/linux-x86/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
# Architecture as present in compile.h
UTS_MACHINE := $(ARCH)

176
arch/arm/configs/rk29_sdk_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.9
# Wed Oct 20 15:12:34 2010
# Sat Nov 6 11:33:18 2010
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@ -68,16 +68,10 @@ CONFIG_RESOURCE_COUNTERS=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../initramfs"
CONFIG_INITRAMFS_ROOT_UID=0
CONFIG_INITRAMFS_ROOT_GID=0
# CONFIG_RD_GZIP is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
CONFIG_INITRAMFS_COMPRESSION_NONE=y
# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -202,6 +196,11 @@ CONFIG_MMU=y
CONFIG_ARCH_RK29=y
CONFIG_MACH_RK29SDK=y
#
# RK29 VPU (Video Processing Unit) support
#
# CONFIG_RK29_VPU is not set
#
# Processor Type
#
@ -223,9 +222,9 @@ CONFIG_CPU_CP15_MMU=y
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_CPU_ICACHE_DISABLE=y
CONFIG_CPU_DCACHE_DISABLE=y
CONFIG_ARM_THUMBEE=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
CONFIG_ARM_L1_CACHE_SHIFT=5
@ -425,7 +424,89 @@ CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_TESTS is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_GPIO is not set
# CONFIG_MTD_NAND_DISKONCHIP is not set
CONFIG_MTD_NAND_RK29=y
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ONENAND is not set
#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
@ -435,8 +516,9 @@ CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MG_DISK is not set
CONFIG_MISC_DEVICES=y
# CONFIG_ANDROID_PMEM is not set
CONFIG_ANDROID_PMEM=y
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_KERNEL_DEBUGGER_CORE is not set
# CONFIG_UID_STAT is not set
@ -643,7 +725,34 @@ CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
# CONFIG_MMC_UNSAFE_RESUME is not set
# CONFIG_MMC_EMBEDDED_SDIO is not set
# CONFIG_MMC_PARANOID_SD_INIT is not set
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_SDMMC_RK29=y
#
# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
#
CONFIG_SDMMC0_RK29=y
CONFIG_SDMMC1_RK29=y
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_AT91 is not set
# CONFIG_MMC_ATMELMCI is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_SWITCH is not set
@ -711,6 +820,11 @@ CONFIG_ANDROID_LOW_MEMORY_KILLER=y
#
# CONFIG_RK2818_POWER is not set
#
# GPU Vivante
#
CONFIG_VIVANTE=y
#
# CMMB
#
@ -719,22 +833,12 @@ CONFIG_ANDROID_LOW_MEMORY_KILLER=y
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
@ -789,6 +893,18 @@ CONFIG_MISC_FILESYSTEMS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=y
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -927,7 +1043,7 @@ CONFIG_DEBUG_ERRORS=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
CONFIG_SECURITYFS=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
@ -1040,6 +1156,8 @@ CONFIG_CRC16=y
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y

2
arch/arm/mach-rk2818/devices.c
View File

@ -28,7 +28,7 @@
#include <linux/mtd/partitions.h>
#include <mach/gpio.h>
#include <mach/rk2818_nand.h>
#include <mach/rk29_nand.h>
#include <mach/iomux.h>
#include <mach/rk2818_camera.h> /* ddl@rock-chips.com : camera support */
#include <linux/i2c.h>

27
arch/arm/mach-rk29/Kconfig
View File

@ -4,4 +4,29 @@ config MACH_RK29SDK
bool "ROCKCHIP Board Rk29 For Sdk"
select PL330
help
Support for the ROCKCHIP Board For Rk29 Sdk.
Support for the ROCKCHIP Board For Rk29 Sdk.
menu "RK29 VPU (Video Processing Unit) support"
config RK29_VPU
tristate "Support for RK29 VPU (Video Processing Unit)"
depends on ARCH_RK29
default y
config RK29_VPU_DEBUG
bool "RK29 VPU debugging"
depends on RK29_VPU != n
default n
help
This is an option for the developers; most people should
say N here. This enables RK29 VPU driver debugging.
config RK29_VPU_HW_PERFORMANCE
bool "RK29 VPU HW_PERFORMANCE ioctl support"
depends on RK29_VPU != n
default n
help
This is an option for the developers; most people should
say N here. This enables RK29 VPU driver HW_PERFORMANCE ioctl.
endmenu

1
arch/arm/mach-rk29/Makefile
View File

@ -1,2 +1,3 @@
obj-y += timer.o io.o devices.o iomux.o clock.o rk29-pl330.o dma.o gpio.o
obj-$(CONFIG_RK29_VPU) += vpu.o
obj-$(CONFIG_MACH_RK29SDK) += board-rk29sdk.o

413
arch/arm/mach-rk29/board-rk29sdk.c
View File

@ -22,8 +22,10 @@
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/mmc/host.h>
#include <linux/android_pmem.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -35,6 +37,7 @@
#include <mach/irqs.h>
#include <mach/rk29_iomap.h>
#include <mach/board.h>
#include <mach/rk29_nand.h>
#include <linux/mtd/nand.h>
@ -44,8 +47,30 @@
#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
/* Set memory size of pmem */
#define SDRAM_SIZE SZ_128M
#define PMEM_GPU_SIZE (12 * SZ_1M)
#define PMEM_UI_SIZE SZ_16M
#define PMEM_VPU_SIZE SZ_32M
#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
#define LINUX_SIZE (PMEM_VPU_BASE - RK29_SDRAM_PHYS)
extern struct sys_timer rk29_timer;
int rk29_nand_io_init(void)
{
return 0;
}
struct rk29_nand_platform_data rk29_nand_data = {
.width = 1, /* data bus width in bytes */
.hw_ecc = 1, /* hw ecc 0: soft ecc */
.num_flash = 1,
.io_init = rk29_nand_io_init,
};
static struct rk29_gpio_bank rk29_gpiobankinit[] = {
{
@ -78,14 +103,385 @@ static struct rk29_gpio_bank rk29_gpiobankinit[] = {
},
};
/*****************************************************************************************
* lcd devices
* author: zyw@rock-chips.com
*****************************************************************************************/
//#ifdef CONFIG_LCD_TD043MGEA1
#define LCD_TXD_PIN RK29_PIN0_PA6 // ÂÒÌî,µÃÐÞ¸Ä
#define LCD_CLK_PIN RK29_PIN0_PA7 // ÂÒÌî,µÃÐÞ¸Ä
#define LCD_CS_PIN RK29_PIN0_PB6 // ÂÒÌî,µÃÐÞ¸Ä
#define LCD_TXD_MUX_NAME GPIOE_U1IR_I2C1_NAME
#define LCD_CLK_MUX_NAME NULL
#define LCD_CS_MUX_NAME GPIOH6_IQ_SEL_NAME
#define LCD_TXD_MUX_MODE 0
#define LCD_CLK_MUX_MODE 0
#define LCD_CS_MUX_MODE 0
//#endif
static int rk29_lcd_io_init(void)
{
int ret = 0;
#if 0
rk29_mux_api_set(LCD_CS_MUX_NAME, LCD_CS_MUX_MODE);
if (LCD_CS_PIN != INVALID_GPIO) {
ret = gpio_request(LCD_CS_PIN, NULL);
if(ret != 0)
{
goto err1;
printk(">>>>>> lcd cs gpio_request err \n ");
}
}
rk29_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE);
if (LCD_CLK_PIN != INVALID_GPIO) {
ret = gpio_request(LCD_CLK_PIN, NULL);
if(ret != 0)
{
goto err2;
printk(">>>>>> lcd clk gpio_request err \n ");
}
}
rk29_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE);
if (LCD_TXD_PIN != INVALID_GPIO) {
ret = gpio_request(LCD_TXD_PIN, NULL);
if(ret != 0)
{
goto err3;
printk(">>>>>> lcd txd gpio_request err \n ");
}
}
return 0;
err3:
if (LCD_CLK_PIN != INVALID_GPIO) {
gpio_free(LCD_CLK_PIN);
}
err2:
if (LCD_CS_PIN != INVALID_GPIO) {
gpio_free(LCD_CS_PIN);
}
err1:
#endif
return ret;
}
static int rk29_lcd_io_deinit(void)
{
int ret = 0;
#if 0
gpio_direction_output(LCD_CLK_PIN, 0);
gpio_set_value(LCD_CLK_PIN, GPIO_HIGH);
gpio_direction_output(LCD_TXD_PIN, 0);
gpio_set_value(LCD_TXD_PIN, GPIO_HIGH);
gpio_free(LCD_CS_PIN);
rk29_mux_api_mode_resume(LCD_CS_MUX_NAME);
gpio_free(LCD_CLK_PIN);
gpio_free(LCD_TXD_PIN);
rk29_mux_api_mode_resume(LCD_TXD_MUX_NAME);
rk29_mux_api_mode_resume(LCD_CLK_MUX_NAME);
#endif
return ret;
}
struct rk29lcd_info rk29_lcd_info = {
//.txd_pin = LCD_TXD_PIN,
//.clk_pin = LCD_CLK_PIN,
//.cs_pin = LCD_CS_PIN,
.io_init = rk29_lcd_io_init,
.io_deinit = rk29_lcd_io_deinit,
};
/*****************************************************************************************
* frame buffe devices
* author: zyw@rock-chips.com
*****************************************************************************************/
#define FB_ID 0
#define FB_DISPLAY_ON_PIN RK29_PIN0_PB1 // ÂÒÌî,µÃÐÞ¸Ä
#define FB_LCD_STANDBY_PIN INVALID_GPIO
#define FB_MCU_FMK_PIN INVALID_GPIO
#if 0
#define FB_DISPLAY_ON_VALUE GPIO_LOW
#define FB_LCD_STANDBY_VALUE 0
#define FB_DISPLAY_ON_MUX_NAME GPIOB1_SMCS1_MMC0PCA_NAME
#define FB_DISPLAY_ON_MUX_MODE IOMUXA_GPIO0_B1
#define FB_LCD_STANDBY_MUX_NAME NULL
#define FB_LCD_STANDBY_MUX_MODE 1
#define FB_MCU_FMK_PIN_MUX_NAME NULL
#define FB_MCU_FMK_MUX_MODE 0
#define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME
#define FB_DATA0_16_MUX_MODE 1
#define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME
#define FB_DATA17_18_MUX_MODE 1
#define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME
#define FB_DATA19_24_MUX_MODE 1
#define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME
#define FB_DEN_MUX_MODE 1
#define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME
#define FB_VSYNC_MUX_MODE 1
#define FB_MCU_FMK_MUX_NAME NULL
#define FB_MCU_FMK_MUX_MODE 0
#endif
static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
int ret = 0;
#if 0
if(fb_setting->data_num <=16)
rk29_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE);
if(fb_setting->data_num >16 && fb_setting->data_num<=18)
rk29_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE);
if(fb_setting->data_num >18)
rk29_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE);
if(fb_setting->vsync_en)
rk29_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE);
if(fb_setting->den_en)
rk29_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE);
if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO))
{
rk29_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE);
ret = gpio_request(FB_MCU_FMK_PIN, NULL);
if(ret != 0)
{
gpio_free(FB_MCU_FMK_PIN);
printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
}
gpio_direction_input(FB_MCU_FMK_PIN);
}
if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO))
{
rk29_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE);
ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
if(ret != 0)
{
gpio_free(FB_DISPLAY_ON_PIN);
printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
}
}
if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO))
{
rk29_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE);
ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
if(ret != 0)
{
gpio_free(FB_LCD_STANDBY_PIN);
printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
}
}
#endif
return ret;
}
struct rk29fb_info rk29_fb_info = {
.fb_id = FB_ID,
//.disp_on_pin = FB_DISPLAY_ON_PIN,
//.disp_on_value = FB_DISPLAY_ON_VALUE,
//.standby_pin = FB_LCD_STANDBY_PIN,
//.standby_value = FB_LCD_STANDBY_VALUE,
//.mcu_fmk_pin = FB_MCU_FMK_PIN,
.lcd_info = &rk29_lcd_info,
.io_init = rk29_fb_io_init,
};
static struct android_pmem_platform_data android_pmem_pdata = {
.name = "pmem",
.start = PMEM_UI_BASE,
.size = PMEM_UI_SIZE,
.no_allocator = 0,
.cached = 1,
};
static struct platform_device android_pmem_device = {
.name = "android_pmem",
.id = 0,
.dev = {
.platform_data = &android_pmem_pdata,
},
};
static struct android_pmem_platform_data android_pmem_vpu_pdata = {
.name = "pmem_vpu",
.start = PMEM_VPU_BASE,
.size = PMEM_VPU_SIZE,
.no_allocator = 0,
.cached = 1,
};
static struct platform_device android_pmem_vpu_device = {
.name = "android_pmem",
.id = 2,
.dev = {
.platform_data = &android_pmem_vpu_pdata,
},
};
/*****************************************************************************************
* SDMMC devices
*****************************************************************************************/
#ifdef CONFIG_SDMMC0_RK29
void rk29_sdmmc0_cfg_gpio(struct platform_device *dev)
{
rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);
}
#define CONFIG_SDMMC0_USE_DMA
struct rk29_sdmmc_platform_data default_sdmmc0_data = {
.num_slots = 1,
.host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
.host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
.io_init = rk29_sdmmc0_cfg_gpio,
.dma_name = "sd_mmc",
#ifdef CONFIG_SDMMC0_USE_DMA
.use_dma = 1,
#else
.use_dma = 0,
#endif
};
#endif
#ifdef CONFIG_SDMMC1_RK29
#define CONFIG_SDMMC1_USE_DMA
void rk29_sdmmc1_cfg_gpio(struct platform_device *dev)
{
rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
}
struct rk29_sdmmc_platform_data default_sdmmc1_data = {
.num_slots = 1,
.host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
MMC_VDD_32_33|MMC_VDD_33_34),
.host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
.io_init = rk29_sdmmc1_cfg_gpio,
.dma_name = "sdio",
#ifdef CONFIG_SDMMC1_USE_DMA
.use_dma = 1,
#else
.use_dma = 0,
#endif
};
#endif
#ifdef CONFIG_VIVANTE
static struct resource resources_gpu[] = {
[0] = {
.name = "gpu_irq",
.start = IRQ_GPU,
.end = IRQ_GPU,
.flags = IORESOURCE_IRQ,
},
[1] = {
.name = "gpu_base",
.start = RK29_GPU_PHYS,
.end = RK29_GPU_PHYS + (256 << 10),
.flags = IORESOURCE_MEM,
},
[2] = {
.name = "gpu_mem",
.start = PMEM_GPU_BASE,
.end = PMEM_GPU_BASE + PMEM_GPU_SIZE,
.flags = IORESOURCE_MEM,
},
};
struct platform_device rk29_device_gpu = {
.name = "galcore",
.id = 0,
.num_resources = ARRAY_SIZE(resources_gpu),
.resource = resources_gpu,
};
#endif
static void __init rk29_board_iomux_init(void)
{
#ifdef CONFIG_UART0_RK29
rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT);
rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN);
#ifdef CONFIG_UART0_CTS_RTS_RK29
rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N);
rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N);
#endif
#endif
#ifdef CONFIG_UART1_RK29
rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
#endif
#ifdef CONFIG_UART2_RK29
rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT);
rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN);
#ifdef CONFIG_UART2_CTS_RTS_RK29
rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N);
#endif
#endif
#ifdef CONFIG_UART3_RK29
rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT);
rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN);
#ifdef CONFIG_UART3_CTS_RTS_RK29
rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N);
rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);
#endif
#endif
}
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_UART1_RK29
#ifdef CONFIG_UART1_RK29
&rk29_device_uart1,
#endif
#ifdef CONFIG_SPIM_RK29XX
&rk29xx_device_spi0m,
&rk29xx_device_spi1m,
#endif
#ifdef CONFIG_SDMMC0_RK29
&rk29_device_sdmmc0,
#endif
#ifdef CONFIG_SDMMC1_RK29
&rk29_device_sdmmc1,
#endif
#ifdef CONFIG_MTD_NAND_RK29
&rk29_device_nand,
#endif
#ifdef CONFIG_FB_RK29
&rk29_device_fb,
#endif
#ifdef CONFIG_VIVANTE
&rk29_device_gpu,
#endif
&android_pmem_device,
&android_pmem_vpu_device,
};
/*****************************************************************************************
@ -286,12 +682,23 @@ static void __init machine_rk29_init_irq(void)
rk29_gpio_init(rk29_gpiobankinit, MAX_BANK);
rk29_gpio_irq_setup();
}
static void __init machine_rk29_board_init(void)
{
rk29_board_iomux_init();
platform_add_devices(devices, ARRAY_SIZE(devices));
spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
}
static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
mi->nr_banks = 1;
mi->bank[0].start = RK29_SDRAM_PHYS;
mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS);
mi->bank[0].size = LINUX_SIZE;
}
static void __init machine_rk29_mapio(void)
{
rk29_map_common_io();
@ -300,11 +707,11 @@ static void __init machine_rk29_mapio(void)
}
MACHINE_START(RK29, "RK29board")
/* UART for LL DEBUG */
/* UART for LL DEBUG */
.phys_io = RK29_UART1_PHYS,
.io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
.boot_params = RK29_SDRAM_PHYS + 0x88000,
.fixup = machine_rk29_fixup,
.map_io = machine_rk29_mapio,
.init_irq = machine_rk29_init_irq,
.init_machine = machine_rk29_board_init,

26
arch/arm/mach-rk29/clock.c
View File

@ -1126,6 +1126,19 @@ static struct clk clk_##NAME = { \
.gate_idx = CLK_GATE_##ID, \
}
GATE_CLK(i2c0, pclk_cpu, I2C0);
GATE_CLK(i2c1, pclk_periph, I2C1);
GATE_CLK(i2c2, pclk_periph, I2C2);
GATE_CLK(i2c3, pclk_periph, I2C3);
GATE_CLK(gpio0, pclk_cpu, GPIO0);
GATE_CLK(gpio1, pclk_periph, GPIO1);
GATE_CLK(gpio2, pclk_periph, GPIO2);
GATE_CLK(gpio3, pclk_periph, GPIO3);
GATE_CLK(gpio4, pclk_cpu, GPIO4);
GATE_CLK(gpio5, pclk_periph, GPIO5);
GATE_CLK(gpio6, pclk_cpu, GPIO6);
#define CLK(dev, con, ck) \
{ \
.dev_id = dev, \
@ -1231,6 +1244,19 @@ static struct clk_lookup clks[] = {
CLK(NULL, "hclk_vdpu", &hclk_vdpu),
CLK1(gpu),
CLK(NULL, "aclk_gpu", &aclk_gpu),
CLK("rk29_i2c.0", "i2c", &clk_i2c0),
CLK("rk29_i2c.1", "i2c", &clk_i2c1),
CLK("rk29_i2c.2", "i2c", &clk_i2c2),
CLK("rk29_i2c.3", "i2c", &clk_i2c3),
CLK1(gpio0),
CLK1(gpio1),
CLK1(gpio2),
CLK1(gpio3),
CLK1(gpio4),
CLK1(gpio5),
CLK1(gpio6),
};
static LIST_HEAD(clocks);

109
arch/arm/mach-rk29/devices.c
View File

@ -21,7 +21,59 @@
#include <mach/rk29_iomap.h>
#include <mach/rk29-dma-pl330.h>
#include "devices.h"
#ifdef CONFIG_SDMMC0_RK29
static struct resource resources_sdmmc0[] = {
{
.start = IRQ_SDMMC,
.end = IRQ_SDMMC,
.flags = IORESOURCE_IRQ,
},
{
.start = RK29_SDMMC0_PHYS,
.end = RK29_SDMMC0_PHYS + RK29_SDMMC0_SIZE -1,
.flags = IORESOURCE_MEM,
}
};
#endif
#ifdef CONFIG_SDMMC1_RK29
static struct resource resources_sdmmc1[] = {
{
.start = IRQ_SDIO,
.end = IRQ_SDIO,
.flags = IORESOURCE_IRQ,
},
{
.start = RK29_SDMMC1_PHYS,
.end = RK29_SDMMC1_PHYS + RK29_SDMMC1_SIZE -1,
.flags = IORESOURCE_MEM,
}
};
#endif
/* sdmmc */
#ifdef CONFIG_SDMMC0_RK29
struct platform_device rk29_device_sdmmc0 = {
.name = "rk29_sdmmc",
.id = 0,
.num_resources = ARRAY_SIZE(resources_sdmmc0),
.resource = resources_sdmmc0,
.dev = {
.platform_data = &default_sdmmc0_data,
},
};
#endif
#ifdef CONFIG_SDMMC1_RK29
struct platform_device rk29_device_sdmmc1 = {
.name = "rk29_sdmmc",
.id = 1,
.num_resources = ARRAY_SIZE(resources_sdmmc1),
.resource = resources_sdmmc1,
.dev = {
.platform_data = &default_sdmmc1_data,
},
};
#endif
/*
* rk29 4 uarts device
*/
@ -34,7 +86,7 @@ static struct resource resources_uart0[] = {
},
{
.start = RK29_UART0_PHYS,
.end = RK29_UART0_PHYS + SZ_1K - 1,
.end = RK29_UART0_PHYS + RK29_UART0_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
@ -48,7 +100,7 @@ static struct resource resources_uart1[] = {
},
{
.start = RK29_UART1_PHYS,
.end = RK29_UART1_PHYS + SZ_1K - 1,
.end = RK29_UART1_PHYS + RK29_UART1_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
@ -62,7 +114,7 @@ static struct resource resources_uart2[] = {
},
{
.start = RK29_UART2_PHYS,
.end = RK29_UART2_PHYS + SZ_1K - 1,
.end = RK29_UART2_PHYS + RK29_UART2_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
@ -76,7 +128,7 @@ static struct resource resources_uart3[] = {
},
{
.start = RK29_UART3_PHYS,
.end = RK29_UART3_PHYS + SZ_1K - 1,
.end = RK29_UART3_PHYS + RK29_UART3_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
@ -186,4 +238,51 @@ struct platform_device rk29xx_device_spi1m = {
},
};
#ifdef CONFIG_FB_RK29
/* rk29 fb resource */
static struct resource rk29_fb_resource[] = {
[0] = {
.start = RK29_LCDC_PHYS,
.end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCDC,
.end = IRQ_LCDC,
.flags = IORESOURCE_IRQ,
},
};
/*platform_device*/
extern struct rk29fb_info rk29_fb_info;
struct platform_device rk29_device_fb = {
.name = "rk29-fb",
.id = 4,
.num_resources = ARRAY_SIZE(rk29_fb_resource),
.resource = rk29_fb_resource,
.dev = {
.platform_data = &rk29_fb_info,
}
};
#endif
#if defined(CONFIG_MTD_NAND_RK29)
static struct resource nand_resources[] = {
{
.start = RK29_NANDC_PHYS,
.end = RK29_NANDC_PHYS+RK29_NANDC_SIZE -1,
.flags = IORESOURCE_MEM,
}
};
struct platform_device rk29_device_nand = {
.name = "rk29-nand",
.id = -1,
.resource = nand_resources,
.num_resources= ARRAY_SIZE(nand_resources),
.dev = {
.platform_data= &rk29_nand_data,
},
};
#endif

9
arch/arm/mach-rk29/devices.h
View File

@ -16,6 +16,7 @@
#ifndef __ARCH_ARM_MACH_RK29_DEVICES_H
#define __ARCH_ARM_MACH_RK29_DEVICES_H
extern struct rk29_nand_platform_data rk29_nand_data;
extern struct platform_device rk29_device_uart0;
extern struct platform_device rk29_device_uart1;
@ -25,5 +26,11 @@ extern struct platform_device rk29xx_device_spi0m;
extern struct platform_device rk29xx_device_spi1m;
extern struct rk29xx_spi_platform_data rk29xx_spi0_platdata;
extern struct rk29xx_spi_platform_data rk29xx_spi1_platdata;
extern struct platform_device rk29_device_fb;
extern struct platform_device rk29_device_nand;
extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
extern struct platform_device rk29_device_sdmmc0;
extern struct platform_device rk29_device_sdmmc1;
#endif
#endif

5
arch/arm/mach-rk29/gpio.c
View File

@ -606,7 +606,8 @@ void __init rk29_gpio_irq_setup(void)
irq = IRQ_GPIO6;
break;
}
set_irq_chip_data(irq+14, this);
set_irq_chip_data(NR_AIC_IRQS+this->bank->id,this);
set_irq_chained_handler(irq, gpio_irq_handler);
this += 1;
pin += 32;
@ -630,4 +631,4 @@ void __init rk29_gpio_init(struct rk29_gpio_bank *data, int nr_banks)
gpiochip_add(&rk29_gpio->chip);
}
printk("rk29_gpio_init:nr_banks=%d\n",nr_banks);
}
}

44
arch/arm/mach-rk29/include/mach/board.h
View File

@ -34,6 +34,50 @@ struct rk29xx_spi_platform_data {
u16 num_chipselect;
};
#define INVALID_GPIO -1
struct rk29lcd_info{
u32 lcd_id;
u32 txd_pin;
u32 clk_pin;
u32 cs_pin;
int (*io_init)(void);
int (*io_deinit)(void);
};
struct rk29_fb_setting_info{
u8 data_num;
u8 vsync_en;
u8 den_en;
u8 mcu_fmk_en;
u8 disp_on_en;
u8 standby_en;
};
struct rk29fb_info{
u32 fb_id;
u32 disp_on_pin;
u8 disp_on_value;
u32 standby_pin;
u8 standby_value;
u32 mcu_fmk_pin;
struct rk29lcd_info *lcd_info;
int (*io_init)(struct rk29_fb_setting_info *fb_setting);
int (*io_deinit)(void);
};
struct rk29_sdmmc_platform_data {
unsigned int num_slots;
unsigned int host_caps;
unsigned int host_ocr_avail;
unsigned int use_dma:1;
char dma_name[8];
int (*io_init)(void);
int (*io_deinit)(void);
int (*status)(struct device *);
int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
};
void __init rk29_map_common_io(void);
void __init rk29_clock_init(void);

443
arch/arm/mach-rk29/include/mach/gpio.h
View File

@ -14,7 +14,8 @@
*/
#ifndef __ARCH_ARM_MACH_RK29_GPIO_H
#define __ARCH_ARM_MACH_RK29_GPIO_H
#include <asm/irq.h>
typedef enum eGPIOPinLevel
{
GPIO_LOW=0,
@ -67,236 +68,236 @@ typedef enum GPIOIntType {
#define PIN_BASE 0
#define MAX_BANK 7
#define RK29_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0);
#define RK29_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1);
#define RK29_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
#define RK29_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
#define RK29_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
#define RK29_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4);
#define RK29_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5);
#define RK29_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6);
#define RK29_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7);
#define RK29_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8);
#define RK29_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9);
#define RK29_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10);
#define RK29_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11);
#define RK29_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12);
#define RK29_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13);
#define RK29_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14);
#define RK29_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15);
#define RK29_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16);
#define RK29_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17);
#define RK29_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18);
#define RK29_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19);
#define RK29_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20);
#define RK29_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21);
#define RK29_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22);
#define RK29_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23);
#define RK29_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24);
#define RK29_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25);
#define RK29_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26);
#define RK29_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27);
#define RK29_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28);
#define RK29_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29);
#define RK29_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30);
#define RK29_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31);
#define RK29_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
#define RK29_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
#define RK29_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
#define RK29_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
#define RK29_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
#define RK29_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
#define RK29_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
#define RK29_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
#define RK29_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
#define RK29_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
#define RK29_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
#define RK29_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
#define RK29_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
#define RK29_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
#define RK29_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
#define RK29_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
#define RK29_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
#define RK29_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
#define RK29_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
#define RK29_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
#define RK29_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
#define RK29_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
#define RK29_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
#define RK29_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
#define RK29_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
#define RK29_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
#define RK29_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
#define RK29_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
#define RK29_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0);
#define RK29_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2);
#define RK29_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
#define RK29_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
#define RK29_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
#define RK29_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
#define RK29_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5);
#define RK29_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6);
#define RK29_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7);
#define RK29_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8);
#define RK29_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9);
#define RK29_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10);
#define RK29_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11);
#define RK29_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12);
#define RK29_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13);
#define RK29_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14);
#define RK29_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15);
#define RK29_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16);
#define RK29_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17);
#define RK29_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18);
#define RK29_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19);
#define RK29_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20);
#define RK29_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21);
#define RK29_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22);
#define RK29_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23);
#define RK29_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24);
#define RK29_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25);
#define RK29_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26);
#define RK29_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27);
#define RK29_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28);
#define RK29_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29);
#define RK29_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30);
#define RK29_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31);
#define RK29_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
#define RK29_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
#define RK29_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
#define RK29_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
#define RK29_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
#define RK29_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
#define RK29_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
#define RK29_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
#define RK29_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
#define RK29_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
#define RK29_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
#define RK29_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
#define RK29_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
#define RK29_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
#define RK29_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
#define RK29_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
#define RK29_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
#define RK29_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
#define RK29_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
#define RK29_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
#define RK29_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
#define RK29_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
#define RK29_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
#define RK29_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
#define RK29_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
#define RK29_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
#define RK29_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
#define RK29_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0);
#define RK29_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1);
#define RK29_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2);
#define RK29_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3);
#define RK29_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4);
#define RK29_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5);
#define RK29_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6);
#define RK29_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7);
#define RK29_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8);
#define RK29_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9);
#define RK29_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10);
#define RK29_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11);
#define RK29_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12);
#define RK29_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13);
#define RK29_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14);
#define RK29_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15);
#define RK29_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16);
#define RK29_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
#define RK29_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
#define RK29_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
#define RK29_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
#define RK29_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
#define RK29_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
#define RK29_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
#define RK29_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
#define RK29_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
#define RK29_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
#define RK29_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
#define RK29_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
#define RK29_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
#define RK29_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
#define RK29_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
#define RK29_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
#define RK29_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
#define RK29_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18);
#define RK29_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19);
#define RK29_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20);
#define RK29_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
#define RK29_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
#define RK29_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
#define RK29_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
#define RK29_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22);
#define RK29_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23);
#define RK29_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24);
#define RK29_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25);
#define RK29_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26);
#define RK29_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27);
#define RK29_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28);
#define RK29_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29);
#define RK29_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30);
#define RK29_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31);
#define RK29_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
#define RK29_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
#define RK29_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
#define RK29_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
#define RK29_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
#define RK29_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
#define RK29_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
#define RK29_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
#define RK29_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
#define RK29_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
#define RK29_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0);
#define RK29_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1);
#define RK29_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2);
#define RK29_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3);
#define RK29_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4);
#define RK29_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5);
#define RK29_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6);
#define RK29_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7);
#define RK29_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8);
#define RK29_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9);
#define RK29_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10);
#define RK29_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11);
#define RK29_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12);
#define RK29_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13);
#define RK29_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14);
#define RK29_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15);
#define RK29_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16);
#define RK29_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17);
#define RK29_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18);
#define RK29_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19);
#define RK29_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20);
#define RK29_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21);
#define RK29_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22);
#define RK29_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23);
#define RK29_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24);
#define RK29_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25);
#define RK29_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26);
#define RK29_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27);
#define RK29_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28);
#define RK29_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29);
#define RK29_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30);
#define RK29_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31);
#define RK29_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
#define RK29_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
#define RK29_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
#define RK29_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
#define RK29_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
#define RK29_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
#define RK29_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
#define RK29_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
#define RK29_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
#define RK29_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
#define RK29_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
#define RK29_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
#define RK29_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
#define RK29_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
#define RK29_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
#define RK29_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
#define RK29_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
#define RK29_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
#define RK29_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
#define RK29_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
#define RK29_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
#define RK29_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
#define RK29_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
#define RK29_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
#define RK29_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
#define RK29_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
#define RK29_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
#define RK29_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
#define RK29_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
#define RK29_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
#define RK29_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
#define RK29_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0);
#define RK29_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1);
#define RK29_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2);
#define RK29_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3);
#define RK29_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4);
#define RK29_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5);
#define RK29_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6);
#define RK29_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7);
#define RK29_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8);
#define RK29_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9);
#define RK29_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10);
#define RK29_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11);
#define RK29_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12);
#define RK29_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13);
#define RK29_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14);
#define RK29_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15);
#define RK29_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16);
#define RK29_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17);
#define RK29_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18);
#define RK29_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19);
#define RK29_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20);
#define RK29_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21);
#define RK29_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22);
#define RK29_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23);
#define RK29_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24);
#define RK29_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25);
#define RK29_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26);
#define RK29_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27);
#define RK29_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28);
#define RK29_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29);
#define RK29_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30);
#define RK29_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31);
#define RK29_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0)
#define RK29_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2)
#define RK29_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3)
#define RK29_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4)
#define RK29_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5)
#define RK29_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6)
#define RK29_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7)
#define RK29_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8)
#define RK29_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9)
#define RK29_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10)
#define RK29_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11)
#define RK29_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12)
#define RK29_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13)
#define RK29_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14)
#define RK29_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15)
#define RK29_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16)
#define RK29_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17)
#define RK29_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18)
#define RK29_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19)
#define RK29_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20)
#define RK29_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21)
#define RK29_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22)
#define RK29_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23)
#define RK29_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24)
#define RK29_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25)
#define RK29_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26)
#define RK29_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27)
#define RK29_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28)
#define RK29_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29)
#define RK29_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30)
#define RK29_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31)
#define RK29_PIN5_PA0 (5*NUM_GROUP + PIN_BASE + 0);
#define RK29_PIN5_PA1 (5*NUM_GROUP + PIN_BASE + 1);
#define RK29_PIN5_PA2 (5*NUM_GROUP + PIN_BASE + 2);
#define RK29_PIN5_PA3 (5*NUM_GROUP + PIN_BASE + 3);
#define RK29_PIN5_PA4 (5*NUM_GROUP + PIN_BASE + 4);
#define RK29_PIN5_PA5 (5*NUM_GROUP + PIN_BASE + 5);
#define RK29_PIN5_PA6 (5*NUM_GROUP + PIN_BASE + 6);
#define RK29_PIN5_PA7 (5*NUM_GROUP + PIN_BASE + 7);
#define RK29_PIN5_PB0 (5*NUM_GROUP + PIN_BASE + 8);
#define RK29_PIN5_PB1 (5*NUM_GROUP + PIN_BASE + 9);
#define RK29_PIN5_PB2 (5*NUM_GROUP + PIN_BASE + 10);
#define RK29_PIN5_PB3 (5*NUM_GROUP + PIN_BASE + 11);
#define RK29_PIN5_PB4 (5*NUM_GROUP + PIN_BASE + 12);
#define RK29_PIN5_PB5 (5*NUM_GROUP + PIN_BASE + 13);
#define RK29_PIN5_PB6 (5*NUM_GROUP + PIN_BASE + 14);
#define RK29_PIN5_PB7 (5*NUM_GROUP + PIN_BASE + 15);
#define RK29_PIN5_PC0 (5*NUM_GROUP + PIN_BASE + 16);
#define RK29_PIN5_PC1 (5*NUM_GROUP + PIN_BASE + 17);
#define RK29_PIN5_PC2 (5*NUM_GROUP + PIN_BASE + 18);
#define RK29_PIN5_PC3 (5*NUM_GROUP + PIN_BASE + 19);
#define RK29_PIN5_PC4 (5*NUM_GROUP + PIN_BASE + 20);
#define RK29_PIN5_PC5 (5*NUM_GROUP + PIN_BASE + 21);
#define RK29_PIN5_PC6 (5*NUM_GROUP + PIN_BASE + 22);
#define RK29_PIN5_PC7 (5*NUM_GROUP + PIN_BASE + 23);
#define RK29_PIN5_PD0 (5*NUM_GROUP + PIN_BASE + 24);
#define RK29_PIN5_PD1 (5*NUM_GROUP + PIN_BASE + 25);
#define RK29_PIN5_PD2 (5*NUM_GROUP + PIN_BASE + 26);
#define RK29_PIN5_PD3 (5*NUM_GROUP + PIN_BASE + 27);
#define RK29_PIN5_PD4 (5*NUM_GROUP + PIN_BASE + 28);
#define RK29_PIN5_PD5 (5*NUM_GROUP + PIN_BASE + 29);
#define RK29_PIN5_PD6 (5*NUM_GROUP + PIN_BASE + 30);
#define RK29_PIN5_PD7 (5*NUM_GROUP + PIN_BASE + 31);
#define RK29_PIN5_PA0 (5*NUM_GROUP + PIN_BASE + 0)
#define RK29_PIN5_PA1 (5*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN5_PA2 (5*NUM_GROUP + PIN_BASE + 2)
#define RK29_PIN5_PA3 (5*NUM_GROUP + PIN_BASE + 3)
#define RK29_PIN5_PA4 (5*NUM_GROUP + PIN_BASE + 4)
#define RK29_PIN5_PA5 (5*NUM_GROUP + PIN_BASE + 5)
#define RK29_PIN5_PA6 (5*NUM_GROUP + PIN_BASE + 6)
#define RK29_PIN5_PA7 (5*NUM_GROUP + PIN_BASE + 7)
#define RK29_PIN5_PB0 (5*NUM_GROUP + PIN_BASE + 8)
#define RK29_PIN5_PB1 (5*NUM_GROUP + PIN_BASE + 9)
#define RK29_PIN5_PB2 (5*NUM_GROUP + PIN_BASE + 10)
#define RK29_PIN5_PB3 (5*NUM_GROUP + PIN_BASE + 11)
#define RK29_PIN5_PB4 (5*NUM_GROUP + PIN_BASE + 12)
#define RK29_PIN5_PB5 (5*NUM_GROUP + PIN_BASE + 13)
#define RK29_PIN5_PB6 (5*NUM_GROUP + PIN_BASE + 14)
#define RK29_PIN5_PB7 (5*NUM_GROUP + PIN_BASE + 15)
#define RK29_PIN5_PC0 (5*NUM_GROUP + PIN_BASE + 16)
#define RK29_PIN5_PC1 (5*NUM_GROUP + PIN_BASE + 17)
#define RK29_PIN5_PC2 (5*NUM_GROUP + PIN_BASE + 18)
#define RK29_PIN5_PC3 (5*NUM_GROUP + PIN_BASE + 19)
#define RK29_PIN5_PC4 (5*NUM_GROUP + PIN_BASE + 20)
#define RK29_PIN5_PC5 (5*NUM_GROUP + PIN_BASE + 21)
#define RK29_PIN5_PC6 (5*NUM_GROUP + PIN_BASE + 22)
#define RK29_PIN5_PC7 (5*NUM_GROUP + PIN_BASE + 23)
#define RK29_PIN5_PD0 (5*NUM_GROUP + PIN_BASE + 24)
#define RK29_PIN5_PD1 (5*NUM_GROUP + PIN_BASE + 25)
#define RK29_PIN5_PD2 (5*NUM_GROUP + PIN_BASE + 26)
#define RK29_PIN5_PD3 (5*NUM_GROUP + PIN_BASE + 27)
#define RK29_PIN5_PD4 (5*NUM_GROUP + PIN_BASE + 28)
#define RK29_PIN5_PD5 (5*NUM_GROUP + PIN_BASE + 29)
#define RK29_PIN5_PD6 (5*NUM_GROUP + PIN_BASE + 30)
#define RK29_PIN5_PD7 (5*NUM_GROUP + PIN_BASE + 31)
#define RK29_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0);
#define RK29_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1);
#define RK29_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2);
#define RK29_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3);
#define RK29_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4);
#define RK29_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5);
#define RK29_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6);
#define RK29_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7);
#define RK29_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8);
#define RK29_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9);
#define RK29_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10);
#define RK29_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11);
#define RK29_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12);
#define RK29_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13);
#define RK29_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14);
#define RK29_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15);
#define RK29_PIN6_PC0 (6*NUM_GROUP + PIN_BASE + 16);
#define RK29_PIN6_PC1 (6*NUM_GROUP + PIN_BASE + 17);
#define RK29_PIN6_PC2 (6*NUM_GROUP + PIN_BASE + 18);
#define RK29_PIN6_PC3 (6*NUM_GROUP + PIN_BASE + 19);
#define RK29_PIN6_PC4 (6*NUM_GROUP + PIN_BASE + 20);
#define RK29_PIN6_PC5 (6*NUM_GROUP + PIN_BASE + 21);
#define RK29_PIN6_PC6 (6*NUM_GROUP + PIN_BASE + 22);
#define RK29_PIN6_PC7 (6*NUM_GROUP + PIN_BASE + 23);
#define RK29_PIN6_PD0 (6*NUM_GROUP + PIN_BASE + 24);
#define RK29_PIN6_PD1 (6*NUM_GROUP + PIN_BASE + 25);
#define RK29_PIN6_PD2 (6*NUM_GROUP + PIN_BASE + 26);
#define RK29_PIN6_PD3 (6*NUM_GROUP + PIN_BASE + 27);
#define RK29_PIN6_PD4 (6*NUM_GROUP + PIN_BASE + 28);
#define RK29_PIN6_PD5 (6*NUM_GROUP + PIN_BASE + 29);
#define RK29_PIN6_PD6 (6*NUM_GROUP + PIN_BASE + 30);
#define RK29_PIN6_PD7 (6*NUM_GROUP + PIN_BASE + 31);
#define RK29_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0)
#define RK29_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1)
#define RK29_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2)
#define RK29_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3)
#define RK29_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4)
#define RK29_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
#define RK29_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
#define RK29_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
#define RK29_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
#define RK29_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
#define RK29_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
#define RK29_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11)
#define RK29_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12)
#define RK29_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13)
#define RK29_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
#define RK29_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)
#define RK29_PIN6_PC0 (6*NUM_GROUP + PIN_BASE + 16)
#define RK29_PIN6_PC1 (6*NUM_GROUP + PIN_BASE + 17)
#define RK29_PIN6_PC2 (6*NUM_GROUP + PIN_BASE + 18)
#define RK29_PIN6_PC3 (6*NUM_GROUP + PIN_BASE + 19)
#define RK29_PIN6_PC4 (6*NUM_GROUP + PIN_BASE + 20)
#define RK29_PIN6_PC5 (6*NUM_GROUP + PIN_BASE + 21)
#define RK29_PIN6_PC6 (6*NUM_GROUP + PIN_BASE + 22)
#define RK29_PIN6_PC7 (6*NUM_GROUP + PIN_BASE + 23)
#define RK29_PIN6_PD0 (6*NUM_GROUP + PIN_BASE + 24)
#define RK29_PIN6_PD1 (6*NUM_GROUP + PIN_BASE + 25)
#define RK29_PIN6_PD2 (6*NUM_GROUP + PIN_BASE + 26)
#define RK29_PIN6_PD3 (6*NUM_GROUP + PIN_BASE + 27)
#define RK29_PIN6_PD4 (6*NUM_GROUP + PIN_BASE + 28)
#define RK29_PIN6_PD5 (6*NUM_GROUP + PIN_BASE + 29)
#define RK29_PIN6_PD6 (6*NUM_GROUP + PIN_BASE + 30)
#define RK29_PIN6_PD7 (6*NUM_GROUP + PIN_BASE + 31)
#define ARCH_NR_GPIOS (NUM_GROUP*MAX_BANK)
@ -325,12 +326,12 @@ extern void __init rk29_gpio_irq_setup(void);
static inline int gpio_to_irq(unsigned gpio)
{
return gpio + NR_AIC_IRQS;
return (gpio + NR_AIC_IRQS);
}
static inline int irq_to_gpio(unsigned irq)
{
return irq - NR_AIC_IRQS;
return (irq - NR_AIC_IRQS);
}
#endif /* __ASSEMBLY__ */

128
arch/arm/mach-rk29/include/mach/rk29_nand.h Normal file
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@ -0,0 +1,128 @@
/*
* arch/arm/mach-rk29/include/mach/rk29_nand.h
*
* Copyright (C) 2010 RockChip, Inc.
* Author:
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_RK29_NAND_H
#define __ASM_ARCH_RK29_NAND_H
//BCHCTL寄存器
#define BCH_WR 0x0002
#define BCH_RST 0x0001
//FLCTL寄存器
#define FL_RDY (0x1<<20)
#define FL_LBA_EN (0x1<<11)
#define FL_COR_EN (0x1<<10)
#define FL_INT_EN (0x1<<9)
#define FL_INTCLR (0x1<<8)
#define FL_STMOD (0x1<<7)
#define FL_TRCNT (0x3<<5)
#define FL_STADDR (0x1<<4)
#define FL_BYPASS (0x1<<3)
#define FL_START (0x1<<2)
#define FL_RDN (0x1<<1)
#define FL_RST (0x1<<0)
//FMCTL寄存器
#define FMC_WP (0x1<<8)
#define FMC_FRDY (0x1<<9)
#define FMC_FRDY_INT_EN (0x1<<10)
#define FMC_FRDY_INT_CLR (0x1<<11)
//FMWAIT寄存器
#define FMW_RWCS_OFFSET 0
#define FMW_RWPW_OFFSET 5
#define FMW_RDY (0x1<<11)
#define FMW_CSRW_OFFSET 12
#define FMW_DLY_OFFSET 24//16
struct rk29_nand_timing {
unsigned int tCH; /* Enable signal hold time */
unsigned int tCS; /* Enable signal setup time */
unsigned int tWH; /* ND_nWE high duration */
unsigned int tWP; /* ND_nWE pulse time */
unsigned int tRH; /* ND_nRE high duration */
unsigned int tRP; /* ND_nRE pulse width */
unsigned int tR; /* ND_nWE high to ND_nRE low for read */
unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
};
struct rk29_nand_cmdset {
uint16_t read1;
uint16_t read2;
uint16_t program;
uint16_t read_status;
uint16_t read_id;
uint16_t erase;
uint16_t reset;
uint16_t lock;
uint16_t unlock;
uint16_t lock_status;
};
typedef volatile struct tagCHIP_IF
{
uint32_t data;
uint32_t addr;
uint32_t cmd;
uint32_t RESERVED[0x3d];
}CHIP_IF, *pCHIP_IF;
//NANDC Registers
typedef volatile struct tagNANDC
{
volatile uint32_t FMCTL;
volatile uint32_t FMWAIT;
volatile uint32_t FLCTL;
volatile uint32_t BCHCTL;
volatile uint32_t BCHST;
volatile uint32_t RESERVED1[(0x200-0x14)/4]; //FLR
volatile uint32_t spare[0x200/4];
volatile uint32_t FMCTL1;
volatile uint32_t FMWAIT1;
volatile uint32_t FLCTL1;
volatile uint32_t BCHCTL1;
volatile uint32_t BCHST1;
volatile uint32_t RESERVED2[(0x200-0x14)/4];
volatile uint32_t RESERVED3[0x200/4];
volatile CHIP_IF chip[8];
volatile uint32_t buf[0x800/4];
}NANDC, *pNANDC;
struct rk29_nand_flash {
const struct rk29_nand_timing *timing; /* NAND Flash timing */
const struct rk29_nand_cmdset *cmdset;
uint32_t page_per_block; /* Pages per block (PG_PER_BLK) */
uint32_t page_size; /* Page size in bytes (PAGE_SZ) */
uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */
uint32_t num_blocks; /* Number of physical blocks in Flash */
uint32_t chip_id;
};
struct rk29_nand_platform_data {
int width; /* data bus width in bytes */
int hw_ecc; /* 1:hw ecc, 0: soft ecc */
struct mtd_partition *parts;
unsigned int nr_parts;
size_t num_flash;
int (*io_init)(void);
int (*io_deinit)(void);
};
#endif /* __ASM_ARCH_RK29_NAND_H */

42
arch/arm/mach-rk29/include/mach/vpu.h Normal file
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@ -0,0 +1,42 @@
/* arch/arm/mach-rk29/include/mach/vcodec.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK29_VPU_H
#define __ARCH_ARM_MACH_RK29_VPU_H
#include <linux/ioctl.h> /* needed for the _IOW etc stuff used later */
/*
* Ioctl definitions
*/
/* Use 'k' as magic number */
#define VPU_IOC_MAGIC 'k'
#define VPU_IOC_PP_INSTANCE _IO(VPU_IOC_MAGIC, 1) /* the client is pp instance */
#define VPU_IOC_HW_PERFORMANCE _IO(VPU_IOC_MAGIC, 2) /* get monotonic time (struct timespec) for HW performance */
#define VPU_IOC_GHWOFFSET _IOR(VPU_IOC_MAGIC, 3, unsigned long *)
#define VPU_IOC_GHWIOSIZE _IOR(VPU_IOC_MAGIC, 4, unsigned int *)
#define VPU_IOC_CLI _IO(VPU_IOC_MAGIC, 5)
#define VPU_IOC_STI _IO(VPU_IOC_MAGIC, 6)
#define VPU_IOC_DEC_INSTANCE _IO(VPU_IOC_MAGIC, 7)
#define VPU_IOC_ENC_INSTANCE _IO(VPU_IOC_MAGIC, 8)
#define VPU_IOC_MAXNR 8
#endif

1
arch/arm/mach-rk29/io.c
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@ -45,6 +45,7 @@ static struct map_desc rk29_io_desc[] __initdata = {
RK29_DEVICE(GPIO4),
RK29_DEVICE(GPIO5),
RK29_DEVICE(GPIO6),
RK29_DEVICE(NANDC),
};
void __init rk29_map_common_io(void)

604
arch/arm/mach-rk29/vpu.c Normal file
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@ -0,0 +1,604 @@
/* arch/arm/mach-rk29/vpu.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifdef CONFIG_RK29_VPU_DEBUG
#define DEBUG
#define pr_fmt(fmt) "VPU: %s: " fmt, __func__
#else
#define pr_fmt(fmt) "VPU: " fmt
#endif
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/miscdevice.h>
#include <linux/mm.h>
#include <linux/poll.h>
#ifdef CONFIG_RK29_VPU_HW_PERFORMANCE
#include <linux/time.h>
#endif
#include <asm/uaccess.h>
#include <mach/irqs.h>
#include <mach/vpu.h>
#include <mach/rk29_iomap.h>
#define DEC_INTERRUPT_REGISTER 1
#define PP_INTERRUPT_REGISTER 60
#define ENC_INTERRUPT_REGISTER 1
#define DEC_INTERRUPT_BIT 0x100
#define PP_INTERRUPT_BIT 0x100
#define ENC_INTERRUPT_BIT 0x1
#define DEC_IO_SIZE ((100 + 1) * 4) /* bytes */
#define ENC_IO_SIZE (96 * 4) /* bytes */
static const u16 dec_hw_ids[] = { 0x8190, 0x8170, 0x9170, 0x9190, 0x6731 };
static const u16 enc_hw_ids[] = { 0x6280, 0x7280, 0x8270 };
struct vpu_device {
unsigned long iobaseaddr;
unsigned int iosize;
volatile u32 *hwregs;
unsigned int irq;
};
static struct vpu_device dec_dev;
static struct vpu_device pp_dev;
static struct vpu_device enc_dev;
struct vpu_client {
struct vpu_device *dev;
s32 event_count; /* for user */
atomic_t event; /* inc by irq */
struct fasync_struct *async_queue;
wait_queue_head_t wait;
struct file *filp; /* for /proc/vpu */
#ifdef CONFIG_RK29_VPU_HW_PERFORMANCE
struct timespec end_time;
#endif
};
static struct vpu_client client;
static void vpu_release_io(void);
#ifdef CONFIG_RK29_VPU_DEBUG
static void dump_regs(struct vpu_device *);
#endif
static long vpu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int err = 0;
struct vpu_device *dev = client.dev;
pr_debug("ioctl cmd 0x%08x\n", cmd);
if (!dev)
return -EINVAL;
/*
* extract the type and number bitfields, and don't decode
* wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
*/
if (_IOC_TYPE(cmd) != VPU_IOC_MAGIC)
return -ENOTTY;
if (_IOC_NR(cmd) > VPU_IOC_MAXNR)
return -ENOTTY;
/*
* the direction is a bitmask, and VERIFY_WRITE catches R/W
* transfers. `Type' is user-oriented, while
* access_ok is kernel-oriented, so the concept of "read" and
* "write" is reversed
*/
if (_IOC_DIR(cmd) & _IOC_READ)
err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
else if (_IOC_DIR(cmd) & _IOC_WRITE)
err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
if (err)
return -EFAULT;
switch (cmd) {
case VPU_IOC_CLI:
disable_irq(dev->irq);
break;
case VPU_IOC_STI:
enable_irq(dev->irq);
break;
case VPU_IOC_GHWOFFSET:
put_user(dev->iobaseaddr, (unsigned long *)arg);
break;
case VPU_IOC_GHWIOSIZE:
put_user(dev->iosize, (unsigned int *)arg);
break;
case VPU_IOC_DEC_INSTANCE:
client.dev = &dec_dev;
break;
case VPU_IOC_PP_INSTANCE:
client.dev = &pp_dev;
break;
case VPU_IOC_ENC_INSTANCE:
client.dev = &enc_dev;
break;
#ifdef CONFIG_RK29_VPU_HW_PERFORMANCE
case VPU_IOC_HW_PERFORMANCE:
put_user(client.end_time.tv_sec, (long *)arg);
put_user(client.end_time.tv_nsec, (long *)arg + 1);
break;
#endif
}
return 0;
}
static int vpu_open(struct inode *inode, struct file *filp)
{
if (client.filp)
return -EBUSY;
client.dev = &dec_dev;
client.event_count = atomic_read(&client.event);
client.filp = filp;
pr_debug("dev opened\n");
return nonseekable_open(inode, filp);
}
static int vpu_fasync(int fd, struct file *filp, int mode)
{
return fasync_helper(fd, filp, mode, &client.async_queue);
}
static int vpu_release(struct inode *inode, struct file *filp)
{
#ifdef CONFIG_RK29_VPU_DEBUG
dump_regs(&enc_dev); /* dump the regs */
dump_regs(&dec_dev); /* dump the regs */
#endif
/* remove this filp from the asynchronusly notified filp's */
vpu_fasync(-1, filp, 0);
client.async_queue = NULL;
client.filp = NULL;
pr_debug("dev closed\n");
return 0;
}
static int vpu_check_hw_id(struct vpu_device * dev, const u16 *hwids, size_t num)
{
u32 hwid = readl(dev->hwregs);
pr_info("HW ID = 0x%08x\n", hwid);
hwid = (hwid >> 16) & 0xFFFF; /* product version only */
while (num--) {
if (hwid == hwids[num]) {
pr_info("Compatible HW found at 0x%08lx\n", dev->iobaseaddr);
return 1;
}
}
pr_info("No Compatible HW found at 0x%08lx\n", dev->iobaseaddr);
return 0;
}
static int vpu_reserve_io(void)
{
if (!request_mem_region(dec_dev.iobaseaddr, dec_dev.iosize, "hx170dec")) {
pr_info("failed to reserve dec HW regs\n");
return -EBUSY;
}
dec_dev.hwregs =
(volatile u32 *)ioremap_nocache(dec_dev.iobaseaddr, dec_dev.iosize);
if (dec_dev.hwregs == NULL) {
pr_info("failed to ioremap dec HW regs\n");
goto err;
}
/* check for correct HW */
if (!vpu_check_hw_id(&dec_dev, dec_hw_ids, ARRAY_SIZE(dec_hw_ids))) {
goto err;
}
if (!request_mem_region(enc_dev.iobaseaddr, enc_dev.iosize, "hx280enc")) {
pr_info("failed to reserve enc HW regs\n");
goto err;
}
enc_dev.hwregs =
(volatile u32 *)ioremap_nocache(enc_dev.iobaseaddr, enc_dev.iosize);
if (enc_dev.hwregs == NULL) {
pr_info("failed to ioremap enc HW regs\n");
goto err;
}
/* check for correct HW */
if (!vpu_check_hw_id(&enc_dev, enc_hw_ids, ARRAY_SIZE(enc_hw_ids))) {
goto err;
}
return 0;
err:
vpu_release_io();
return -EBUSY;
}
static void vpu_release_io(void)
{
if (dec_dev.hwregs)
iounmap((void *)dec_dev.hwregs);
release_mem_region(dec_dev.iobaseaddr, dec_dev.iosize);
if (enc_dev.hwregs)
iounmap((void *)enc_dev.hwregs);
release_mem_region(enc_dev.iobaseaddr, enc_dev.iosize);
}
static void vpu_event_notify(void)
{
atomic_inc(&client.event);
wake_up_interruptible(&client.wait);
if (client.async_queue)
kill_fasync(&client.async_queue, SIGIO, POLL_IN);
}
static irqreturn_t hx170dec_isr(int irq, void *dev_id)
{
unsigned int handled = 0;
struct vpu_device *dev = (struct vpu_device *) dev_id;
u32 irq_status_dec;
u32 irq_status_pp;
handled = 0;
/* interrupt status register read */
irq_status_dec = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
irq_status_pp = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
if (irq_status_dec & DEC_INTERRUPT_BIT) {
#ifdef CONFIG_RK29_VPU_HW_PERFORMANCE
ktime_get_ts(&client.end_time);
#endif
/* clear dec IRQ */
writel(irq_status_dec & (~DEC_INTERRUPT_BIT),
dev->hwregs + DEC_INTERRUPT_REGISTER);
vpu_event_notify();
pr_debug("DEC IRQ received!\n");
handled = 1;
}
if (irq_status_pp & PP_INTERRUPT_BIT) {
#ifdef CONFIG_RK29_VPU_HW_PERFORMANCE
ktime_get_ts(&client.end_time);
#endif
/* clear pp IRQ */
writel(irq_status_pp & (~DEC_INTERRUPT_BIT),
dev->hwregs + PP_INTERRUPT_REGISTER);
vpu_event_notify();
pr_debug("PP IRQ received!\n");
handled = 1;
}
if (!handled) {
pr_debug("IRQ received, but not x170's!\n");
}
return IRQ_RETVAL(handled);
}
static irqreturn_t hx280enc_isr(int irq, void *dev_id)
{
struct vpu_device *dev = (struct vpu_device *) dev_id;
u32 irq_status;
irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
if (irq_status & ENC_INTERRUPT_BIT) {
#ifdef CONFIG_RK29_VPU_HW_PERFORMANCE
ktime_get_ts(&client.end_time);
#endif
/* clear enc IRQ */
writel(irq_status & (~ENC_INTERRUPT_BIT),
dev->hwregs + ENC_INTERRUPT_REGISTER);
vpu_event_notify();
pr_debug("ENC IRQ handled!\n");
return IRQ_HANDLED;
} else {
pr_debug("ENC IRQ received, but NOT handled!\n");
return IRQ_NONE;
}
}
static void vpu_reset_dec_asic(struct vpu_device * dev)
{
unsigned int i, n = dev->iosize >> 2;
writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
for (i = 1; i < n; i++) {
writel(0, dev->hwregs + i);
}
}
static void vpu_reset_enc_asic(struct vpu_device * dev)
{
unsigned int i, n = dev->iosize >> 2;
writel(0, dev->hwregs + 14);
for (i = 4; i < n; i++) {
writel(0, dev->hwregs + i);
}
}
#ifdef CONFIG_RK29_VPU_DEBUG
static void dump_regs(struct vpu_device *dev)
{
unsigned int i, n = dev->iosize >> 2;
pr_debug("Reg Dump Start\n");
for (i = 0; i < n; i++) {
pr_debug("\tswreg%d = %08X\n", i, readl(dev->hwregs + i));
}
pr_debug("Reg Dump End\n");
}
#endif
static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
{
unsigned long pfn;
/* Only support the simple cases where we map in a register page. */
if (((vm->vm_end - vm->vm_start) > RK29_VCODEC_SIZE) || vm->vm_pgoff)
return -EINVAL;
vm->vm_flags |= VM_IO | VM_RESERVED;
vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
pfn = RK29_VCODEC_PHYS >> PAGE_SHIFT;
pr_debug("size = 0x%x, page no. = 0x%x\n",
(int)(vm->vm_end - vm->vm_start), (int)pfn);
return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start,
vm->vm_page_prot) ? -EAGAIN : 0;
}
static unsigned int vpu_poll(struct file *filep, poll_table *wait)
{
poll_wait(filep, &client.wait, wait);
if (client.event_count != atomic_read(&client.event))
return POLLIN | POLLRDNORM;
return 0;
}
static ssize_t vpu_read(struct file *filep, char __user *buf,
size_t count, loff_t *ppos)
{
DECLARE_WAITQUEUE(wait, current);
ssize_t retval;
s32 event_count;
if (count != sizeof(s32))
return -EINVAL;
add_wait_queue(&client.wait, &wait);
do {
set_current_state(TASK_INTERRUPTIBLE);
event_count = atomic_read(&client.event);
if (event_count != client.event_count) {
if (copy_to_user(buf, &event_count, count))
retval = -EFAULT;
else {
client.event_count = event_count;
retval = count;
}
break;
}
if (filep->f_flags & O_NONBLOCK) {
retval = -EAGAIN;
break;
}
if (signal_pending(current)) {
retval = -ERESTARTSYS;
break;
}
schedule();
} while (1);
__set_current_state(TASK_RUNNING);
remove_wait_queue(&client.wait, &wait);
return retval;
}
static const struct file_operations vpu_fops = {
.read = vpu_read,
.poll = vpu_poll,
.unlocked_ioctl = vpu_ioctl,
.mmap = vpu_mmap,
.open = vpu_open,
.release = vpu_release,
.fasync = vpu_fasync,
};
static struct miscdevice vpu_misc_device = {
.minor = MISC_DYNAMIC_MINOR,
.name = "vpu",
.fops = &vpu_fops,
};
static int __init vpu_init(void)
{
int ret;
pr_debug("baseaddr = 0x%08x vdpu irq = %d vepu irq = %d\n", RK29_VCODEC_PHYS, IRQ_VDPU, IRQ_VEPU);
dec_dev.iobaseaddr = RK29_VCODEC_PHYS + 0x200;
dec_dev.iosize = DEC_IO_SIZE;
dec_dev.irq = IRQ_VDPU;
enc_dev.iobaseaddr = RK29_VCODEC_PHYS;
enc_dev.iosize = ENC_IO_SIZE;
enc_dev.irq = IRQ_VEPU;
ret = vpu_reserve_io();
if (ret < 0) {
goto err_reserve_io;
}
pp_dev = dec_dev;
init_waitqueue_head(&client.wait);
atomic_set(&client.event, 0);
vpu_reset_dec_asic(&dec_dev); /* reset hardware */
vpu_reset_enc_asic(&enc_dev); /* reset hardware */
/* get the IRQ line */
ret = request_irq(IRQ_VDPU, hx170dec_isr, 0, "hx170dec", (void *)&dec_dev);
if (ret != 0) {
pr_err("can't request vdpu irq %d\n", IRQ_VDPU);
goto err_req_vdpu_irq;
}
ret = request_irq(IRQ_VEPU, hx280enc_isr, 0, "hx280enc", (void *)&enc_dev);
if (ret != 0) {
pr_err("can't request vepu irq %d\n", IRQ_VEPU);
goto err_req_vepu_irq;
}
ret = misc_register(&vpu_misc_device);
if (ret) {
pr_err("misc_register failed\n");
goto err_register;
}
pr_info("init success\n");
return 0;
err_register:
free_irq(IRQ_VEPU, (void *)&enc_dev);
err_req_vepu_irq:
free_irq(IRQ_VDPU, (void *)&dec_dev);
err_req_vdpu_irq:
vpu_release_io();
err_reserve_io:
pr_info("init failed\n");
return ret;
}
static void __exit vpu_exit(void)
{
/* clear dec IRQ */
writel(0, dec_dev.hwregs + DEC_INTERRUPT_REGISTER);
/* clear pp IRQ */
writel(0, dec_dev.hwregs + PP_INTERRUPT_REGISTER);
writel(0, enc_dev.hwregs + 14); /* disable HW */
/* clear enc IRQ */
writel(0, enc_dev.hwregs + ENC_INTERRUPT_REGISTER);
#ifdef CONFIG_RK29_VPU_DEBUG
dump_regs(&enc_dev); /* dump the regs */
dump_regs(&dec_dev); /* dump the regs */
#endif
misc_deregister(&vpu_misc_device);
free_irq(IRQ_VEPU, (void *)&enc_dev);
free_irq(IRQ_VDPU, (void *)&dec_dev);
vpu_release_io();
}
module_init(vpu_init);
module_exit(vpu_exit);
MODULE_LICENSE("GPL");
#ifdef CONFIG_PROC_FS
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
static int proc_vpu_show(struct seq_file *s, void *v)
{
unsigned int i, n;
if (client.filp) {
seq_printf(s, "Opened\n");
seq_printf(s, "%s instance\n", client.dev == &dec_dev ? "DEC" : client.dev == &pp_dev ? "PP" : "ENC");
} else {
seq_printf(s, "Closed\n");
}
seq_printf(s, "event_count %d event %d\n", client.event_count, atomic_read(&client.event));
#ifdef CONFIG_RK29_VPU_HW_PERFORMANCE
seq_printf(s, "end_time: %ld.%09ld\n", client.end_time.tv_sec, client.end_time.tv_nsec);
#endif
seq_printf(s, "\nENC Registers:\n");
n = enc_dev.iosize >> 2;
for (i = 0; i < n; i++) {
seq_printf(s, "\tswreg%d = %08X\n", i, readl(enc_dev.hwregs + i));
}
seq_printf(s, "\nDEC Registers:\n");
n = dec_dev.iosize >> 2;
for (i = 0; i < n; i++) {
seq_printf(s, "\tswreg%d = %08X\n", i, readl(dec_dev.hwregs + i));
}
return 0;
}
static int proc_vpu_open(struct inode *inode, struct file *file)
{
return single_open(file, proc_vpu_show, NULL);
}
static const struct file_operations proc_vpu_fops = {
.open = proc_vpu_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int __init vpu_proc_init(void)
{
proc_create("vpu", 0, NULL, &proc_vpu_fops);
return 0;
}
late_initcall(vpu_proc_init);
#endif /* CONFIG_PROC_FS */

8
drivers/input/touchscreen/xpt2046_cbn_ts.c
View File

@ -382,7 +382,7 @@ static int xpt2046_debounce(void *xpt, int data_idx, int *val)
static int average_val[2];
xpt2046printk("***>%s:%d,%d,%d,%d,%d,%d,%d,%d\n",__FUNCTION__,
xpt2046printk("***>%s:%d,%d,%d,%d,%ld,%d,%d,%d\n",__FUNCTION__,
data_idx,ts->last_read,
ts->read_cnt,ts->debounce_max,
abs(ts->last_read - *val),ts->debounce_tol,
@ -700,8 +700,6 @@ static int __devinit xpt2046_probe(struct spi_device *spi)
struct spi_transfer *x;
int vref;
int err;
int i;
if (!spi->irq) {
dev_dbg(&spi->dev, "no IRQ?\n");
@ -955,12 +953,14 @@ static struct spi_driver xpt2046_driver = {
static int __init xpt2046_init(void)
{
int ret;
xpt2046printk("Touch panel drive XPT2046 driver init...\n");
gADPoint.x = 0;
gADPoint.y = 0;
int ret = spi_register_driver(&xpt2046_driver);
ret = spi_register_driver(&xpt2046_driver);
if (ret)
{
printk("Register XPT2046 driver failed.\n");

10
drivers/mmc/card/block.c
View File

@ -235,11 +235,9 @@ static u32 get_card_status(struct mmc_card *card, struct request *req)
cmd.arg = card->rca << 16;
cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
err = mmc_wait_for_cmd(card->host, &cmd, 0);
#if 0 //[xjh] not printk,save time
if (err)
printk(KERN_ERR "%s: error %d sending status comand",
req->rq_disk->disk_name, err);
#endif
return cmd.resp[0];
}
@ -378,9 +376,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
* until later as we need to wait for the card to leave
* programming mode even when things go wrong.
*/
#if 1/*[xjh] do not retry with cmd17*/
if (brq.cmd.error || brq.data.error || brq.stop.error) {
if (brq.data.blocks > 1 && rq_data_dir(req) == READ) {
/* Redo read one sector at a time */
printk(KERN_WARNING "%s: retrying using single "
@ -388,14 +384,11 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
disable_multi = 1;
continue;
}
status = get_card_status(card, req);
} else if (disable_multi == 1) {
disable_multi = 0;
}
#endif
#if 0 //[xjh] not printk,save time
if (brq.cmd.error) {
printk(KERN_ERR "%s: error %d sending read/write "
"command, response %#x, card status %#x\n",
@ -420,7 +413,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
req->rq_disk->disk_name, brq.stop.error,
brq.stop.resp[0], status);
}
#endif
if (!mmc_host_is_spi(card->host) && rq_data_dir(req) != READ) {
do {
@ -453,7 +445,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
}
if (brq.cmd.error || brq.stop.error || brq.data.error) {
#if 1/*[xjh] do not retry with cmd17*/
if (rq_data_dir(req) == READ) {
/*
* After an error, we redo I/O one sector at a
@ -465,7 +456,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
spin_unlock_irq(&md->lock);
continue;
}
#endif
goto cmd_err;
}

9
drivers/mmc/core/bus.c
View File

@ -268,7 +268,6 @@ int mmc_add_card(struct mmc_card *card)
return 0;
}
extern int sdmmc0_disable_Irq_ForRemoval;
/*
* Unregister a new MMC card with the driver model, and
* (eventually) free it.
@ -278,7 +277,6 @@ void mmc_remove_card(struct mmc_card *card)
#ifdef CONFIG_DEBUG_FS
mmc_remove_card_debugfs(card);
#endif
unsigned long flags;
if (mmc_card_present(card)) {
if (mmc_host_is_spi(card->host)) {
@ -288,13 +286,6 @@ void mmc_remove_card(struct mmc_card *card)
printk(KERN_INFO "%s: card %04x removed\n",
mmc_hostname(card->host), card->rca);
}
if( !strncmp( mmc_hostname(card->host) ,"mmc0" , strlen("mmc0")) )
{
local_irq_save(flags);
sdmmc0_disable_Irq_ForRemoval = 1; //close the IRQ for insertion or removal
local_irq_restore(flags);
}
device_del(&card->dev);
}

98
drivers/mmc/core/core.c
View File

@ -1059,7 +1059,7 @@ void mmc_detect_change(struct mmc_host *host, unsigned long delay)
EXPORT_SYMBOL(mmc_detect_change);
#if 0
void mmc_rescan(struct work_struct *work)
{
struct mmc_host *host =
@ -1154,102 +1154,6 @@ void mmc_rescan(struct work_struct *work)
if (host->caps & MMC_CAP_NEEDS_POLL)
mmc_schedule_delayed_work(&host->detect, HZ);
}
#else
void mmc_rescan(struct work_struct *work)
{
struct mmc_host *host =
container_of(work, struct mmc_host, detect.work);
u32 ocr;
int err;
int extend_wakelock = 0;
mmc_bus_get(host);
if(host->bus_ops == NULL)
{
/* detect a newly inserted card */
/*
* Only we can add a new handler, so it's safe to
* release the lock here.
*/
mmc_bus_put(host);
if (host->ops->get_cd && host->ops->get_cd(host) == 0)
goto out;
mmc_claim_host(host);
mmc_power_up(host);
mmc_go_idle(host);
mmc_send_if_cond(host, host->ocr_avail);
/*
* First we search for SDIO...
*/
err = mmc_send_io_op_cond(host, 0, &ocr);
if (!err) {
if (mmc_attach_sdio(host, ocr))
mmc_power_off(host);
extend_wakelock = 1;
goto out;
}
/*
* ...then normal SD...
*/
err = mmc_send_app_op_cond(host, 0, &ocr);
if (!err) {
if (mmc_attach_sd(host, ocr))
mmc_power_off(host);
extend_wakelock = 1;
goto out;
}
/*
* ...and finally MMC.
*/
err = mmc_send_op_cond(host, 0, &ocr);
if (!err) {
if (mmc_attach_mmc(host, ocr))
mmc_power_off(host);
extend_wakelock = 1;
goto out;
}
mmc_release_host(host);
mmc_power_off(host);
}
else
{
/* if there is a card registered, check whether it is still present */
if ((host->bus_ops != NULL) && host->bus_ops->detect && !host->bus_dead)
host->bus_ops->detect(host);
/* If the card was removed the bus will be marked
* as dead - extend the wakelock so userspace
* can respond */
if (host->bus_dead)
extend_wakelock = 1;
mmc_bus_put(host);
}
out:
if (extend_wakelock)
wake_lock_timeout(&mmc_delayed_work_wake_lock, HZ / 2);
else
wake_unlock(&mmc_delayed_work_wake_lock);
if (host->caps & MMC_CAP_NEEDS_POLL)
mmc_schedule_delayed_work(&host->detect, HZ);
}
#endif
void mmc_start_host(struct mmc_host *host)
{

7
drivers/mmc/core/mmc.c
View File

@ -660,9 +660,6 @@ static void mmc_attach_bus_ops(struct mmc_host *host)
int mmc_attach_mmc(struct mmc_host *host, u32 ocr)
{
int err;
unsigned long flags;
extern int sdmmc0_disable_Irq_ForRemoval;
BUG_ON(!host);
WARN_ON(!host->claimed);
@ -711,10 +708,6 @@ int mmc_attach_mmc(struct mmc_host *host, u32 ocr)
err = mmc_add_card(host->card);
if (err)
goto remove_card;
local_irq_save(flags);
sdmmc0_disable_Irq_ForRemoval = 0; //close the IRQ for insertion or removal
local_irq_restore(flags);
return 0;

23
drivers/mmc/host/Kconfig
View File

@ -27,6 +27,29 @@ if SDMMC_RK2818
This supports the use of the SDMMC1 controller on rk2818 processors.
endif
config SDMMC_RK29
tristate "RK29 SDMMC controller suppport"
depends on ARCH_RK29
help
This selects the RK29 SDMMC controller.
SDMMC0 used for sd/mmc card, and SDMMC1 used for sdio.
if SDMMC_RK29
comment "Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1."
config SDMMC0_RK29
tristate "RK29 SDMMC0 controller support(sdmmc)"
default y
depends on ARCH_RK29
help
This supports the use of the SDMMC0 controller on Rk29 processors.
config SDMMC1_RK29
tristate "RK29 SDMMC1 controller support(sdio)"
default y
depends on ARCH_RK29
help
This supports the use of the SDMMC1 controller on Rk29 processors.
endif
config MMC_ARMMMCI
tristate "ARM AMBA Multimedia Card Interface support"
depends on ARM_AMBA

1
drivers/mmc/host/Makefile
View File

@ -6,6 +6,7 @@ ifeq ($(CONFIG_MMC_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG
endif
obj-$(CONFIG_SDMMC_RK29) += rk29_sdmmc.o
obj-$(CONFIG_SDMMC_RK2818) += rk2818-sdmmc.o
obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
obj-$(CONFIG_MMC_PXA) += pxamci.o

2
drivers/mmc/host/rk2818-sdmmc.h
View File

@ -126,7 +126,7 @@
/* Specifies how often in millisecs to poll for card removal-insertion changes
* when the timer switch is open */
#define RK28_SDMMC0_SWITCH_POLL_DELAY 3500
#define RK_SDMMC0_SWITCH_POLL_DELAY 3500
#endif

1484
drivers/mmc/host/rk29_sdmmc.c Normal file
View File

File diff suppressed because it is too large Load Diff

5
drivers/mtd/nand/Kconfig
View File

@ -365,6 +365,11 @@ config MTD_NAND_RK2818
depends on ARCH_RK2818
help
This enables the NAND flash controller on the RK2818 SoC
config MTD_NAND_RK29
tristate "NAND Flash support for RK29sdk"
depends on ARCH_RK29
help
This enables the NAND flash controller on the RK29 SoC
config MTD_NAND_PXA3xx
tristate "Support for NAND flash devices on PXA3xx"

2
drivers/mtd/nand/Makefile
View File

@ -43,5 +43,5 @@ obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o
obj-$(CONFIG_MTD_NAND_W90P910) += w90p910_nand.o
obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
obj-$(CONFIG_MTD_NAND_RK2818) += rk2818_nand.o
obj-$(CONFIG_MTD_NAND_RK29) += rk29_nand.o
nand-objs := nand_base.o nand_bbt.o

1096
drivers/mtd/nand/rk29_nand.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/staging/Kconfig Normal file → Executable file
View File

@ -130,5 +130,7 @@ source "drivers/staging/rk2818/rk2818_dsp/Kconfig"
source "drivers/staging/rk2818/rk1000_control/Kconfig"
source "drivers/staging/rk2818/rk2818_power/Kconfig"
source "drivers/staging/rk29/vivante/Kconfig"
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING

1
drivers/staging/Makefile Normal file → Executable file
View File

@ -48,3 +48,4 @@ obj-$(CONFIG_RK2818_DSP) += rk2818/rk2818_dsp/
obj-$(CONFIG_RK1000_CONTROL) += rk2818/rk1000_control/
obj-$(CONFIG_RK1000_TVOUT) += rk2818/rk1000_tv/
obj-$(CONFIG_RK2818_POWER) += rk2818/rk2818_power/
obj-$(CONFIG_VIVANTE) += rk29/vivante/

171
drivers/staging/rk29/vivante/Kbuild_ Normal file
View File

@ -0,0 +1,171 @@
##############################################################################
#
# Copyright (C) 2005 - 2010 by Vivante Corp.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the license, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
##############################################################################
#
# Linux build file for kernel HAL driver.
#
include $(AQROOT)/config
DRIVER_OUT_DIR = hal/driver
KERNEL_DIR ?= $(TOOL_DIR)/kernel
OS_KERNEL_DIR := hal/os/linux/kernel
ARCH_KERNEL_DIR := arch/$(notdir $(AQARCH))/hal/kernel
HAL_KERNEL_DIR := hal/kernel
EXTRA_CFLAGS += -Werror
OBJS := $(OS_KERNEL_DIR)/gc_hal_kernel_debug.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_device.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_driver.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_linux.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_os.o
ifeq ($(USE_3D_VG), 1)
OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_event.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o
OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o
else
OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_interrupt.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o
OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o \
$(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware_command.o
endif
ifeq ($(KERNELRELEASE), )
.PHONY: all clean install
# Define targets.
all:
@mkdir -p $(DRIVER_OUT_DIR)
@make V=$(V) ARCH=$(ARCH_TYPE) -C $(KERNEL_DIR) SUBDIRS=`pwd` modules
clean:
@rm -rf $(OBJS)
@rm -rf $(DRIVER_OUT_DIR)
@rm -rf modules.order Module.symvers
install: all
@mkdir -p $(SDK_DIR)/drivers
@cp $(DRIVER_OUT_DIR)/galcore.ko $(SDK_DIR)/drivers
else
EXTRA_CFLAGS += -DLINUX -DDRIVER
ifeq ($(ENUM_WORKAROUND), 1)
EXTRA_CFLAGS += -DENUM_WORKAROUND=1
else
EXTRA_CFLAGS += -DENUM_WORKAROUND=0
endif
ifeq ($(FLAREON),1)
EXTRA_CFLAGS += -DFLAREON
endif
ifeq ($(DEBUG), 1)
EXTRA_CFLAGS += -DDBG=1 -DDEBUG -D_DEBUG
else
EXTRA_CFLAGS += -DDBG=0
endif
ifeq ($(NO_DMA_COHERENT), 1)
EXTRA_CFLAGS += -DNO_DMA_COHERENT
endif
ifeq ($(ENABLE_ARM_L2_CACHE), 1)
EXTRA_CFLAGS += -DENABLE_ARM_L2_CACHE=1
else
EXTRA_CFLAGS += -DENABLE_ARM_L2_CACHE=0
endif
ifeq ($(CONFIG_DOVE_GPU), 1)
EXTRA_CFLAGS += -DCONFIG_DOVE_GPU=1
endif
ifeq ($(gcdNO_POWER_MANAGEMENT), 1)
EXTRA_CFLAGS += -DgcdNO_POWER_MANAGEMENT=1
else
EXTRA_CFLAGS += -DgcdNO_POWER_MANAGEMENT=0
endif
ifneq ($(USE_PLATFORM_DRIVER), 0)
EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1
else
EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0
endif
ifeq ($(USE_PROFILER), 1)
EXTRA_CFLAGS += -DVIVANTE_PROFILER=1
else
EXTRA_CFLAGS += -DVIVANTE_PROFILER=0
endif
ifeq ($(ANDROID), 1)
EXTRA_CFLAGS += -DANDROID=1
endif
ifeq ($(ENABLE_GPU_CLOCK_BY_DRIVER), 1)
EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=1
else
EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=0
endif
ifeq ($(USE_NEW_LINUX_SIGNAL), 1)
EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=1
else
EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=0
endif
ifeq ($(NO_USER_DIRECT_ACCESS_FROM_KERNEL), 1)
EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=1
else
EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=0
endif
EXTRA_CFLAGS += -I$(AQROOT)/hal/inc
EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel
EXTRA_CFLAGS += -I$(AQARCH)/hal/kernel
EXTRA_CFLAGS += -I$(AQARCH)/cmodel/inc
EXTRA_CFLAGS += -I$(AQROOT)/hal/user
obj-m = $(DRIVER_OUT_DIR)/galcore.o
$(DRIVER_OUT_DIR)/galcore-objs = $(OBJS)
endif

7
drivers/staging/rk29/vivante/Kconfig Normal file
View File

@ -0,0 +1,7 @@
menu "GPU Vivante"
config VIVANTE
tristate "ROCKCHIP Vivante GPU"
default y
help
Vivante GPU module.
endmenu

202
drivers/staging/rk29/vivante/Makefile Normal file
View File

@ -0,0 +1,202 @@
##############################################################################
#
# Copyright (C) 2005 - 2010 by Vivante Corp.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the license, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
##############################################################################
#
# Linux build file for kernel HAL driver.
#
################################################################
# Arch.
ARCH_TYPE ?= arm
CPU_TYPE ?= arm920
CPU_ARCH ?= 0
STATIC_LINK ?= 0
EGL_API_FB ?= 0
USE_VDK ?= 0
USE_PROFILER ?= 0
USE_SW_FB ?= 0
USE_3D_VG =1
ABI ?= 0
ANDROID ?= 0
EGL_API_ANDROID ?= 0
ENUM_WORKAROUND ?= 0
ENDIANNESS ?=
QNX ?= 0
LINUX_OABI ?= 0
USE_ARMCC ?= 0
ifeq ($(LINUX_OABI), 1)
ABI ?= 0
else
ABI ?= aapcs-linux
endif
################################################################
# Force to use dma_coherent_* stuff.
NO_DMA_COHERENT ?= 0
################################################################
# Set this value to 1 if you are using ARM L2 cache.
ENABLE_ARM_L2_CACHE = 0
################################################################
# Set this value to 1 if you are using DOVE board.
CONFIG_DOVE_GPU = 0
ENABLE_GPU_CLOCK_BY_DRIVER = 0
AQROOT ?= drivers/staging/rk29/vivante
AQARCH ?= $(AQROOT)/arch/XAQ2
#include $(AQROOT)/config
ARCH_TYPE ?= arm
SDK_DIR ?= $(AQROOT)/build/sdk
USE_3D_VG = 1
DEBUG = 1
#DRIVER_OUT_DIR = hal/driver
#KERNEL_DIR ?= $(TOOL_DIR)/kernel
OS_KERNEL_DIR := hal/os/linux/kernel
ARCH_KERNEL_DIR := arch/XAQ2/hal/kernel
HAL_KERNEL_DIR := hal/kernel
EXTRA_CFLAGS += -Werror
OBJS := $(OS_KERNEL_DIR)/gc_hal_kernel_debug.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_device.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_driver.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_linux.o \
$(OS_KERNEL_DIR)/gc_hal_kernel_os.o
ifeq ($(USE_3D_VG), 1)
OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_event.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o
OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o
else
OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_interrupt.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
$(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o
OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o \
$(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware_command.o
endif
EXTRA_CFLAGS += -DLINUX -DDRIVER
ifeq ($(ENUM_WORKAROUND), 1)
EXTRA_CFLAGS += -DENUM_WORKAROUND=1
else
EXTRA_CFLAGS += -DENUM_WORKAROUND=0
endif
ifeq ($(FLAREON),1)
EXTRA_CFLAGS += -DFLAREON
endif
ifeq ($(DEBUG), 1)
EXTRA_CFLAGS += -DDBG=1 -DDEBUG -D_DEBUG
else
EXTRA_CFLAGS += -DDBG=0
endif
ifeq ($(NO_DMA_COHERENT), 1)
EXTRA_CFLAGS += -DNO_DMA_COHERENT
endif
ifeq ($(ENABLE_ARM_L2_CACHE), 1)
EXTRA_CFLAGS += -DENABLE_ARM_L2_CACHE=1
else
EXTRA_CFLAGS += -DENABLE_ARM_L2_CACHE=0
endif
ifeq ($(CONFIG_DOVE_GPU), 1)
EXTRA_CFLAGS += -DCONFIG_DOVE_GPU=1
endif
ifeq ($(gcdNO_POWER_MANAGEMENT), 1)
EXTRA_CFLAGS += -DgcdNO_POWER_MANAGEMENT=1
else
EXTRA_CFLAGS += -DgcdNO_POWER_MANAGEMENT=0
endif
ifneq ($(USE_PLATFORM_DRIVER), 0)
EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1
else
EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0
endif
ifeq ($(USE_PROFILER), 1)
EXTRA_CFLAGS += -DVIVANTE_PROFILER=1
else
EXTRA_CFLAGS += -DVIVANTE_PROFILER=0
endif
ifeq ($(ANDROID), 1)
EXTRA_CFLAGS += -DANDROID=1
endif
ifeq ($(ENABLE_GPU_CLOCK_BY_DRIVER), 1)
EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=1
else
EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=0
endif
ifeq ($(USE_NEW_LINUX_SIGNAL), 1)
EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=1
else
EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=0
endif
ifeq ($(NO_USER_DIRECT_ACCESS_FROM_KERNEL), 1)
EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=1
else
EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=0
endif
EXTRA_CFLAGS += -I$(AQROOT)/hal/inc
EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel
EXTRA_CFLAGS += -I$(AQARCH)/hal/kernel
EXTRA_CFLAGS += -I$(AQARCH)/cmodel/inc
EXTRA_CFLAGS += -I$(AQROOT)/hal/user
obj-$(CONFIG_VIVANTE) += galcore.o
galcore-objs := $(OBJS)

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_kernel_hardware_h_
#define __gc_hal_kernel_hardware_h_
#ifdef __cplusplus
extern "C" {
#endif
/* gckHARDWARE object. */
struct _gckHARDWARE
{
/* Object. */
gcsOBJECT object;
/* Pointer to gctKERNEL object. */
gckKERNEL kernel;
/* Pointer to gctOS object. */
gckOS os;
/* Chip characteristics. */
gceCHIPMODEL chipModel;
gctUINT32 chipRevision;
gctUINT32 chipFeatures;
gctUINT32 chipMinorFeatures0;
gctUINT32 chipMinorFeatures1;
gctBOOL allowFastClear;
gctBOOL allowCompression;
gctUINT32 powerBaseAddress;
gctBOOL extraEventStates;
gctUINT32 streamCount;
gctUINT32 registerMax;
gctUINT32 threadCount;
gctUINT32 shaderCoreCount;
gctUINT32 vertexCacheSize;
gctUINT32 vertexOutputBufferSize;
/* Big endian */
gctBOOL bigEndian;
/* Chip status */
gctPOINTER powerMutex;
gctUINT32 powerProcess;
gctUINT32 powerThread;
gceCHIPPOWERSTATE chipPowerState;
gctUINT32 lastWaitLink;
};
gceSTATUS
gckHARDWARE_GetBaseAddress(
IN gckHARDWARE Hardware,
OUT gctUINT32_PTR BaseAddress
);
gceSTATUS
gckHARDWARE_NeedBaseAddress(
IN gckHARDWARE Hardware,
IN gctUINT32 State,
OUT gctBOOL_PTR NeedBase
);
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_kernel_hardware_h_ */

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##############################################################################
#
# Copyright (C) 2005 - 2010 by Vivante Corp.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the license, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
##############################################################################
#
# Linux build file for architecture dependent kernel HAL layer.
#
#
################################################################################
# Include common definitions.
include $(AQROOT)/makefile.linux.def
################################################################################
# Define a shortcut for the main target.
STATIC = 1
TARGET_NAME = libhalarchkernel.a
################################################################################
# Supply additional include directories.
INCLUDE += -I$(AQROOT)/hal/inc
INCLUDE += -I$(AQROOT)/hal/kernel
INCLUDE += -I$(AQARCH)/hal/kernel
INCLUDE += -I$(AQARCH)/cmodel/inc
CFLAGS += $(INCLUDE) -Werror -ansi
################################################################################
# Describe object files.
OBJECTS = $(OBJ_DIR)/gc_hal_kernel_hardware.o
include $(AQROOT)/common.target

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##############################################################################
#
# Copyright (C) 2005 - 2010 by Vivante Corp.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the license, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
##############################################################################
ARCH_TYPE ?= arm
SDK_DIR ?= $(AQROOT)/build/sdk
USE_3D_VG = 1

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_driver_h_
#define __gc_hal_driver_h_
#include "gc_hal_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************\
******************************* I/O Control Codes ******************************
\******************************************************************************/
#define gcvHAL_CLASS "galcore"
#define IOCTL_GCHAL_INTERFACE 30000
#define IOCTL_GCHAL_KERNEL_INTERFACE 30001
#define IOCTL_GCHAL_TERMINATE 30002
/******************************************************************************\
********************************* Command Codes ********************************
\******************************************************************************/
typedef enum _gceHAL_COMMAND_CODES
{
/* Generic query. */
gcvHAL_QUERY_VIDEO_MEMORY,
gcvHAL_QUERY_CHIP_IDENTITY,
/* Contiguous memory. */
gcvHAL_ALLOCATE_NON_PAGED_MEMORY,
gcvHAL_FREE_NON_PAGED_MEMORY,
gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY,
gcvHAL_FREE_CONTIGUOUS_MEMORY,
/* Video memory allocation. */
gcvHAL_ALLOCATE_VIDEO_MEMORY, /* Enforced alignment. */
gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY, /* No alignment. */
gcvHAL_FREE_VIDEO_MEMORY,
/* Physical-to-logical mapping. */
gcvHAL_MAP_MEMORY,
gcvHAL_UNMAP_MEMORY,
/* Logical-to-physical mapping. */
gcvHAL_MAP_USER_MEMORY,
gcvHAL_UNMAP_USER_MEMORY,
/* Surface lock/unlock. */
gcvHAL_LOCK_VIDEO_MEMORY,
gcvHAL_UNLOCK_VIDEO_MEMORY,
/* Event queue. */
gcvHAL_EVENT_COMMIT,
gcvHAL_USER_SIGNAL,
gcvHAL_SIGNAL,
gcvHAL_WRITE_DATA,
gcvHAL_COMMIT,
gcvHAL_STALL,
gcvHAL_READ_REGISTER,
gcvHAL_WRITE_REGISTER,
gcvHAL_GET_PROFILE_SETTING,
gcvHAL_SET_PROFILE_SETTING,
gcvHAL_READ_ALL_PROFILE_REGISTERS,
gcvHAL_PROFILE_REGISTERS_2D,
/* Power management. */
gcvHAL_SET_POWER_MANAGEMENT_STATE,
gcvHAL_QUERY_POWER_MANAGEMENT_STATE,
gcvHAL_GET_BASE_ADDRESS,
gcvHAL_SET_IDLE, /* reserved */
/* Queries. */
gcvHAL_QUERY_KERNEL_SETTINGS,
/* Reset. */
gcvHAL_RESET,
/* Map physical address into handle. */
gcvHAL_MAP_PHYSICAL,
/* Debugger stuff. */
gcvHAL_DEBUG,
/* Cache stuff. */
gcvHAL_CACHE,
}
gceHAL_COMMAND_CODES;
/******************************************************************************\
****************************** Interface Structure *****************************
\******************************************************************************/
#define gcdMAX_PROFILE_FILE_NAME 128
typedef struct _gcsHAL_INTERFACE
{
/* Command code. */
gceHAL_COMMAND_CODES command;
/* Status value. */
gceSTATUS status;
/* Handle to this interface channel. */
gctHANDLE handle;
/* Pid of the client. */
gctUINT32 pid;
/* Union of command structures. */
union _u
{
/* gcvHAL_GET_BASE_ADDRESS */
struct _gcsHAL_GET_BASE_ADDRESS
{
/* Physical memory address of internal memory. */
OUT gctUINT32 baseAddress;
}
GetBaseAddress;
/* gcvHAL_QUERY_VIDEO_MEMORY */
struct _gcsHAL_QUERY_VIDEO_MEMORY
{
/* Physical memory address of internal memory. */
OUT gctPHYS_ADDR internalPhysical;
/* Size in bytes of internal memory.*/
OUT gctSIZE_T internalSize;
/* Physical memory address of external memory. */
OUT gctPHYS_ADDR externalPhysical;
/* Size in bytes of external memory.*/
OUT gctSIZE_T externalSize;
/* Physical memory address of contiguous memory. */
OUT gctPHYS_ADDR contiguousPhysical;
/* Size in bytes of contiguous memory.*/
OUT gctSIZE_T contiguousSize;
}
QueryVideoMemory;
/* gcvHAL_QUERY_CHIP_IDENTITY */
struct _gcsHAL_QUERY_CHIP_IDENTITY
{
/* Chip model. */
OUT gceCHIPMODEL chipModel;
/* Revision value.*/
OUT gctUINT32 chipRevision;
/* Supported feature fields. */
OUT gctUINT32 chipFeatures;
/* Supported minor feature fields. */
OUT gctUINT32 chipMinorFeatures;
/* Supported minor feature 1 fields. */
OUT gctUINT32 chipMinorFeatures1;
/* Number of streams supported. */
OUT gctUINT32 streamCount;
/* Total number of temporary registers per thread. */
OUT gctUINT32 registerMax;
/* Maximum number of threads. */
OUT gctUINT32 threadCount;
/* Number of shader cores. */
OUT gctUINT32 shaderCoreCount;
/* Size of the vertex cache. */
OUT gctUINT32 vertexCacheSize;
/* Number of entries in the vertex output buffer. */
OUT gctUINT32 vertexOutputBufferSize;
}
QueryChipIdentity;
/* gcvHAL_MAP_MEMORY */
struct _gcsHAL_MAP_MEMORY
{
/* Physical memory address to map. */
IN gctPHYS_ADDR physical;
/* Number of bytes in physical memory to map. */
IN gctSIZE_T bytes;
/* Address of mapped memory. */
OUT gctPOINTER logical;
}
MapMemory;
/* gcvHAL_UNMAP_MEMORY */
struct _gcsHAL_UNMAP_MEMORY
{
/* Physical memory address to unmap. */
IN gctPHYS_ADDR physical;
/* Number of bytes in physical memory to unmap. */
IN gctSIZE_T bytes;
/* Address of mapped memory to unmap. */
IN gctPOINTER logical;
}
UnmapMemory;
/* gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY */
struct _gcsHAL_ALLOCATE_LINEAR_VIDEO_MEMORY
{
/* Number of bytes to allocate. */
IN OUT gctUINT bytes;
/* Buffer alignment. */
IN gctUINT alignment;
/* Type of allocation. */
IN gceSURF_TYPE type;
/* Memory pool to allocate from. */
IN OUT gcePOOL pool;
/* Allocated video memory. */
OUT gcuVIDMEM_NODE_PTR node;
}
AllocateLinearVideoMemory;
/* gcvHAL_ALLOCATE_VIDEO_MEMORY */
struct _gcsHAL_ALLOCATE_VIDEO_MEMORY
{
/* Width of rectangle to allocate. */
IN OUT gctUINT width;
/* Height of rectangle to allocate. */
IN OUT gctUINT height;
/* Depth of rectangle to allocate. */
IN gctUINT depth;
/* Format rectangle to allocate in gceSURF_FORMAT. */
IN gceSURF_FORMAT format;
/* Type of allocation. */
IN gceSURF_TYPE type;
/* Memory pool to allocate from. */
IN OUT gcePOOL pool;
/* Allocated video memory. */
OUT gcuVIDMEM_NODE_PTR node;
}
AllocateVideoMemory;
/* gcvHAL_FREE_VIDEO_MEMORY */
struct _gcsHAL_FREE_VIDEO_MEMORY
{
/* Allocated video memory. */
IN gcuVIDMEM_NODE_PTR node;
#ifdef __QNXNTO__
/* TODO: This is part of the unlock - why is it here? */
/* Mapped logical address to unmap in user space. */
OUT gctPOINTER memory;
/* Number of bytes to allocated. */
OUT gctSIZE_T bytes;
#endif
}
FreeVideoMemory;
/* gcvHAL_LOCK_VIDEO_MEMORY */
struct _gcsHAL_LOCK_VIDEO_MEMORY
{
/* Allocated video memory. */
IN gcuVIDMEM_NODE_PTR node;
/* Hardware specific address. */
OUT gctUINT32 address;
/* Mapped logical address. */
OUT gctPOINTER memory;
}
LockVideoMemory;
/* gcvHAL_UNLOCK_VIDEO_MEMORY */
struct _gcsHAL_UNLOCK_VIDEO_MEMORY
{
/* Allocated video memory. */
IN gcuVIDMEM_NODE_PTR node;
/* Type of surface. */
IN gceSURF_TYPE type;
/* Flag to unlock surface asynchroneously. */
IN OUT gctBOOL asynchroneous;
}
UnlockVideoMemory;
/* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
struct _gcsHAL_ALLOCATE_NON_PAGED_MEMORY
{
/* Number of bytes to allocate. */
IN OUT gctSIZE_T bytes;
/* Physical address of allocation. */
OUT gctPHYS_ADDR physical;
/* Logical address of allocation. */
OUT gctPOINTER logical;
}
AllocateNonPagedMemory;
/* gcvHAL_FREE_NON_PAGED_MEMORY */
struct _gcsHAL_FREE_NON_PAGED_MEMORY
{
/* Number of bytes allocated. */
IN gctSIZE_T bytes;
/* Physical address of allocation. */
IN gctPHYS_ADDR physical;
/* Logical address of allocation. */
IN gctPOINTER logical;
}
FreeNonPagedMemory;
/* gcvHAL_EVENT_COMMIT. */
struct _gcsHAL_EVENT_COMMIT
{
/* Event queue. */
IN struct _gcsQUEUE * queue;
}
Event;
/* gcvHAL_COMMIT */
struct _gcsHAL_COMMIT
{
/* Command buffer. */
IN gcoCMDBUF commandBuffer;
/* Context buffer. */
IN gcoCONTEXT contextBuffer;
/* Process handle. */
IN gctHANDLE process;
}
Commit;
/* gcvHAL_MAP_USER_MEMORY */
struct _gcsHAL_MAP_USER_MEMORY
{
/* Base address of user memory to map. */
IN gctPOINTER memory;
/* Size of user memory in bytes to map. */
IN gctSIZE_T size;
/* Info record required by gcvHAL_UNMAP_USER_MEMORY. */
OUT gctPOINTER info;
/* Physical address of mapped memory. */
OUT gctUINT32 address;
}
MapUserMemory;
/* gcvHAL_UNMAP_USER_MEMORY */
struct _gcsHAL_UNMAP_USER_MEMORY
{
/* Base address of user memory to unmap. */
IN gctPOINTER memory;
/* Size of user memory in bytes to unmap. */
IN gctSIZE_T size;
/* Info record returned by gcvHAL_MAP_USER_MEMORY. */
IN gctPOINTER info;
/* Physical address of mapped memory as returned by
gcvHAL_MAP_USER_MEMORY. */
IN gctUINT32 address;
}
UnmapUserMemory;
#if !USE_NEW_LINUX_SIGNAL
/* gcsHAL_USER_SIGNAL */
struct _gcsHAL_USER_SIGNAL
{
/* Command. */
gceUSER_SIGNAL_COMMAND_CODES command;
/* Signal ID. */
IN OUT gctINT id;
/* Reset mode. */
IN gctBOOL manualReset;
/* Wait timedout. */
IN gctUINT32 wait;
/* State. */
IN gctBOOL state;
}
UserSignal;
#endif
/* gcvHAL_SIGNAL. */
struct _gcsHAL_SIGNAL
{
/* Signal handle to signal. */
IN gctSIGNAL signal;
/* Reserved. */
IN gctSIGNAL auxSignal;
/* Process owning the signal. */
IN gctHANDLE process;
#if defined(__QNXNTO__)
/* Client pulse side-channel connection ID. Set by client in gcoOS_CreateSignal. */
IN gctINT32 coid;
/* Set by server. */
IN gctINT32 rcvid;
#endif
/* Event generated from where of pipeline */
IN gceKERNEL_WHERE fromWhere;
}
Signal;
/* gcvHAL_WRITE_DATA. */
struct _gcsHAL_WRITE_DATA
{
/* Address to write data to. */
IN gctUINT32 address;
/* Data to write. */
IN gctUINT32 data;
}
WriteData;
/* gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY */
struct _gcsHAL_ALLOCATE_CONTIGUOUS_MEMORY
{
/* Number of bytes to allocate. */
IN OUT gctSIZE_T bytes;
/* Physical address of allocation. */
OUT gctPHYS_ADDR physical;
/* Logical address of allocation. */
OUT gctPOINTER logical;
}
AllocateContiguousMemory;
/* gcvHAL_FREE_CONTIGUOUS_MEMORY */
struct _gcsHAL_FREE_CONTIGUOUS_MEMORY
{
/* Number of bytes allocated. */
IN gctSIZE_T bytes;
/* Physical address of allocation. */
IN gctPHYS_ADDR physical;
/* Logical address of allocation. */
IN gctPOINTER logical;
}
FreeContiguousMemory;
/* gcvHAL_READ_REGISTER */
struct _gcsHAL_READ_REGISTER
{
/* Logical address of memory to write data to. */
IN gctUINT32 address;
/* Data read. */
OUT gctUINT32 data;
}
ReadRegisterData;
/* gcvHAL_WRITE_REGISTER */
struct _gcsHAL_WRITE_REGISTER
{
/* Logical address of memory to write data to. */
IN gctUINT32 address;
/* Data read. */
IN gctUINT32 data;
}
WriteRegisterData;
/* gcvHAL_GET_PROFILE_SETTING */
struct _gcsHAL_GET_PROFILE_SETTING
{
/* Enable profiling */
OUT gctBOOL enable;
/* The profile file name */
OUT gctCHAR fileName[gcdMAX_PROFILE_FILE_NAME];
}
GetProfileSetting;
/* gcvHAL_SET_PROFILE_SETTING */
struct _gcsHAL_SET_PROFILE_SETTING
{
/* Enable profiling */
IN gctBOOL enable;
/* The profile file name */
IN gctCHAR fileName[gcdMAX_PROFILE_FILE_NAME];
}
SetProfileSetting;
/* gcvHAL_READ_ALL_PROFILE_REGISTERS */
struct _gcsHAL_READ_ALL_PROFILE_REGISTERS
{
/* Data read. */
OUT gcsPROFILER_COUNTERS counters;
}
RegisterProfileData;
/* gcvHAL_PROFILE_REGISTERS_2D */
struct _gcsHAL_PROFILE_REGISTERS_2D
{
/* Data read. */
OUT gcs2D_PROFILE_PTR hwProfile2D;
}
RegisterProfileData2D;
/* Power management. */
/* gcvHAL_SET_POWER_MANAGEMENT_STATE */
struct _gcsHAL_SET_POWER_MANAGEMENT
{
/* Data read. */
IN gceCHIPPOWERSTATE state;
}
SetPowerManagement;
/* gcvHAL_QUERY_POWER_MANAGEMENT_STATE */
struct _gcsHAL_QUERY_POWER_MANAGEMENT
{
/* Data read. */
OUT gceCHIPPOWERSTATE state;
/* Idle query. */
OUT gctBOOL isIdle;
}
QueryPowerManagement;
/* gcvHAL_QUERY_KERNEL_SETTINGS */
struct _gcsHAL_QUERY_KERNEL_SETTINGS
{
/* Settings.*/
OUT gcsKERNEL_SETTINGS settings;
}
QueryKernelSettings;
/* gcvHAL_MAP_PHYSICAL */
struct _gcsHAL_MAP_PHYSICAL
{
/* gcvTRUE to map, gcvFALSE to unmap. */
IN gctBOOL map;
/* Physical address. */
IN OUT gctPHYS_ADDR physical;
}
MapPhysical;
/* gcvHAL_DEBUG */
struct _gcsHAL_DEBUG
{
/* If gcvTRUE, set the debug information. */
IN gctBOOL set;
IN gctUINT32 level;
IN gctUINT32 zones;
IN gctBOOL enable;
/* Message to print if not empty. */
IN gctCHAR message[80];
}
Debug;
struct _gcsHAL_CACHE
{
IN gctBOOL invalidate;
IN gctHANDLE process;
IN gctPOINTER logical;
IN gctSIZE_T bytes;
}
Cache;
}
u;
}
gcsHAL_INTERFACE;
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_driver_h_ */

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_dump_h_
#define __gc_hal_dump_h_
#ifdef __cplusplus
extern "C" {
#endif
/*
** FILE LAYOUT:
**
** gcsDUMP_FILE structure
**
** gcsDUMP_DATA frame
** gcsDUMP_DATA or gcDUMP_DATA_SIZE records rendingring the frame
** gctUINT8 data[length]
*/
#define gcvDUMP_FILE_SIGNATURE gcmCC('g','c','D','B')
typedef struct _gcsDUMP_FILE
{
gctUINT32 signature; /* File signature */
gctSIZE_T length; /* Length of file */
gctUINT32 frames; /* Number of frames in file */
}
gcsDUMP_FILE;
typedef enum _gceDUMP_TAG
{
gcvTAG_SURFACE = gcmCC('s','u','r','f'),
gcvTAG_FRAME = gcmCC('f','r','m',' '),
gcvTAG_COMMAND = gcmCC('c','m','d',' '),
gcvTAG_INDEX = gcmCC('i','n','d','x'),
gcvTAG_STREAM = gcmCC('s','t','r','m'),
gcvTAG_TEXTURE = gcmCC('t','e','x','t'),
gcvTAG_RENDER_TARGET = gcmCC('r','n','d','r'),
gcvTAG_DEPTH = gcmCC('z','b','u','f'),
gcvTAG_RESOLVE = gcmCC('r','s','l','v'),
gcvTAG_DELETE = gcmCC('d','e','l',' '),
}
gceDUMP_TAG;
typedef struct _gcsDUMP_SURFACE
{
gceDUMP_TAG type; /* Type of record. */
gctUINT32 address; /* Address of the surface. */
gctINT16 width; /* Width of surface. */
gctINT16 height; /* Height of surface. */
gceSURF_FORMAT format; /* Surface pixel format. */
gctSIZE_T length; /* Number of bytes inside the surface. */
}
gcsDUMP_SURFACE;
typedef struct _gcsDUMP_DATA
{
gceDUMP_TAG type; /* Type of record. */
gctSIZE_T length; /* Number of bytes of data. */
gctUINT32 address; /* Address for the data. */
}
gcsDUMP_DATA;
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_dump_h_ */

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_enum_h_
#define __gc_hal_enum_h_
#ifdef __cplusplus
extern "C" {
#endif
/* Chip models. */
typedef enum _gceCHIPMODEL
{
gcv300 = 0x0300,
gcv400 = 0x0400,
gcv410 = 0x0410,
gcv450 = 0x0450,
gcv500 = 0x0500,
gcv530 = 0x0530,
gcv600 = 0x0600,
gcv700 = 0x0700,
gcv800 = 0x0800,
gcv860 = 0x0860,
gcv1000 = 0x1000,
}
gceCHIPMODEL;
/* Chip features. */
typedef enum _gceFEATURE
{
gcvFEATURE_PIPE_2D,
gcvFEATURE_PIPE_3D,
gcvFEATURE_PIPE_VG,
gcvFEATURE_DC,
gcvFEATURE_HIGH_DYNAMIC_RANGE,
gcvFEATURE_MODULE_CG,
gcvFEATURE_MIN_AREA,
gcvFEATURE_BUFFER_INTERLEAVING,
gcvFEATURE_BYTE_WRITE_2D,
gcvFEATURE_ENDIANNESS_CONFIG,
gcvFEATURE_DUAL_RETURN_BUS,
gcvFEATURE_DEBUG_MODE,
gcvFEATURE_YUY2_RENDER_TARGET,
gcvFEATURE_FRAGMENT_PROCESSOR,
gcvFEATURE_2DPE20,
gcvFEATURE_FAST_CLEAR,
gcvFEATURE_YUV420_TILER,
gcvFEATURE_YUY2_AVERAGING,
gcvFEATURE_FLIP_Y,
gcvFEATURE_EARLY_Z,
gcvFEATURE_Z_COMPRESSION,
gcvFEATURE_MSAA,
gcvFEATURE_SPECIAL_ANTI_ALIASING,
gcvFEATURE_SPECIAL_MSAA_LOD,
gcvFEATURE_422_TEXTURE_COMPRESSION,
gcvFEATURE_DXT_TEXTURE_COMPRESSION,
gcvFEATURE_ETC1_TEXTURE_COMPRESSION,
gcvFEATURE_CORRECT_TEXTURE_CONVERTER,
gcvFEATURE_TEXTURE_8K,
gcvFEATURE_SCALER,
gcvFEATURE_YUV420_SCALER,
gcvFEATURE_SHADER_HAS_W,
gcvFEATURE_SHADER_HAS_SIGN,
gcvFEATURE_SHADER_HAS_FLOOR,
gcvFEATURE_SHADER_HAS_CEIL,
gcvFEATURE_SHADER_HAS_SQRT,
gcvFEATURE_SHADER_HAS_TRIG,
gcvFEATURE_VAA,
gcvFEATURE_HZ,
gcvFEATURE_CORRECT_STENCIL,
gcvFEATURE_VG20,
gcvFEATURE_VG_FILTER,
gcvFEATURE_VG21,
gcvFEATURE_VG_DOUBLE_BUFFER,
gcvFEATURE_MC20,
gcvFEATURE_SUPER_TILED,
}
gceFEATURE;
/* Chip Power Status. */
typedef enum _gceCHIPPOWERSTATE
{
gcvPOWER_ON,
gcvPOWER_OFF,
gcvPOWER_IDLE,
gcvPOWER_SUSPEND,
gcvPOWER_SUSPEND_ATPOWERON,
gcvPOWER_OFF_ATPOWERON,
gcvPOWER_IDLE_BROADCAST,
gcvPOWER_SUSPEND_BROADCAST,
gcvPOWER_OFF_BROADCAST,
gcvPOWER_OFF_RECOVERY,
}
gceCHIPPOWERSTATE;
/* Surface types. */
typedef enum _gceSURF_TYPE
{
gcvSURF_TYPE_UNKNOWN,
gcvSURF_INDEX,
gcvSURF_VERTEX,
gcvSURF_TEXTURE,
gcvSURF_RENDER_TARGET,
gcvSURF_DEPTH,
gcvSURF_BITMAP,
gcvSURF_TILE_STATUS,
gcvSURF_MASK,
gcvSURF_SCISSOR,
gcvSURF_HIERARCHICAL_DEPTH,
gcvSURF_NUM_TYPES, /* Make sure this is the last one! */
/* Combinations. */
gcvSURF_NO_TILE_STATUS = 0x100,
gcvSURF_RENDER_TARGET_NO_TILE_STATUS = gcvSURF_RENDER_TARGET
| gcvSURF_NO_TILE_STATUS,
gcvSURF_DEPTH_NO_TILE_STATUS = gcvSURF_DEPTH
| gcvSURF_NO_TILE_STATUS,
}
gceSURF_TYPE;
typedef enum _gceSURF_COLOR_TYPE
{
gcvSURF_COLOR_UNKNOWN,
gcvSURF_COLOR_LINEAR = 0x01,
gcvSURF_COLOR_ALPHA_PRE = 0x02,
}
gceSURF_COLOR_TYPE;
/* Rotation. */
typedef enum _gceSURF_ROTATION
{
gcvSURF_0_DEGREE,
gcvSURF_90_DEGREE,
gcvSURF_180_DEGREE,
gcvSURF_270_DEGREE
}
gceSURF_ROTATION;
/* Surface formats. */
typedef enum _gceSURF_FORMAT
{
/* Unknown format. */
gcvSURF_UNKNOWN,
/* Palettized formats. */
gcvSURF_INDEX1 = 100,
gcvSURF_INDEX4,
gcvSURF_INDEX8,
/* RGB formats. */
gcvSURF_A2R2G2B2 = 200,
gcvSURF_R3G3B2,
gcvSURF_A8R3G3B2,
gcvSURF_X4R4G4B4,
gcvSURF_A4R4G4B4,
gcvSURF_R4G4B4A4,
gcvSURF_X1R5G5B5,
gcvSURF_A1R5G5B5,
gcvSURF_R5G5B5A1,
gcvSURF_R5G6B5,
gcvSURF_R8G8B8,
gcvSURF_X8R8G8B8,
gcvSURF_A8R8G8B8,
gcvSURF_R8G8B8A8,
gcvSURF_G8R8G8B8,
gcvSURF_R8G8B8G8,
gcvSURF_X2R10G10B10,
gcvSURF_A2R10G10B10,
gcvSURF_X12R12G12B12,
gcvSURF_A12R12G12B12,
gcvSURF_X16R16G16B16,
gcvSURF_A16R16G16B16,
gcvSURF_R8G8B8X8,
gcvSURF_R5G5B5X1,
gcvSURF_R4G4B4X4,
/* BGR formats. */
gcvSURF_A4B4G4R4 = 300,
gcvSURF_A1B5G5R5,
gcvSURF_B5G6R5,
gcvSURF_B8G8R8,
gcvSURF_X8B8G8R8,
gcvSURF_A8B8G8R8,
gcvSURF_A2B10G10R10,
gcvSURF_A16B16G16R16,
gcvSURF_G16R16,
gcvSURF_B4G4R4A4,
gcvSURF_B5G5R5A1,
gcvSURF_B8G8R8X8,
gcvSURF_B8G8R8A8,
gcvSURF_X4B4G4R4,
gcvSURF_X1B5G5R5,
gcvSURF_B4G4R4X4,
gcvSURF_B5G5R5X1,
/* Compressed formats. */
gcvSURF_DXT1 = 400,
gcvSURF_DXT2,
gcvSURF_DXT3,
gcvSURF_DXT4,
gcvSURF_DXT5,
gcvSURF_CXV8U8,
gcvSURF_ETC1,
/* YUV formats. */
gcvSURF_YUY2 = 500,
gcvSURF_UYVY,
gcvSURF_YV12,
gcvSURF_I420,
gcvSURF_NV12,
gcvSURF_NV21,
gcvSURF_NV16,
gcvSURF_NV61,
gcvSURF_YVYU,
gcvSURF_VYUY,
/* Depth formats. */
gcvSURF_D16 = 600,
gcvSURF_D24S8,
gcvSURF_D32,
gcvSURF_D24X8,
/* Alpha formats. */
gcvSURF_A4 = 700,
gcvSURF_A8,
gcvSURF_A12,
gcvSURF_A16,
gcvSURF_A32,
gcvSURF_A1,
/* Luminance formats. */
gcvSURF_L4 = 800,
gcvSURF_L8,
gcvSURF_L12,
gcvSURF_L16,
gcvSURF_L32,
gcvSURF_L1,
/* Alpha/Luminance formats. */
gcvSURF_A4L4 = 900,
gcvSURF_A2L6,
gcvSURF_A8L8,
gcvSURF_A4L12,
gcvSURF_A12L12,
gcvSURF_A16L16,
/* Bump formats. */
gcvSURF_L6V5U5 = 1000,
gcvSURF_V8U8,
gcvSURF_X8L8V8U8,
gcvSURF_Q8W8V8U8,
gcvSURF_A2W10V10U10,
gcvSURF_V16U16,
gcvSURF_Q16W16V16U16,
/* Floating point formats. */
gcvSURF_R16F = 1100,
gcvSURF_G16R16F,
gcvSURF_A16B16G16R16F,
gcvSURF_R32F,
gcvSURF_G32R32F,
gcvSURF_A32B32G32R32F,
#if 0
/* FIXME: remove HDR support for now. */
/* HDR formats. */
gcvSURF_HDR7E3 = 1200,
gcvSURF_HDR6E4,
gcvSURF_HDR5E5,
gcvSURF_HDR6E5,
#endif
}
gceSURF_FORMAT;
/* Pixel swizzle modes. */
typedef enum _gceSURF_SWIZZLE
{
gcvSURF_NOSWIZZLE,
gcvSURF_ARGB,
gcvSURF_ABGR,
gcvSURF_RGBA,
gcvSURF_BGRA
}
gceSURF_SWIZZLE;
/* Transparency modes. */
typedef enum _gceSURF_TRANSPARENCY
{
/* Valid only for PE 1.0 */
gcvSURF_OPAQUE,
gcvSURF_SOURCE_MATCH,
gcvSURF_SOURCE_MASK,
gcvSURF_PATTERN_MASK,
}
gceSURF_TRANSPARENCY;
/* Transparency modes. */
typedef enum _gce2D_TRANSPARENCY
{
/* Valid only for PE 2.0 */
gcv2D_OPAQUE,
gcv2D_KEYED,
gcv2D_MASKED
}
gce2D_TRANSPARENCY;
/* Mono packing modes. */
typedef enum _gceSURF_MONOPACK
{
gcvSURF_PACKED8,
gcvSURF_PACKED16,
gcvSURF_PACKED32,
gcvSURF_UNPACKED,
}
gceSURF_MONOPACK;
/* Blending modes. */
typedef enum _gceSURF_BLEND_MODE
{
/* Porter-Duff blending modes. */
/* Fsrc Fdst */
gcvBLEND_CLEAR, /* 0 0 */
gcvBLEND_SRC, /* 1 0 */
gcvBLEND_DST, /* 0 1 */
gcvBLEND_SRC_OVER_DST, /* 1 1 - Asrc */
gcvBLEND_DST_OVER_SRC, /* 1 - Adst 1 */
gcvBLEND_SRC_IN_DST, /* Adst 0 */
gcvBLEND_DST_IN_SRC, /* 0 Asrc */
gcvBLEND_SRC_OUT_DST, /* 1 - Adst 0 */
gcvBLEND_DST_OUT_SRC, /* 0 1 - Asrc */
gcvBLEND_SRC_ATOP_DST, /* Adst 1 - Asrc */
gcvBLEND_DST_ATOP_SRC, /* 1 - Adst Asrc */
gcvBLEND_SRC_XOR_DST, /* 1 - Adst 1 - Asrc */
/* Special blending modes. */
gcvBLEND_SET, /* DST = 1 */
gcvBLEND_SUB /* DST = DST * (1 - SRC) */
}
gceSURF_BLEND_MODE;
/* Per-pixel alpha modes. */
typedef enum _gceSURF_PIXEL_ALPHA_MODE
{
gcvSURF_PIXEL_ALPHA_STRAIGHT,
gcvSURF_PIXEL_ALPHA_INVERSED
}
gceSURF_PIXEL_ALPHA_MODE;
/* Global alpha modes. */
typedef enum _gceSURF_GLOBAL_ALPHA_MODE
{
gcvSURF_GLOBAL_ALPHA_OFF,
gcvSURF_GLOBAL_ALPHA_ON,
gcvSURF_GLOBAL_ALPHA_SCALE
}
gceSURF_GLOBAL_ALPHA_MODE;
/* Color component modes for alpha blending. */
typedef enum _gceSURF_PIXEL_COLOR_MODE
{
gcvSURF_COLOR_STRAIGHT,
gcvSURF_COLOR_MULTIPLY
}
gceSURF_PIXEL_COLOR_MODE;
/* Color component modes for alpha blending. */
typedef enum _gce2D_PIXEL_COLOR_MULTIPLY_MODE
{
gcv2D_COLOR_MULTIPLY_DISABLE,
gcv2D_COLOR_MULTIPLY_ENABLE
}
gce2D_PIXEL_COLOR_MULTIPLY_MODE;
/* Color component modes for alpha blending. */
typedef enum _gce2D_GLOBAL_COLOR_MULTIPLY_MODE
{
gcv2D_GLOBAL_COLOR_MULTIPLY_DISABLE,
gcv2D_GLOBAL_COLOR_MULTIPLY_ALPHA,
gcv2D_GLOBAL_COLOR_MULTIPLY_COLOR
}
gce2D_GLOBAL_COLOR_MULTIPLY_MODE;
/* Alpha blending factor modes. */
typedef enum _gceSURF_BLEND_FACTOR_MODE
{
gcvSURF_BLEND_ZERO,
gcvSURF_BLEND_ONE,
gcvSURF_BLEND_STRAIGHT,
gcvSURF_BLEND_INVERSED,
gcvSURF_BLEND_COLOR,
gcvSURF_BLEND_COLOR_INVERSED,
gcvSURF_BLEND_SRC_ALPHA_SATURATED
}
gceSURF_BLEND_FACTOR_MODE;
/* Alpha blending porter duff rules. */
typedef enum _gce2D_PORTER_DUFF_RULE
{
gcvPD_CLEAR,
gcvPD_SRC,
gcvPD_SRC_OVER,
gcvPD_DST_OVER,
gcvPD_SRC_IN,
gcvPD_DST_IN,
gcvPD_SRC_OUT,
gcvPD_DST_OUT,
gcvPD_SRC_ATOP,
gcvPD_DST_ATOP,
gcvPD_ADD,
gcvPD_XOR,
gcvPD_DST
}
gce2D_PORTER_DUFF_RULE;
/* Alpha blending factor modes. */
typedef enum _gce2D_YUV_COLOR_MODE
{
gcv2D_YUV_601,
gcv2D_YUV_709
}
gce2D_YUV_COLOR_MODE;
/* 2D Rotation and flipping. */
typedef enum _gce2D_ORIENTATION
{
gcv2D_0_DEGREE,
gcv2D_90_DEGREE,
gcv2D_180_DEGREE,
gcv2D_270_DEGREE,
gcv2D_X_FLIP,
gcv2D_Y_FLIP
}
gce2D_ORIENTATION;
typedef enum _gce2D_COMMAND
{
gcv2D_CLEAR,
gcv2D_LINE,
gcv2D_BLT,
gcv2D_STRETCH,
gcv2D_HOR_FILTER,
gcv2D_VER_FILTER,
}
gce2D_COMMAND;
/* Texture functions. */
typedef enum _gceTEXTURE_FUNCTION
{
gcvTEXTURE_DUMMY = 0,
gcvTEXTURE_REPLACE = 0,
gcvTEXTURE_MODULATE,
gcvTEXTURE_ADD,
gcvTEXTURE_ADD_SIGNED,
gcvTEXTURE_INTERPOLATE,
gcvTEXTURE_SUBTRACT,
gcvTEXTURE_DOT3
}
gceTEXTURE_FUNCTION;
/* Texture sources. */
typedef enum _gceTEXTURE_SOURCE
{
gcvCOLOR_FROM_TEXTURE,
gcvCOLOR_FROM_CONSTANT_COLOR,
gcvCOLOR_FROM_PRIMARY_COLOR,
gcvCOLOR_FROM_PREVIOUS_COLOR
}
gceTEXTURE_SOURCE;
/* Texture source channels. */
typedef enum _gceTEXTURE_CHANNEL
{
gcvFROM_COLOR,
gcvFROM_ONE_MINUS_COLOR,
gcvFROM_ALPHA,
gcvFROM_ONE_MINUS_ALPHA
}
gceTEXTURE_CHANNEL;
/* Filter types. */
typedef enum _gceFILTER_TYPE
{
gcvFILTER_SYNC,
gcvFILTER_BLUR,
gcvFILTER_USER
}
gceFILTER_TYPE;
/* Filter pass types. */
typedef enum _gceFILTER_PASS_TYPE
{
gcvFILTER_HOR_PASS,
gcvFILTER_VER_PASS
}
gceFILTER_PASS_TYPE;
/* Endian hints. */
typedef enum _gceENDIAN_HINT
{
gcvENDIAN_NO_SWAP = 0,
gcvENDIAN_SWAP_WORD,
gcvENDIAN_SWAP_DWORD
}
gceENDIAN_HINT;
/* Endian hints. */
typedef enum _gceTILING
{
gcvLINEAR,
gcvTILED,
gcvSUPERTILED
}
gceTILING;
/******************************************************************************\
****************************** Object Declarations *****************************
\******************************************************************************/
typedef struct _gcoCONTEXT * gcoCONTEXT;
typedef struct _gcoCMDBUF * gcoCMDBUF;
typedef struct _gcoQUEUE * gcoQUEUE;
typedef struct _gcsHAL_INTERFACE * gcsHAL_INTERFACE_PTR;
typedef struct gcs2D_PROFILE * gcs2D_PROFILE_PTR;
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_enum_h_ */

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drivers/staging/rk29/vivante/hal/inc/gc_hal_mem.h Normal file
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@ -0,0 +1,471 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
/*
** Include file for the local memory management.
*/
#ifndef __gc_hal_mem_h_
#define __gc_hal_mem_h_
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
** Usage:
The macros to declare MemPool type and functions are
gcmMEM_DeclareFSMemPool (Type, TypeName, Prefix)
gcmMEM_DeclareVSMemPool (Type, TypeName, Prefix)
gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix)
The data structures for MemPool are
typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
The MemPool constructor and destructor functions are
gcfMEM_InitFSMemPool(gcsMEM_FS_MEM_POOL *, gcoOS, gctUINT, gctUINT);
gcfMEM_FreeFSMemPool(gcsMEM_FS_MEM_POOL *);
gcfMEM_InitVSMemPool(gcsMEM_VS_MEM_POOL *, gcoOS, gctUINT, gctBOOL);
gcfMEM_FreeVSMemPool(gcsMEM_VS_MEM_POOL *);
gcfMEM_InitAFSMemPool(gcsMEM_AFS_MEM_POOL *, gcoOS, gctUINT);
gcfMEM_FreeAFSMemPool(gcsMEM_AFS_MEM_POOL *);
FS: for Fixed-Size data structures
VS: for Variable-size data structures
AFS: for Array of Fixed-Size data structures
// Example 1: For a fixed-size data structure, struct gcsNode.
// It is used locally in a file, so the functions are static without prefix.
// At top level, declear allocate and free functions.
// The first argument is the data type.
// The second armument is the short name used in the fuctions.
gcmMEM_DeclareFSMemPool(struct gcsNode, Node, );
// The previous macro creates two inline functions,
// _AllocateNode and _FreeNode.
// In function or struct
gcsMEM_FS_MEM_POOL nodeMemPool;
// In function,
struct gcsNode * node;
gceSTATUS status;
// Before using the memory pool, initialize it.
// The second argument is the gcoOS object.
// The third argument is the number of data structures to allocate for each chunk.
status = gcfMEM_InitFSMemPool(&nodeMemPool, os, 100, sizeof(struct gcsNode));
...
// Allocate a node.
status = _AllocateNode(nodeMemPool, &node);
...
// Free a node.
_FreeNode(nodeMemPool, node);
// After using the memory pool, free it.
gcfMEM_FreeFSMemPool(&nodeMemPool);
// Example 2: For array of fixed-size data structures, struct gcsNode.
// It is used in several files, so the functions are extern with prefix.
// At top level, declear allocate and free functions.
// The first argument is the data type, and the second one is the short name
// used in the fuctions.
gcmMEM_DeclareAFSMemPool(struct gcsNode, NodeArray, gcfOpt);
// The previous macro creates two inline functions,
// gcfOpt_AllocateNodeArray and gcfOpt_FreeNodeArray.
// In function or struct
gcsMEM_AFS_MEM_POOL nodeArrayMemPool;
// In function,
struct gcsNode * nodeArray;
gceSTATUS status;
// Before using the array memory pool, initialize it.
// The second argument is the gcoOS object, the third is the number of data
// structures to allocate for each chunk.
status = gcfMEM_InitAFSMemPool(&nodeArrayMemPool, os, sizeof(struct gcsNode));
...
// Allocate a node array of size 100.
status = gcfOpt_AllocateNodeArray(nodeArrayMemPool, &nodeArray, 100);
...
// Free a node array.
gcfOpt_FreeNodeArray(&nodeArrayMemPool, nodeArray);
// After using the array memory pool, free it.
gcfMEM_FreeAFSMemPool(&nodeArrayMemPool);
*******************************************************************************/
/*******************************************************************************
** To switch back to use gcoOS_Allocate and gcoOS_Free, add
** #define USE_LOCAL_MEMORY_POOL 0
** before including this file.
*******************************************************************************/
#ifndef USE_LOCAL_MEMORY_POOL
/*
USE_LOCAL_MEMORY_POOL
This define enables the local memory management to improve performance.
*/
#define USE_LOCAL_MEMORY_POOL 1
#endif
/*******************************************************************************
** Memory Pool Data Structures
*******************************************************************************/
#if USE_LOCAL_MEMORY_POOL
typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
#else
typedef gcoOS gcsMEM_FS_MEM_POOL;
typedef gcoOS gcsMEM_VS_MEM_POOL;
typedef gcoOS gcsMEM_AFS_MEM_POOL;
#endif
/*******************************************************************************
** Memory Pool Macros
*******************************************************************************/
#if USE_LOCAL_MEMORY_POOL
#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
gceSTATUS \
Prefix##_Allocate##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type ** Pointer \
) \
{ \
return(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
} \
\
gceSTATUS \
Prefix##_CAllocate##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type ** Pointer \
) \
{ \
gceSTATUS status; \
gcmERR_RETURN(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
gcmVERIFY_OK(gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type))); \
return gcvSTATUS_OK; \
} \
\
gceSTATUS \
Prefix##_Free##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type * Pointer \
) \
{ \
return(gcfMEM_FSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer)); \
} \
\
gceSTATUS \
Prefix##_Free##TypeName##List( \
gcsMEM_FS_MEM_POOL MemPool, \
Type * FirstPointer, \
Type * LastPointer \
) \
{ \
return(gcfMEM_FSMemPoolFreeAList(MemPool, (gctPOINTER) FirstPointer, (gctPOINTER) LastPointer)); \
}
#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
gceSTATUS \
Prefix##_Allocate##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Size \
) \
{ \
return(gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer)); \
} \
\
gceSTATUS \
Prefix##_CAllocate##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Size \
) \
{ \
gceSTATUS status; \
gcmERR_RETURN(gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer)); \
gcmVERIFY_OK(gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, size)); \
return gcvSTATUS_OK; \
} \
\
gceSTATUS \
Prefix##_Free##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type * Pointer \
) \
{ \
return(gcfMEM_VSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer)); \
}
#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
gceSTATUS \
Prefix##_Allocate##TypeName( \
gcsMEM_AFS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Count \
) \
{ \
return(gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer)); \
} \
\
gceSTATUS \
Prefix##_CAllocate##TypeName( \
gcsMEM_AFS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Count \
) \
{ \
gceSTATUS status; \
gcmERR_RETURN(gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer)); \
gcmVERIFY_OK(gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type))); \
return gcvSTATUS_OK; \
} \
\
gceSTATUS \
Prefix##_Free##TypeName( \
gcsMEM_AFS_MEM_POOL MemPool, \
Type * Pointer \
) \
{ \
return(gcfMEM_AFSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer)); \
}
#else
#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
gceSTATUS \
Prefix##_Allocate##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type ** Pointer \
) \
{ \
return(gcoOS_Allocate(MemPool, \
gcmSIZEOF(Type), \
(gctPOINTER *) Pointer)); \
} \
\
gceSTATUS \
Prefix##_CAllocate##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type ** Pointer \
) \
{ \
gceSTATUS status; \
gcmERR_RETURN(gcoOS_Allocate(MemPool, \
gcmSIZEOF(Type), \
(gctPOINTER *) Pointer)); \
gcmVERIFY_OK(gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type))); \
return gcvSTATUS_OK; \
} \
\
gceSTATUS \
Prefix##_Free##TypeName( \
gcsMEM_FS_MEM_POOL MemPool, \
Type * Pointer \
) \
{ \
return(gcoOS_Free(MemPool, Pointer)); \
}
#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
gceSTATUS \
Prefix##_Allocate##TypeName( \
gcsMEM_VS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Size \
) \
{ \
return(gcoOS_Allocate(MemPool, \
Size, \
(gctPOINTER *) Pointer)); \
} \
\
gceSTATUS \
Prefix##_CAllocate##TypeName( \
gcsMEM_VS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Size \
) \
{ \
gceSTATUS status; \
gcmERR_RETURN(gcoOS_Allocate(MemPool, \
Size, \
(gctPOINTER *) Pointer)); \
gcmVERIFY_OK(gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Size)); \
return gcvSTATUS_OK; \
} \
\
gceSTATUS \
Prefix##_Free##TypeName( \
gcsMEM_VS_MEM_POOL MemPool, \
Type * Pointer \
) \
{ \
return(gcoOS_Free(MemPool, Pointer)); \
}
#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
gceSTATUS \
Prefix##_Allocate##TypeName( \
gcsMEM_AFS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Count \
) \
{ \
return(gcoOS_Allocate(MemPool, \
Count * gcmSIZEOF(Type), \
(gctPOINTER *) Pointer)); \
} \
\
gceSTATUS \
Prefix##_CAllocate##TypeName( \
gcsMEM_AFS_MEM_POOL MemPool, \
Type ** Pointer, \
gctUINT Count \
) \
{ \
gceSTATUS status; \
gcmERR_RETURN(gcoOS_Allocate(MemPool, \
Count * gcmSIZEOF(Type), \
(gctPOINTER *) Pointer)); \
gcmVERIFY_OK(gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type))); \
return gcvSTATUS_OK; \
} \
\
gceSTATUS \
Prefix##_Free##TypeName( \
gcsMEM_AFS_MEM_POOL MemPool, \
Type * Pointer \
) \
{ \
return(gcoOS_Free(MemPool, Pointer)); \
}
#endif
/*******************************************************************************
** Memory Pool Data Functions
*******************************************************************************/
gceSTATUS
gcfMEM_InitFSMemPool(
IN gcsMEM_FS_MEM_POOL * MemPool,
IN gcoOS OS,
IN gctUINT NodeCount,
IN gctUINT NodeSize
);
gceSTATUS
gcfMEM_FreeFSMemPool(
IN gcsMEM_FS_MEM_POOL * MemPool
);
gceSTATUS
gcfMEM_FSMemPoolGetANode(
IN gcsMEM_FS_MEM_POOL MemPool,
OUT gctPOINTER * Node
);
gceSTATUS
gcfMEM_FSMemPoolFreeANode(
IN gcsMEM_FS_MEM_POOL MemPool,
IN gctPOINTER Node
);
gceSTATUS
gcfMEM_FSMemPoolFreeAList(
IN gcsMEM_FS_MEM_POOL MemPool,
IN gctPOINTER FirstNode,
IN gctPOINTER LastNode
);
gceSTATUS
gcfMEM_InitVSMemPool(
IN gcsMEM_VS_MEM_POOL * MemPool,
IN gcoOS OS,
IN gctUINT BlockSize,
IN gctBOOL RecycleFreeNode
);
gceSTATUS
gcfMEM_FreeVSMemPool(
IN gcsMEM_VS_MEM_POOL * MemPool
);
gceSTATUS
gcfMEM_VSMemPoolGetANode(
IN gcsMEM_VS_MEM_POOL MemPool,
IN gctUINT Size,
IN gctUINT Alignment,
OUT gctPOINTER * Node
);
gceSTATUS
gcfMEM_VSMemPoolFreeANode(
IN gcsMEM_VS_MEM_POOL MemPool,
IN gctPOINTER Node
);
gceSTATUS
gcfMEM_InitAFSMemPool(
IN gcsMEM_AFS_MEM_POOL *MemPool,
IN gcoOS OS,
IN gctUINT NodeCount,
IN gctUINT NodeSize
);
gceSTATUS
gcfMEM_FreeAFSMemPool(
IN gcsMEM_AFS_MEM_POOL *MemPool
);
gceSTATUS
gcfMEM_AFSMemPoolGetANode(
IN gcsMEM_AFS_MEM_POOL MemPool,
IN gctUINT Count,
OUT gctPOINTER * Node
);
gceSTATUS
gcfMEM_AFSMemPoolFreeANode(
IN gcsMEM_AFS_MEM_POOL MemPool,
IN gctPOINTER Node
);
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_mem_h_ */

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_options_h_
#define __gc_hal_options_h_
/*
USE_NEW_LINUX_SIGNAL
This define enables the Linux kernel signaling between kernel and user.
*/
#ifndef USE_NEW_LINUX_SIGNAL
# define USE_NEW_LINUX_SIGNAL 0
#endif
/*
NO_USER_DIRECT_ACCESS_FROM_KERNEL
This define enables the Linux kernel behavior accessing user memory.
*/
#ifndef NO_USER_DIRECT_ACCESS_FROM_KERNEL
# define NO_USER_DIRECT_ACCESS_FROM_KERNEL 0
#endif
/*
VIVANTE_PROFILER
This define enables the profiler.
*/
#ifndef VIVANTE_PROFILER
# define VIVANTE_PROFILER 0
#endif
/*
gcdUSE_VG
Enable VG HAL layer (only for GC350).
*/
#ifndef gcdUSE_VG
# define gcdUSE_VG 0
#endif
/*
USE_SW_FB
Set to 1 if the frame buffer memory cannot be accessed by the GPU.
*/
#ifndef USE_SW_FB
#define USE_SW_FB 0
#endif
/*
USE_SHADER_SYMBOL_TABLE
This define enables the symbol table in shader object.
*/
#define USE_SHADER_SYMBOL_TABLE 1
/*
USE_SUPER_SAMPLING
This define enables super-sampling support.
*/
#define USE_SUPER_SAMPLING 0
/*
PROFILE_HAL_COUNTERS
This define enables HAL counter profiling support.
HW and SHADER Counter profiling depends on this.
*/
#define PROFILE_HAL_COUNTERS 1
/*
PROFILE_HW_COUNTERS
This define enables HW counter profiling support.
*/
#define PROFILE_HW_COUNTERS 1
/*
PROFILE_SHADER_COUNTERS
This define enables SHADER counter profiling support.
*/
#define PROFILE_SHADER_COUNTERS 1
/*
COMMAND_PROCESSOR_VERSION
The version of the command buffer and task manager.
*/
#define COMMAND_PROCESSOR_VERSION 1
/*
gcdDUMP
When set to 1, a dump of all states and memory uploads, as well as other
hardware related execution will be printed to the debug console. This
data can be used for playing back applications.
*/
#define gcdDUMP 0
/*
gcdDUMP_API
When set to 1, a high level dump of the EGL and GL/VG APs's are
captured.
*/
#define gcdDUMP_API 0
/*
gcdDUMP_IN_KERNEL
When set to 1, all dumps will happen in the kernel. This is handy if
you want the kernel to dump its command buffers as well and the data
needs to be in sync.
*/
#define gcdDUMP_IN_KERNEL 0
/*
gcdDUMP_COMMAND
When set to non-zero, the command queue will dump all incoming command
and context buffers as well as all other modifications to the command
queue.
*/
#define gcdDUMP_COMMAND 0
/*
gcdNULL_DRIVER
*/
#define gcdNULL_DRIVER 0
/*
gcdENABLE_TIMEOUT_DETECTION
Enable timeout detection.
*/
#define gcdENABLE_TIMEOUT_DETECTION 0
/*
gcdCMD_BUFFERS
Number of command buffers to use per client. Each command buffer is 32kB in
size.
*/
#define gcdCMD_BUFFERS 2
/*
gcdPOWER_CONTROL_DELAY
The delay in milliseconds required to wait until the GPU has woke up from a
suspend or power-down state. This is system dependent because the bus clock
also needs to be stabalize.
*/
#define gcdPOWER_CONTROL_DELAY 1
/*
gcdMMU_SIZE
Size of the MMU page table in bytes. Each 4 bytes can hold 4kB worth of
virtual data.
*/
#define gcdMMU_SIZE (128 << 10)
/*
gcdSECURE_USER
Use logical addresses instead of physical addresses in user land. In this
case a hint table is created for both command buffers and context buffers,
and that hint table will be used to patch up those buffers in the kernel
when they are ready to submit.
*/
#define gcdSECURE_USER 0
/*
gcdSECURE_CACHE_SLOTS
Number of slots in the logical to DMA address cache table. Each time a
logical address needs to be translated into a DMA address for the GPU, this
cache will be walked. The replacement scheme is LRU.
*/
#define gcdSECURE_CACHE_SLOTS 64
/*
gcdREGISTER_ACCESS_FROM_USER
Set to 1 to allow IOCTL calls to get through from user land. This should
only be in debug or development drops.
*/
#ifndef gcdREGISTER_ACCESS_FROM_USER
# define gcdREGISTER_ACCESS_FROM_USER 1
#endif
/*
gcdHEAP_SIZE
Set the allocation size for the internal heaps. Each time a heap is full,
a new heap will be allocated with this minmimum amount of bytes. The bigger
this size, the fewer heaps there are to allocate, the better the
performance. However, heaps won't be freed until they are completely free,
so there might be some more memory waste if the size is too big.
*/
#define gcdHEAP_SIZE (64 << 10)
/*
gcdNO_POWER_MANAGEMENT
This define disables the power management code.
*/
#ifndef gcdNO_POWER_MANAGEMENT
# define gcdNO_POWER_MANAGEMENT 0
#endif
/*
gcdFPGA_BUILD
This define enables work arounds for FPGA images.
*/
#if !defined(gcdFPGA_BUILD)
# define gcdFPGA_BUILD 0
#endif
/*
gcdGPU_TIMEOUT
This define specified the number of milliseconds the system will wait before
it broadcasts the GPU is stuck. In other words, it will define the timeout
of any operation that needs to wait for the GPU.
If the value is 0, no timeout will be checked for.
*/
#if !defined(gcdGPU_TIMEOUT)
# define gcdGPU_TIMEOUT 0
#endif
#endif /* __gc_hal_options_h_ */

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_profiler_h_
#define __gc_hal_profiler_h_
#ifdef __cplusplus
extern "C" {
#endif
#define GLVERTEX_OBJECT 10
#define GLVERTEX_OBJECT_BYTES 11
#define GLINDEX_OBJECT 20
#define GLINDEX_OBJECT_BYTES 21
#define GLTEXTURE_OBJECT 30
#define GLTEXTURE_OBJECT_BYTES 31
#if VIVANTE_PROFILER
#define gcmPROFILE_GC(Hal, Enum, Value) gcoPROFILER_Count(Hal, Enum, Value)
#else
#define gcmPROFILE_GC(Hal, Enum, Value) do { } while (gcvFALSE)
#endif
/* HW profile information. */
typedef struct _gcsPROFILER_COUNTERS
{
/* HW static counters. */
gctUINT32 gpuClock;
gctUINT32 axiClock;
gctUINT32 shaderClock;
/* HW vairable counters. */
gctUINT32 gpuClockStart;
gctUINT32 gpuClockEnd;
/* HW vairable counters. */
gctUINT32 gpuCyclesCounter;
gctUINT32 gpuTotalRead64BytesPerFrame;
gctUINT32 gpuTotalWrite64BytesPerFrame;
/* PE */
gctUINT32 pe_pixel_count_killed_by_color_pipe;
gctUINT32 pe_pixel_count_killed_by_depth_pipe;
gctUINT32 pe_pixel_count_drawn_by_color_pipe;
gctUINT32 pe_pixel_count_drawn_by_depth_pipe;
/* SH */
gctUINT32 ps_inst_counter;
gctUINT32 rendered_pixel_counter;
gctUINT32 vs_inst_counter;
gctUINT32 rendered_vertice_counter;
gctUINT32 vtx_branch_inst_counter;
gctUINT32 vtx_texld_inst_counter;
gctUINT32 pxl_branch_inst_counter;
gctUINT32 pxl_texld_inst_counter;
/* PA */
gctUINT32 pa_input_vtx_counter;
gctUINT32 pa_input_prim_counter;
gctUINT32 pa_output_prim_counter;
gctUINT32 pa_depth_clipped_counter;
gctUINT32 pa_trivial_rejected_counter;
gctUINT32 pa_culled_counter;
/* SE */
gctUINT32 se_culled_triangle_count;
gctUINT32 se_culled_lines_count;
/* RA */
gctUINT32 ra_valid_pixel_count;
gctUINT32 ra_total_quad_count;
gctUINT32 ra_valid_quad_count_after_early_z;
gctUINT32 ra_total_primitive_count;
gctUINT32 ra_pipe_cache_miss_counter;
gctUINT32 ra_prefetch_cache_miss_counter;
gctUINT32 ra_eez_culled_counter;
/* TX */
gctUINT32 tx_total_bilinear_requests;
gctUINT32 tx_total_trilinear_requests;
gctUINT32 tx_total_discarded_texture_requests;
gctUINT32 tx_total_texture_requests;
gctUINT32 tx_mem_read_count;
gctUINT32 tx_mem_read_in_8B_count;
gctUINT32 tx_cache_miss_count;
gctUINT32 tx_cache_hit_texel_count;
gctUINT32 tx_cache_miss_texel_count;
/* MC */
gctUINT32 mc_total_read_req_8B_from_pipeline;
gctUINT32 mc_total_read_req_8B_from_IP;
gctUINT32 mc_total_write_req_8B_from_pipeline;
/* HI */
gctUINT32 hi_axi_cycles_read_request_stalled;
gctUINT32 hi_axi_cycles_write_request_stalled;
gctUINT32 hi_axi_cycles_write_data_stalled;
}
gcsPROFILER_COUNTERS;
/* HAL profile information. */
typedef struct _gcsPROFILER
{
gctFILE file;
/* Aggregate Information */
/* Clock Info */
gctUINT64 frameStart;
gctUINT64 frameEnd;
/* Current frame information */
gctUINT32 frameNumber;
gctUINT64 frameStartTimeusec;
gctUINT64 frameEndTimeusec;
gctUINT64 frameStartCPUTimeusec;
gctUINT64 frameEndCPUTimeusec;
#if PROFILE_HAL_COUNTERS
gctUINT32 vertexBufferTotalBytesAlloc;
gctUINT32 vertexBufferNewBytesAlloc;
int vertexBufferTotalObjectsAlloc;
int vertexBufferNewObjectsAlloc;
gctUINT32 indexBufferTotalBytesAlloc;
gctUINT32 indexBufferNewBytesAlloc;
int indexBufferTotalObjectsAlloc;
int indexBufferNewObjectsAlloc;
gctUINT32 textureBufferTotalBytesAlloc;
gctUINT32 textureBufferNewBytesAlloc;
int textureBufferTotalObjectsAlloc;
int textureBufferNewObjectsAlloc;
gctUINT32 numCommits;
gctUINT32 drawPointCount;
gctUINT32 drawLineCount;
gctUINT32 drawTriangleCount;
gctUINT32 drawVertexCount;
gctUINT32 redundantStateChangeCalls;
#endif
}
gcsPROFILER;
/* Memory profile information. */
struct _gcsMemProfile
{
/* Memory Usage */
gctUINT32 videoMemUsed;
gctUINT32 systemMemUsed;
gctUINT32 commitBufferSize;
gctUINT32 contextBufferCopyBytes;
};
/* Shader profile information. */
struct _gcsSHADER_PROFILER
{
gctUINT32 shaderLength;
gctUINT32 shaderALUCycles;
gctUINT32 shaderTexLoadCycles;
gctUINT32 shaderTempRegCount;
gctUINT32 shaderSamplerRegCount;
gctUINT32 shaderInputRegCount;
gctUINT32 shaderOutputRegCount;
};
/* Initialize the gcsProfiler. */
gceSTATUS
gcoPROFILER_Initialize(
IN gcoHAL Hal,
IN gctFILE File
);
/* Destroy the gcProfiler. */
gceSTATUS
gcoPROFILER_Destroy(
IN gcoHAL Hal
);
/* Call to signal end of frame. */
gceSTATUS
gcoPROFILER_EndFrame(
IN gcoHAL Hal
);
gceSTATUS
gcoPROFILER_Count(
IN gcoHAL Hal,
IN gctUINT32 Enum,
IN gctINT Value
);
/* Profile input vertex shader. */
gceSTATUS
gcoPROFILER_ShaderVS(
IN gcoHAL Hal,
IN gctPOINTER Vs
);
/* Profile input fragment shader. */
gceSTATUS
gcoPROFILER_ShaderFS(
IN gcoHAL Hal,
IN gctPOINTER Fs
);
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_profiler_h_ */

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_raster_h_
#define __gc_hal_raster_h_
#include "gc_hal_enum.h"
#include "gc_hal_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************\
****************************** Object Declarations *****************************
\******************************************************************************/
typedef struct _gcoBRUSH * gcoBRUSH;
typedef struct _gcoBRUSH_CACHE * gcoBRUSH_CACHE;
/******************************************************************************\
******************************** gcoBRUSH Object *******************************
\******************************************************************************/
/* Create a new solid color gcoBRUSH object. */
gceSTATUS
gcoBRUSH_ConstructSingleColor(
IN gcoHAL Hal,
IN gctUINT32 ColorConvert,
IN gctUINT32 Color,
IN gctUINT64 Mask,
gcoBRUSH * Brush
);
/* Create a new monochrome gcoBRUSH object. */
gceSTATUS
gcoBRUSH_ConstructMonochrome(
IN gcoHAL Hal,
IN gctUINT32 OriginX,
IN gctUINT32 OriginY,
IN gctUINT32 ColorConvert,
IN gctUINT32 FgColor,
IN gctUINT32 BgColor,
IN gctUINT64 Bits,
IN gctUINT64 Mask,
gcoBRUSH * Brush
);
/* Create a color gcoBRUSH object. */
gceSTATUS
gcoBRUSH_ConstructColor(
IN gcoHAL Hal,
IN gctUINT32 OriginX,
IN gctUINT32 OriginY,
IN gctPOINTER Address,
IN gceSURF_FORMAT Format,
IN gctUINT64 Mask,
gcoBRUSH * Brush
);
/* Destroy an gcoBRUSH object. */
gceSTATUS
gcoBRUSH_Destroy(
IN gcoBRUSH Brush
);
/******************************************************************************\
******************************** gcoSURF Object *******************************
\******************************************************************************/
/* Set cipping rectangle. */
gceSTATUS
gcoSURF_SetClipping(
IN gcoSURF Surface
);
/* Clear one or more rectangular areas. */
gceSTATUS
gcoSURF_Clear2D(
IN gcoSURF DestSurface,
IN gctUINT32 RectCount,
IN gcsRECT_PTR DestRect,
IN gctUINT32 LoColor,
IN gctUINT32 HiColor
);
/* Draw one or more Bresenham lines. */
gceSTATUS
gcoSURF_Line(
IN gcoSURF Surface,
IN gctUINT32 LineCount,
IN gcsRECT_PTR Position,
IN gcoBRUSH Brush,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop
);
/* Generic rectangular blit. */
gceSTATUS
gcoSURF_Blit(
IN OPTIONAL gcoSURF SrcSurface,
IN gcoSURF DestSurface,
IN gctUINT32 RectCount,
IN OPTIONAL gcsRECT_PTR SrcRect,
IN gcsRECT_PTR DestRect,
IN OPTIONAL gcoBRUSH Brush,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN OPTIONAL gceSURF_TRANSPARENCY Transparency,
IN OPTIONAL gctUINT32 TransparencyColor,
IN OPTIONAL gctPOINTER Mask,
IN OPTIONAL gceSURF_MONOPACK MaskPack
);
/* Monochrome blit. */
gceSTATUS
gcoSURF_MonoBlit(
IN gcoSURF DestSurface,
IN gctPOINTER Source,
IN gceSURF_MONOPACK SourcePack,
IN gcsPOINT_PTR SourceSize,
IN gcsPOINT_PTR SourceOrigin,
IN gcsRECT_PTR DestRect,
IN OPTIONAL gcoBRUSH Brush,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN gctBOOL ColorConvert,
IN gctUINT8 MonoTransparency,
IN gceSURF_TRANSPARENCY Transparency,
IN gctUINT32 FgColor,
IN gctUINT32 BgColor
);
/* Filter blit. */
gceSTATUS
gcoSURF_FilterBlit(
IN gcoSURF SrcSurface,
IN gcoSURF DestSurface,
IN gcsRECT_PTR SrcRect,
IN gcsRECT_PTR DestRect,
IN gcsRECT_PTR DestSubRect
);
/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
gceSTATUS
gcoSURF_EnableAlphaBlend(
IN gcoSURF Surface,
IN gctUINT8 SrcGlobalAlphaValue,
IN gctUINT8 DstGlobalAlphaValue,
IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
IN gceSURF_PIXEL_COLOR_MODE DstColorMode
);
/* Disable alpha blending engine in the hardware and engage the ROP engine. */
gceSTATUS
gcoSURF_DisableAlphaBlend(
IN gcoSURF Surface
);
/* Copy a rectangular area with format conversion. */
gceSTATUS
gcoSURF_CopyPixels(
IN gcoSURF Source,
IN gcoSURF Target,
IN gctINT SourceX,
IN gctINT SourceY,
IN gctINT TargetX,
IN gctINT TargetY,
IN gctINT Width,
IN gctINT Height
);
/* Read surface pixel. */
gceSTATUS
gcoSURF_ReadPixel(
IN gcoSURF Surface,
IN gctPOINTER Memory,
IN gctINT X,
IN gctINT Y,
IN gceSURF_FORMAT Format,
OUT gctPOINTER PixelValue
);
/* Write surface pixel. */
gceSTATUS
gcoSURF_WritePixel(
IN gcoSURF Surface,
IN gctPOINTER Memory,
IN gctINT X,
IN gctINT Y,
IN gceSURF_FORMAT Format,
IN gctPOINTER PixelValue
);
/******************************************************************************\
********************************** gco2D Object *********************************
\******************************************************************************/
/* Construct a new gco2D object. */
gceSTATUS
gco2D_Construct(
IN gcoHAL Hal,
OUT gco2D * Hardware
);
/* Destroy an gco2D object. */
gceSTATUS
gco2D_Destroy(
IN gco2D Hardware
);
/* Sets the maximum number of brushes in the brush cache. */
gceSTATUS
gco2D_SetBrushLimit(
IN gco2D Hardware,
IN gctUINT MaxCount
);
/* Flush the brush. */
gceSTATUS
gco2D_FlushBrush(
IN gco2D Engine,
IN gcoBRUSH Brush,
IN gceSURF_FORMAT Format
);
/* Program the specified solid color brush. */
gceSTATUS
gco2D_LoadSolidBrush(
IN gco2D Engine,
IN gceSURF_FORMAT Format,
IN gctUINT32 ColorConvert,
IN gctUINT32 Color,
IN gctUINT64 Mask
);
/* Configure monochrome source. */
gceSTATUS
gco2D_SetMonochromeSource(
IN gco2D Engine,
IN gctBOOL ColorConvert,
IN gctUINT8 MonoTransparency,
IN gceSURF_MONOPACK DataPack,
IN gctBOOL CoordRelative,
IN gceSURF_TRANSPARENCY Transparency,
IN gctUINT32 FgColor,
IN gctUINT32 BgColor
);
/* Configure color source. */
gceSTATUS
gco2D_SetColorSource(
IN gco2D Engine,
IN gctUINT32 Address,
IN gctUINT32 Stride,
IN gceSURF_FORMAT Format,
IN gceSURF_ROTATION Rotation,
IN gctUINT32 SurfaceWidth,
IN gctBOOL CoordRelative,
IN gceSURF_TRANSPARENCY Transparency,
IN gctUINT32 TransparencyColor
);
/* Configure color source extension for full rotation. */
gceSTATUS
gco2D_SetColorSourceEx(
IN gco2D Engine,
IN gctUINT32 Address,
IN gctUINT32 Stride,
IN gceSURF_FORMAT Format,
IN gceSURF_ROTATION Rotation,
IN gctUINT32 SurfaceWidth,
IN gctUINT32 SurfaceHeight,
IN gctBOOL CoordRelative,
IN gceSURF_TRANSPARENCY Transparency,
IN gctUINT32 TransparencyColor
);
/* Configure color source. */
gceSTATUS
gco2D_SetColorSourceAdvanced(
IN gco2D Engine,
IN gctUINT32 Address,
IN gctUINT32 Stride,
IN gceSURF_FORMAT Format,
IN gceSURF_ROTATION Rotation,
IN gctUINT32 SurfaceWidth,
IN gctUINT32 SurfaceHeight,
IN gctBOOL CoordRelative
);
/* Configure masked color source. */
gceSTATUS
gco2D_SetMaskedSource(
IN gco2D Engine,
IN gctUINT32 Address,
IN gctUINT32 Stride,
IN gceSURF_FORMAT Format,
IN gctBOOL CoordRelative,
IN gceSURF_MONOPACK MaskPack
);
/* Configure masked color source extension for full rotation. */
gceSTATUS
gco2D_SetMaskedSourceEx(
IN gco2D Engine,
IN gctUINT32 Address,
IN gctUINT32 Stride,
IN gceSURF_FORMAT Format,
IN gctBOOL CoordRelative,
IN gceSURF_MONOPACK MaskPack,
IN gceSURF_ROTATION Rotation,
IN gctUINT32 SurfaceWidth,
IN gctUINT32 SurfaceHeight
);
/* Setup the source rectangle. */
gceSTATUS
gco2D_SetSource(
IN gco2D Engine,
IN gcsRECT_PTR SrcRect
);
/* Set clipping rectangle. */
gceSTATUS
gco2D_SetClipping(
IN gco2D Engine,
IN gcsRECT_PTR Rect
);
/* Configure destination. */
gceSTATUS
gco2D_SetTarget(
IN gco2D Engine,
IN gctUINT32 Address,
IN gctUINT32 Stride,
IN gceSURF_ROTATION Rotation,
IN gctUINT32 SurfaceWidth
);
/* Configure destination extension for full rotation. */
gceSTATUS
gco2D_SetTargetEx(
IN gco2D Engine,
IN gctUINT32 Address,
IN gctUINT32 Stride,
IN gceSURF_ROTATION Rotation,
IN gctUINT32 SurfaceWidth,
IN gctUINT32 SurfaceHeight
);
/* Calculate and program the stretch factors. */
gceSTATUS
gco2D_SetStretchFactors(
IN gco2D Engine,
IN gctUINT32 HorFactor,
IN gctUINT32 VerFactor
);
/* Calculate and program the stretch factors based on the rectangles. */
gceSTATUS
gco2D_SetStretchRectFactors(
IN gco2D Engine,
IN gcsRECT_PTR SrcRect,
IN gcsRECT_PTR DestRect
);
/* Create a new solid color gcoBRUSH object. */
gceSTATUS
gco2D_ConstructSingleColorBrush(
IN gco2D Engine,
IN gctUINT32 ColorConvert,
IN gctUINT32 Color,
IN gctUINT64 Mask,
gcoBRUSH * Brush
);
/* Create a new monochrome gcoBRUSH object. */
gceSTATUS
gco2D_ConstructMonochromeBrush(
IN gco2D Engine,
IN gctUINT32 OriginX,
IN gctUINT32 OriginY,
IN gctUINT32 ColorConvert,
IN gctUINT32 FgColor,
IN gctUINT32 BgColor,
IN gctUINT64 Bits,
IN gctUINT64 Mask,
gcoBRUSH * Brush
);
/* Create a color gcoBRUSH object. */
gceSTATUS
gco2D_ConstructColorBrush(
IN gco2D Engine,
IN gctUINT32 OriginX,
IN gctUINT32 OriginY,
IN gctPOINTER Address,
IN gceSURF_FORMAT Format,
IN gctUINT64 Mask,
gcoBRUSH * Brush
);
/* Clear one or more rectangular areas. */
gceSTATUS
gco2D_Clear(
IN gco2D Engine,
IN gctUINT32 RectCount,
IN gcsRECT_PTR Rect,
IN gctUINT32 Color32,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN gceSURF_FORMAT DestFormat
);
/* Draw one or more Bresenham lines. */
gceSTATUS
gco2D_Line(
IN gco2D Engine,
IN gctUINT32 LineCount,
IN gcsRECT_PTR Position,
IN gcoBRUSH Brush,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN gceSURF_FORMAT DestFormat
);
/* Draw one or more Bresenham lines based on the 32-bit color. */
gceSTATUS
gco2D_ColorLine(
IN gco2D Engine,
IN gctUINT32 LineCount,
IN gcsRECT_PTR Position,
IN gctUINT32 Color32,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN gceSURF_FORMAT DestFormat
);
/* Generic blit. */
gceSTATUS
gco2D_Blit(
IN gco2D Engine,
IN gctUINT32 RectCount,
IN gcsRECT_PTR Rect,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN gceSURF_FORMAT DestFormat
);
/* Batch blit. */
gceSTATUS
gco2D_BatchBlit(
IN gco2D Engine,
IN gctUINT32 RectCount,
IN gcsRECT_PTR SrcRect,
IN gcsRECT_PTR DestRect,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN gceSURF_FORMAT DestFormat
);
/* Stretch blit. */
gceSTATUS
gco2D_StretchBlit(
IN gco2D Engine,
IN gctUINT32 RectCount,
IN gcsRECT_PTR Rect,
IN gctUINT8 FgRop,
IN gctUINT8 BgRop,
IN gceSURF_FORMAT DestFormat
);
/* Monochrome blit. */
gceSTATUS
gco2D_MonoBlit(
IN gco2D Engine,
IN gctPOINTER StreamBits,
IN gcsPOINT_PTR StreamSize,
IN gcsRECT_PTR StreamRect,
IN gceSURF_MONOPACK SrcStreamPack,
IN gceSURF_MONOPACK DestStreamPack,
IN gcsRECT_PTR DestRect,
IN gctUINT32 FgRop,
IN gctUINT32 BgRop,
IN gceSURF_FORMAT DestFormat
);
/* Set kernel size. */
gceSTATUS
gco2D_SetKernelSize(
IN gco2D Engine,
IN gctUINT8 HorKernelSize,
IN gctUINT8 VerKernelSize
);
/* Set filter type. */
gceSTATUS
gco2D_SetFilterType(
IN gco2D Engine,
IN gceFILTER_TYPE FilterType
);
/* Set the filter kernel by user. */
gceSTATUS
gco2D_SetUserFilterKernel(
IN gco2D Engine,
IN gceFILTER_PASS_TYPE PassType,
IN gctUINT16_PTR KernelArray
);
/* Select the pass(es) to be done for user defined filter. */
gceSTATUS
gco2D_EnableUserFilterPasses(
IN gco2D Engine,
IN gctBOOL HorPass,
IN gctBOOL VerPass
);
/* Frees the temporary buffer allocated by filter blit operation. */
gceSTATUS
gco2D_FreeFilterBuffer(
IN gco2D Engine
);
/* Filter blit. */
gceSTATUS
gco2D_FilterBlit(
IN gco2D Engine,
IN gctUINT32 SrcAddress,
IN gctUINT SrcStride,
IN gctUINT32 SrcUAddress,
IN gctUINT SrcUStride,
IN gctUINT32 SrcVAddress,
IN gctUINT SrcVStride,
IN gceSURF_FORMAT SrcFormat,
IN gceSURF_ROTATION SrcRotation,
IN gctUINT32 SrcSurfaceWidth,
IN gcsRECT_PTR SrcRect,
IN gctUINT32 DestAddress,
IN gctUINT DestStride,
IN gceSURF_FORMAT DestFormat,
IN gceSURF_ROTATION DestRotation,
IN gctUINT32 DestSurfaceWidth,
IN gcsRECT_PTR DestRect,
IN gcsRECT_PTR DestSubRect
);
/* Filter blit extension for full rotation. */
gceSTATUS
gco2D_FilterBlitEx(
IN gco2D Engine,
IN gctUINT32 SrcAddress,
IN gctUINT SrcStride,
IN gctUINT32 SrcUAddress,
IN gctUINT SrcUStride,
IN gctUINT32 SrcVAddress,
IN gctUINT SrcVStride,
IN gceSURF_FORMAT SrcFormat,
IN gceSURF_ROTATION SrcRotation,
IN gctUINT32 SrcSurfaceWidth,
IN gctUINT32 SrcSurfaceHeight,
IN gcsRECT_PTR SrcRect,
IN gctUINT32 DestAddress,
IN gctUINT DestStride,
IN gceSURF_FORMAT DestFormat,
IN gceSURF_ROTATION DestRotation,
IN gctUINT32 DestSurfaceWidth,
IN gctUINT32 DestSurfaceHeight,
IN gcsRECT_PTR DestRect,
IN gcsRECT_PTR DestSubRect
);
/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
gceSTATUS
gco2D_EnableAlphaBlend(
IN gco2D Engine,
IN gctUINT8 SrcGlobalAlphaValue,
IN gctUINT8 DstGlobalAlphaValue,
IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
IN gceSURF_PIXEL_COLOR_MODE DstColorMode
);
/* Enable alpha blending engine in the hardware. */
gceSTATUS
gco2D_EnableAlphaBlendAdvanced(
IN gco2D Engine,
IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
IN gceSURF_BLEND_FACTOR_MODE DstFactorMode
);
/* Enable alpha blending engine with Porter Duff rule. */
gceSTATUS
gco2D_SetPorterDuffBlending(
IN gco2D Engine,
IN gce2D_PORTER_DUFF_RULE Rule
);
/* Disable alpha blending engine in the hardware and engage the ROP engine. */
gceSTATUS
gco2D_DisableAlphaBlend(
IN gco2D Engine
);
/* Retrieve the maximum number of 32-bit data chunks for a single DE command. */
gctUINT32
gco2D_GetMaximumDataCount(
void
);
/* Retrieve the maximum number of rectangles, that can be passed in a single DE command. */
gctUINT32
gco2D_GetMaximumRectCount(
void
);
/* Returns the pixel alignment of the surface. */
gceSTATUS
gco2D_GetPixelAlignment(
gceSURF_FORMAT Format,
gcsPOINT_PTR Alignment
);
/* Retrieve monochrome stream pack size. */
gceSTATUS
gco2D_GetPackSize(
IN gceSURF_MONOPACK StreamPack,
OUT gctUINT32 * PackWidth,
OUT gctUINT32 * PackHeight
);
/* Flush the 2D pipeline. */
gceSTATUS
gco2D_Flush(
IN gco2D Engine
);
/* Load 256-entry color table for INDEX8 source surfaces. */
gceSTATUS
gco2D_LoadPalette(
IN gco2D Engine,
IN gctUINT FirstIndex,
IN gctUINT IndexCount,
IN gctPOINTER ColorTable,
IN gctBOOL ColorConvert
);
/* Enable/disable 2D BitBlt mirrorring. */
gceSTATUS
gco2D_SetBitBlitMirror(
IN gco2D Engine,
IN gctBOOL HorizontalMirror,
IN gctBOOL VerticalMirror
);
/* Set the transparency for source, destination and pattern. */
gceSTATUS
gco2D_SetTransparencyAdvanced(
IN gco2D Engine,
IN gce2D_TRANSPARENCY SrcTransparency,
IN gce2D_TRANSPARENCY DstTransparency,
IN gce2D_TRANSPARENCY PatTransparency
);
/* Set the source color key. */
gceSTATUS
gco2D_SetSourceColorKeyAdvanced(
IN gco2D Engine,
IN gctUINT32 ColorKey
);
/* Set the source color key range. */
gceSTATUS
gco2D_SetSourceColorKeyRangeAdvanced(
IN gco2D Engine,
IN gctUINT32 ColorKeyLow,
IN gctUINT32 ColorKeyHigh
);
/* Set the target color key. */
gceSTATUS
gco2D_SetTargetColorKeyAdvanced(
IN gco2D Engine,
IN gctUINT32 ColorKey
);
/* Set the target color key range. */
gceSTATUS
gco2D_SetTargetColorKeyRangeAdvanced(
IN gco2D Engine,
IN gctUINT32 ColorKeyLow,
IN gctUINT32 ColorKeyHigh
);
/* Set the YUV color space mode. */
gceSTATUS
gco2D_SetYUVColorMode(
IN gco2D Engine,
IN gce2D_YUV_COLOR_MODE Mode
);
/* Setup the source global color value in ARGB8 format. */
gceSTATUS gco2D_SetSourceGlobalColorAdvanced(
IN gco2D Engine,
IN gctUINT32 Color32
);
/* Setup the target global color value in ARGB8 format. */
gceSTATUS gco2D_SetTargetGlobalColorAdvanced(
IN gco2D Engine,
IN gctUINT32 Color32
);
/* Setup the source and target pixel multiply modes. */
gceSTATUS
gco2D_SetPixelMultiplyModeAdvanced(
IN gco2D Engine,
IN gce2D_PIXEL_COLOR_MULTIPLY_MODE SrcPremultiplySrcAlpha,
IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstPremultiplyDstAlpha,
IN gce2D_GLOBAL_COLOR_MULTIPLY_MODE SrcPremultiplyGlobalMode,
IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstDemultiplyDstAlpha
);
/* Set the GPU clock cycles after which the idle engine will keep auto-flushing. */
gceSTATUS
gco2D_SetAutoFlushCycles(
IN gco2D Engine,
IN gctUINT32 Cycles
);
/* Read the profile registers available in the 2D engine and sets them in the profile.
The function will also reset the pixelsRendered counter every time.
*/
gceSTATUS
gco2D_ProfileEngine(
IN gco2D Engine,
OPTIONAL gcs2D_PROFILE_PTR Profile
);
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_raster_h_ */

544
drivers/staging/rk29/vivante/hal/inc/gc_hal_types.h Normal file
View File

@ -0,0 +1,544 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_types_h_
#define __gc_hal_types_h_
#include "gc_hal_options.h"
#ifdef _WIN32
#pragma warning(disable:4127) /* Conditional expression is constant (do { }
** while(0)). */
#pragma warning(disable:4100) /* Unreferenced formal parameter. */
#pragma warning(disable:4204) /* Non-constant aggregate initializer (C99). */
#pragma warning(disable:4131) /* Uses old-style declarator (for Bison and
** Flex generated files). */
#pragma warning(disable:4206) /* Translation unit is empty. */
#endif
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************\
** Platform macros.
*/
#if defined(__GNUC__)
# define gcdHAS_ELLIPSES 1 /* GCC always has it. */
#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)
# define gcdHAS_ELLIPSES 1 /* C99 has it. */
#elif defined(_MSC_VER) && (_MSC_VER >= 1500)
# define gcdHAS_ELLIPSES 1 /* MSVC 2007+ has it. */
#elif defined(UNDER_CE)
# define gcdHAS_ELLIPSES 0 /* Windows CE doesn't have it. */
#else
# error "gcdHAS_ELLIPSES: Platform could not be determined"
#endif
/******************************************************************************\
************************************ Keyword ***********************************
\******************************************************************************/
#if (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L))
# define gcmINLINE inline /* C99 keyword. */
#elif defined(__GNUC__)
# define gcmINLINE __inline__ /* GNU keyword. */
#elif defined(_MSC_VER) || defined(UNDER_CE)
# define gcmINLINE __inline /* Internal keyword. */
#else
# error "gcmINLINE: Platform could not be determined"
#endif
#ifndef gcdDEBUG
# if (defined(DBG) && DBG) || defined(DEBUG) || defined(_DEBUG)
# define gcdDEBUG 1
# else
# define gcdDEBUG 0
# endif
#endif
#ifdef _USRDLL
# ifdef _MSC_VER
# ifdef HAL_EXPORTS
# define HALAPI __declspec(dllexport)
# else
# define HALAPI __declspec(dllimport)
# endif
# define HALDECL __cdecl
# else
# ifdef HAL_EXPORTS
# define HALAPI
# else
# define HALAPI extern
# endif
# endif
#else
# define HALAPI
# define HALDECL
#endif
/******************************************************************************\
********************************** Common Types ********************************
\******************************************************************************/
#define gcvFALSE 0
#define gcvTRUE 1
#define gcvINFINITE ((gctUINT32) ~0U)
typedef int gctBOOL;
typedef gctBOOL * gctBOOL_PTR;
typedef int gctINT;
typedef signed char gctINT8;
typedef signed short gctINT16;
typedef signed int gctINT32;
typedef signed long long gctINT64;
typedef gctINT * gctINT_PTR;
typedef gctINT8 * gctINT8_PTR;
typedef gctINT16 * gctINT16_PTR;
typedef gctINT32 * gctINT32_PTR;
typedef gctINT64 * gctINT64_PTR;
typedef unsigned int gctUINT;
typedef unsigned char gctUINT8;
typedef unsigned short gctUINT16;
typedef unsigned int gctUINT32;
typedef unsigned long long gctUINT64;
typedef gctUINT * gctUINT_PTR;
typedef gctUINT8 * gctUINT8_PTR;
typedef gctUINT16 * gctUINT16_PTR;
typedef gctUINT32 * gctUINT32_PTR;
typedef gctUINT64 * gctUINT64_PTR;
typedef unsigned long gctSIZE_T;
typedef gctSIZE_T * gctSIZE_T_PTR;
#ifdef __cplusplus
# define gcvNULL 0
#else
# define gcvNULL ((void *) 0)
#endif
typedef float gctFLOAT;
typedef signed int gctFIXED_POINT;
typedef float * gctFLOAT_PTR;
typedef void * gctPHYS_ADDR;
typedef void * gctHANDLE;
typedef void * gctFILE;
typedef void * gctSIGNAL;
typedef void * gctWINDOW;
typedef void * gctIMAGE;
typedef void * gctPOINTER;
typedef const void * gctCONST_POINTER;
typedef char gctCHAR;
typedef char * gctSTRING;
typedef const char * gctCONST_STRING;
typedef struct _gcsCOUNT_STRING
{
gctSIZE_T Length;
gctCONST_STRING String;
}
gcsCOUNT_STRING;
/* Fixed point constants. */
#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
/******************************************************************************\
******************************* Fixed Point Math *******************************
\******************************************************************************/
#define gcmXMultiply(x1, x2) \
(gctFIXED_POINT) (((gctINT64) (x1) * (x2)) >> 16)
#define gcmXDivide(x1, x2) \
(gctFIXED_POINT) ((((gctINT64) (x1)) << 16) / (x2))
#define gcmXMultiplyDivide(x1, x2, x3) \
(gctFIXED_POINT) ((gctINT64) (x1) * (x2) / (x3))
/* 2D Engine profile. */
struct gcs2D_PROFILE
{
/* Cycle count.
32bit counter incremented every 2D clock cycle.
Wraps back to 0 when the counter overflows.
*/
gctUINT32 cycleCount;
/* Pixels rendered by the 2D engine.
Resets to 0 every time it is read. */
gctUINT32 pixelsRendered;
};
/* Macro to combine four characters into a Charcater Code. */
#define gcmCC(c1, c2, c3, c4) \
( \
(char) (c1) \
| \
((char) (c2) << 8) \
| \
((char) (c3) << 16) \
| \
((char) (c4) << 24) \
)
#define gcmPRINTABLE(c) ((((c) >= ' ') && ((c) <= '}')) ? (c) : ' ')
#define gcmCC_PRINT(cc) \
gcmPRINTABLE((char) ( (cc) & 0xFF)), \
gcmPRINTABLE((char) (((cc) >> 8) & 0xFF)), \
gcmPRINTABLE((char) (((cc) >> 16) & 0xFF)), \
gcmPRINTABLE((char) (((cc) >> 24) & 0xFF))
/******************************************************************************\
****************************** Function Parameters *****************************
\******************************************************************************/
#define IN
#define OUT
#define OPTIONAL
/******************************************************************************\
********************************* Status Codes *********************************
\******************************************************************************/
typedef enum _gceSTATUS
{
gcvSTATUS_OK = 0,
gcvSTATUS_FALSE = 0,
gcvSTATUS_TRUE = 1,
gcvSTATUS_NO_MORE_DATA = 2,
gcvSTATUS_CACHED = 3,
gcvSTATUS_MIPMAP_TOO_LARGE = 4,
gcvSTATUS_NAME_NOT_FOUND = 5,
gcvSTATUS_NOT_OUR_INTERRUPT = 6,
gcvSTATUS_MISMATCH = 7,
gcvSTATUS_MIPMAP_TOO_SMALL = 8,
gcvSTATUS_LARGER = 9,
gcvSTATUS_SMALLER = 10,
gcvSTATUS_CHIP_NOT_READY = 11,
gcvSTATUS_NEED_CONVERSION = 12,
gcvSTATUS_SKIP = 13,
gcvSTATUS_DATA_TOO_LARGE = 14,
gcvSTATUS_INVALID_CONFIG = 15,
gcvSTATUS_CHANGED = 16,
gcvSTATUS_INVALID_ARGUMENT = -1,
gcvSTATUS_INVALID_OBJECT = -2,
gcvSTATUS_OUT_OF_MEMORY = -3,
gcvSTATUS_MEMORY_LOCKED = -4,
gcvSTATUS_MEMORY_UNLOCKED = -5,
gcvSTATUS_HEAP_CORRUPTED = -6,
gcvSTATUS_GENERIC_IO = -7,
gcvSTATUS_INVALID_ADDRESS = -8,
gcvSTATUS_CONTEXT_LOSSED = -9,
gcvSTATUS_TOO_COMPLEX = -10,
gcvSTATUS_BUFFER_TOO_SMALL = -11,
gcvSTATUS_INTERFACE_ERROR = -12,
gcvSTATUS_NOT_SUPPORTED = -13,
gcvSTATUS_MORE_DATA = -14,
gcvSTATUS_TIMEOUT = -15,
gcvSTATUS_OUT_OF_RESOURCES = -16,
gcvSTATUS_INVALID_DATA = -17,
gcvSTATUS_INVALID_MIPMAP = -18,
gcvSTATUS_NOT_FOUND = -19,
gcvSTATUS_NOT_ALIGNED = -20,
gcvSTATUS_INVALID_REQUEST = -21,
gcvSTATUS_GPU_NOT_RESPONDING = -22,
/* Linker errors. */
gcvSTATUS_GLOBAL_TYPE_MISMATCH = -1000,
gcvSTATUS_TOO_MANY_ATTRIBUTES = -1001,
gcvSTATUS_TOO_MANY_UNIFORMS = -1002,
gcvSTATUS_TOO_MANY_VARYINGS = -1003,
gcvSTATUS_UNDECLARED_VARYING = -1004,
gcvSTATUS_VARYING_TYPE_MISMATCH = -1005,
gcvSTATUS_MISSING_MAIN = -1006,
gcvSTATUS_NAME_MISMATCH = -1007,
gcvSTATUS_INVALID_INDEX = -1008,
}
gceSTATUS;
/******************************************************************************\
********************************* Status Macros ********************************
\******************************************************************************/
#define gcmIS_ERROR(status) (status < 0)
#define gcmNO_ERROR(status) (status >= 0)
#define gcmIS_SUCCESS(status) (status == gcvSTATUS_OK)
/******************************************************************************\
********************************* Field Macros *********************************
\******************************************************************************/
#define __gcmSTART(reg_field) \
(0 ? reg_field)
#define __gcmEND(reg_field) \
(1 ? reg_field)
#define __gcmGETSIZE(reg_field) \
(__gcmEND(reg_field) - __gcmSTART(reg_field) + 1)
#define __gcmALIGN(data, reg_field) \
(((gctUINT32) (data)) << __gcmSTART(reg_field))
#define __gcmMASK(reg_field) \
((gctUINT32) ((__gcmGETSIZE(reg_field) == 32) \
? ~0 \
: (~(~0 << __gcmGETSIZE(reg_field)))))
/*******************************************************************************
**
** gcmFIELDMASK
**
** Get aligned field mask.
**
** ARGUMENTS:
**
** reg Name of register.
** field Name of field within register.
*/
#define gcmFIELDMASK(reg, field) \
( \
__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field) \
)
/*******************************************************************************
**
** gcmGETFIELD
**
** Extract the value of a field from specified data.
**
** ARGUMENTS:
**
** data Data value.
** reg Name of register.
** field Name of field within register.
*/
#define gcmGETFIELD(data, reg, field) \
( \
((((gctUINT32) (data)) >> __gcmSTART(reg##_##field)) \
& __gcmMASK(reg##_##field)) \
)
/*******************************************************************************
**
** gcmSETFIELD
**
** Set the value of a field within specified data.
**
** ARGUMENTS:
**
** data Data value.
** reg Name of register.
** field Name of field within register.
** value Value for field.
*/
#define gcmSETFIELD(data, reg, field, value) \
( \
(((gctUINT32) (data)) \
& ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
| __gcmALIGN((gctUINT32) (value) \
& __gcmMASK(reg##_##field), reg##_##field) \
)
/*******************************************************************************
**
** gcmSETFIELDVALUE
**
** Set the value of a field within specified data with a
** predefined value.
**
** ARGUMENTS:
**
** data Data value.
** reg Name of register.
** field Name of field within register.
** value Name of the value within the field.
*/
#define gcmSETFIELDVALUE(data, reg, field, value) \
( \
(((gctUINT32) (data)) \
& ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
| __gcmALIGN(reg##_##field##_##value \
& __gcmMASK(reg##_##field), reg##_##field) \
)
/*******************************************************************************
**
** gcmSETMASKEDFIELD
**
** Set the value of a masked field with specified data.
**
** ARGUMENTS:
**
** reg Name of register.
** field Name of field within register.
** value Value for field.
*/
#define gcmSETMASKEDFIELD(reg, field, value) \
( \
gcmSETFIELD(~0, reg, field, value) & \
gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
)
/*******************************************************************************
**
** gcmVERIFYFIELDVALUE
**
** Verify if the value of a field within specified data equals a
** predefined value.
**
** ARGUMENTS:
**
** data Data value.
** reg Name of register.
** field Name of field within register.
** value Name of the value within the field.
*/
#define gcmVERIFYFIELDVALUE(data, reg, field, value) \
( \
(((gctUINT32) (data)) >> __gcmSTART(reg##_##field) & \
__gcmMASK(reg##_##field)) \
== \
(reg##_##field##_##value & __gcmMASK(reg##_##field)) \
)
/*******************************************************************************
** Bit field macros.
*/
#define __gcmSTARTBIT(Field) \
( 1 ? Field )
#define __gcmBITSIZE(Field) \
( 0 ? Field )
#define __gcmBITMASK(Field) \
( \
(1 << __gcmBITSIZE(Field)) - 1 \
)
#define gcmGETBITS(Value, Type, Field) \
( \
( ((Type) (Value)) >> __gcmSTARTBIT(Field) ) \
& \
__gcmBITMASK(Field) \
)
#define gcmSETBITS(Value, Type, Field, NewValue) \
( \
( ((Type) (Value)) \
& ~(__gcmBITMASK(Field) << __gcmSTARTBIT(Field)) \
) \
| \
( ( ((Type) (NewValue)) \
& __gcmBITMASK(Field) \
) << __gcmSTARTBIT(Field) \
) \
)
/******************************************************************************\
******************************** Min/Max Macros ********************************
\******************************************************************************/
#define gcmMIN(x, y) (((x) <= (y)) ? (x) : (y))
#define gcmMAX(x, y) (((x) >= (y)) ? (x) : (y))
#define gcmCLAMP(x, min, max) (((x) < (min)) ? (min) : \
((x) > (max)) ? (max) : (x))
#define gcmABS(x) (((x) < 0) ? -(x) : (x))
#define gcmNEG(x) (((x) < 0) ? (x) : -(x))
/*******************************************************************************
**
** gcmPTR2INT
**
** Convert a pointer to an integer value.
**
** ARGUMENTS:
**
** p Pointer value.
*/
#if defined(_WIN32) || (defined(__LP64__) && __LP64__)
# define gcmPTR2INT(p) \
( \
(gctUINT32) (gctUINT64) (p) \
)
#else
# define gcmPTR2INT(p) \
( \
(gctUINT32) (p) \
)
#endif
/*******************************************************************************
**
** gcmINT2PTR
**
** Convert an integer value into a pointer.
**
** ARGUMENTS:
**
** v Integer value.
*/
#define gcmINT2PTR(i) \
( \
(gctPOINTER) (i) \
)
/*******************************************************************************
**
** gcmOFFSETOF
**
** Compute the byte offset of a field inside a structure.
**
** ARGUMENTS:
**
** s Structure name.
** field Field name.
*/
#define gcmOFFSETOF(s, field) \
( \
gcmPTR2INT(& (((struct s *) 0)->field)) \
)
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_types_h_ */

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_kernel_h_
#define __gc_hal_kernel_h_
#include "gc_hal.h"
#include "gc_hal_kernel_hardware.h"
#include "gc_hal_driver.h"
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************\
********************************** Structures **********************************
\******************************************************************************/
#if gcdSECURE_USER
typedef struct _gckLOGICAL_CACHE
{
gctHANDLE process;
gctPOINTER logical;
gctUINT32 dma;
gctUINT64 stamp;
}
gckLOGICAL_CACHE;
#endif
/* gckKERNEL object. */
struct _gckKERNEL
{
/* Object. */
gcsOBJECT object;
/* Pointer to gckOS object. */
gckOS os;
/* Pointer to gckHARDWARE object. */
gckHARDWARE hardware;
/* Pointer to gckCOMMAND object. */
gckCOMMAND command;
/* Pointer to gckEVENT object. */
gckEVENT event;
/* Pointer to context. */
gctPOINTER context;
/* Pointer to gckMMU object. */
gckMMU mmu;
/* Arom holding number of clients. */
gctPOINTER atomClients;
#if VIVANTE_PROFILER
/* Enable profiling */
gctBOOL profileEnable;
/* The profile file name */
gctCHAR profileFileName[gcdMAX_PROFILE_FILE_NAME];
#endif
#if gcdSECURE_USER
gckLOGICAL_CACHE cache[gcdSECURE_CACHE_SLOTS];
gctUINT cacheSlots;
gctUINT64 cacheTimeStamp;
#endif
};
#define gcdCOMMAND_QUEUES 2
/* gckCOMMAND object. */
struct _gckCOMMAND
{
/* Object. */
gcsOBJECT object;
/* Pointer to required object. */
gckKERNEL kernel;
gckOS os;
/* Number of bytes per page. */
gctSIZE_T pageSize;
/* Current pipe select. */
gctUINT32 pipeSelect;
/* Command queue running flag. */
gctBOOL running;
/* Idle flag and commit stamp. */
gctBOOL idle;
gctUINT64 commitStamp;
/* Command queue mutex. */
gctPOINTER mutexQueue;
/* Context switching mutex. */
gctPOINTER mutexContext;
/* Command queue power semaphore. */
gctPOINTER powerSemaphore;
/* Current command queue. */
struct _gcskCOMMAND_QUEUE
{
gctSIGNAL signal;
gctPHYS_ADDR physical;
gctPOINTER logical;
}
queues[gcdCOMMAND_QUEUES];
gctPHYS_ADDR physical;
gctPOINTER logical;
gctINT index;
gctUINT32 offset;
/* The command queue is new. */
gctBOOL newQueue;
gctBOOL submit;
/* Context counter used for unique ID. */
gctUINT64 contextCounter;
/* Current context ID. */
gctUINT64 currentContext;
/* Pointer to last WAIT command. */
gctPOINTER wait;
gctSIZE_T waitSize;
/* Command buffer alignment. */
gctSIZE_T alignment;
gctSIZE_T reservedHead;
gctSIZE_T reservedTail;
/* Commit counter. */
gctPOINTER atomCommit;
};
typedef struct _gcsEVENT * gcsEVENT_PTR;
/* Structure holding one event to be processed. */
typedef struct _gcsEVENT
{
/* Pointer to next event in queue. */
gcsEVENT_PTR next;
/* Event information. */
gcsHAL_INTERFACE event;
#ifdef __QNXNTO__
/* Kernel. */
gckKERNEL kernel;
#endif
}
gcsEVENT;
/* Structure holding a list of events to be processed by an interrupt. */
typedef struct _gcsEVENT_QUEUE
{
/* Time stamp. */
gctUINT64 stamp;
/* Source of the event. */
gceKERNEL_WHERE source;
/* Pointer to head of event queue. */
gcsEVENT_PTR head;
/* Pointer to tail of event queue. */
gcsEVENT_PTR tail;
/* Process ID owning the event queue. */
gctUINT32 processID;
}
gcsEVENT_QUEUE;
/* gckEVENT object. */
struct _gckEVENT
{
/* The object. */
gcsOBJECT object;
/* Pointer to required objects. */
gckOS os;
gckKERNEL kernel;
/* Time stamp. */
gctUINT64 stamp;
gctUINT64 lastCommitStamp;
/* Queue mutex. */
gctPOINTER mutexQueue;
/* Array of event queues. */
gcsEVENT_QUEUE queues[31];
gctUINT8 lastID;
/* Pending events. */
volatile gctUINT pending;
/* List of free event structures and its mutex. */
gcsEVENT_PTR freeList;
gctSIZE_T freeCount;
gctPOINTER freeMutex;
/* Events queued to be added to an event queue and its mutex. */
gcsEVENT_QUEUE list;
gctPOINTER listMutex;
};
/* gcuVIDMEM_NODE structure. */
typedef union _gcuVIDMEM_NODE
{
/* Allocated from gckVIDMEM. */
struct _gcsVIDMEM_NODE_VIDMEM
{
/* Owner of this node. */
gckVIDMEM memory;
/* Dual-linked list of nodes. */
gcuVIDMEM_NODE_PTR next;
gcuVIDMEM_NODE_PTR prev;
/* Dual linked list of free nodes. */
gcuVIDMEM_NODE_PTR nextFree;
gcuVIDMEM_NODE_PTR prevFree;
/* Information for this node. */
gctUINT32 offset;
gctSIZE_T bytes;
gctUINT32 alignment;
#ifdef __QNXNTO__
/* Client/server vaddr (mapped using mmap_join). */
gctPOINTER logical;
/* Unique handle of the caller process channel. */
gctHANDLE handle;
#endif
/* Locked counter. */
gctINT32 locked;
/* Memory pool. */
gcePOOL pool;
gctUINT32 physical;
}
VidMem;
/* Allocated from gckOS. */
struct _gcsVIDMEM_NODE_VIRTUAL
{
/* Pointer to gckKERNEL object. */
gckKERNEL kernel;
/* Information for this node. */
gctBOOL contiguous;
gctPHYS_ADDR physical;
gctSIZE_T bytes;
gctPOINTER logical;
/* Page table information. */
gctSIZE_T pageCount;
gctPOINTER pageTable;
gctUINT32 address;
/* Mutex. */
gctPOINTER mutex;
/* Locked counter. */
gctINT32 locked;
#ifdef __QNXNTO__
/* Single linked list of nodes. */
gcuVIDMEM_NODE_PTR next;
/* PID of the caller process channel. */
gctUINT32 userPID;
/* Unique handle of the caller process channel. */
gctHANDLE handle;
/* Unlock pending flag. */
gctBOOL unlockPending;
/* Free pending flag. */
gctBOOL freePending;
#else
/* Pending flag. */
gctBOOL pending;
#endif
}
Virtual;
}
gcuVIDMEM_NODE;
/* gckVIDMEM object. */
struct _gckVIDMEM
{
/* Object. */
gcsOBJECT object;
/* Pointer to gckOS object. */
gckOS os;
/* Information for this video memory heap. */
gctUINT32 baseAddress;
gctSIZE_T bytes;
gctSIZE_T freeBytes;
/* Mapping for each type of surface. */
gctINT mapping[gcvSURF_NUM_TYPES];
/* Sentinel nodes for up to 8 banks. */
gcuVIDMEM_NODE sentinel[8];
/* Allocation threshold. */
gctSIZE_T threshold;
/* The heap mutex. */
gctPOINTER mutex;
};
/* gckMMU object. */
struct _gckMMU
{
/* The object. */
gcsOBJECT object;
/* Pointer to gckOS object. */
gckOS os;
/* Pointer to gckHARDWARE object. */
gckHARDWARE hardware;
/* The page table mutex. */
gctPOINTER pageTableMutex;
/* Page table information. */
gctSIZE_T pageTableSize;
gctPHYS_ADDR pageTablePhysical;
gctUINT32_PTR pageTableLogical;
gctUINT32 pageTableEntries;
/* Free entries. */
gctUINT32 heapList;
gctBOOL freeNodes;
#ifdef __QNXNTO__
/* Single linked list of all allocated nodes. */
gctPOINTER nodeMutex;
gcuVIDMEM_NODE_PTR nodeList;
#endif
};
gceSTATUS
gckKERNEL_AttachProcess(
IN gckKERNEL Kernel,
IN gctBOOL Attach
);
#if gcdSECURE_USER
gceSTATUS
gckKERNEL_MapLogicalToPhysical(
IN gckKERNEL Kernel,
IN gctHANDLE Process,
IN OUT gctPOINTER * Data
);
#endif
gceSTATUS
gckHARDWARE_QueryIdle(
IN gckHARDWARE Hardware,
OUT gctBOOL_PTR IsIdle
);
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_kernel_h_ */

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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#include "gc_hal_kernel_precomp.h"
#define _GC_OBJ_ZONE gcvZONE_MMU
typedef enum _gceMMU_TYPE
{
gcvMMU_USED = 0,
gcvMMU_SINGLE,
gcvMMU_FREE,
}
gceMMU_TYPE;
static gceSTATUS
_Link(
IN gckMMU Mmu,
IN gctUINT32 Index,
IN gctUINT32 Next
)
{
if (Index >= Mmu->pageTableEntries)
{
/* Just move heap pointer. */
Mmu->heapList = Next;
}
else
{
/* Address page table. */
gctUINT32_PTR pageTable = Mmu->pageTableLogical;
/* Dispatch on node type. */
switch (pageTable[Index] & 0xFF)
{
case gcvMMU_SINGLE:
/* Set single index. */
pageTable[Index] = (Next << 8) | gcvMMU_SINGLE;
break;
case gcvMMU_FREE:
/* Set index. */
pageTable[Index + 1] = Next;
break;
default:
gcmkFATAL("MMU table correcupted at index %u!", Index);
return gcvSTATUS_HEAP_CORRUPTED;
}
}
/* Success. */
return gcvSTATUS_OK;
}
static gceSTATUS
_AddFree(
IN gckMMU Mmu,
IN gctUINT32 Index,
IN gctUINT32 Node,
IN gctUINT32 Count
)
{
gctUINT32_PTR pageTable = Mmu->pageTableLogical;
if (Count == 1)
{
/* Initialize a single page node. */
pageTable[Node] = (~0U << 8) | gcvMMU_SINGLE;
}
else
{
/* Initialize the node. */
pageTable[Node + 0] = (Count << 8) | gcvMMU_FREE;
pageTable[Node + 1] = ~0U;
}
/* Append the node. */
return _Link(Mmu, Index, Node);
}
static gceSTATUS
_Collect(
IN gckMMU Mmu
)
{
gctUINT32_PTR pageTable = Mmu->pageTableLogical;
gceSTATUS status;
gctUINT32 i, previous, start = 0, count = 0;
/* Flush the MMU cache. */
gcmkONERROR(
gckHARDWARE_FlushMMU(Mmu->hardware));
previous = Mmu->heapList = ~0U;
Mmu->freeNodes = gcvFALSE;
/* Walk the entire page table. */
for (i = 0; i < Mmu->pageTableEntries; ++i)
{
/* Dispatch based on type of page. */
switch (pageTable[i] & 0xFF)
{
case gcvMMU_USED:
/* Used page, so close any open node. */
if (count > 0)
{
/* Add the node. */
gcmkONERROR(_AddFree(Mmu, previous, start, count));
/* Reset the node. */
previous = start;
count = 0;
}
break;
case gcvMMU_SINGLE:
/* Single free node. */
if (count++ == 0)
{
/* Start a new node. */
start = i;
}
break;
case gcvMMU_FREE:
/* A free node. */
if (count == 0)
{
/* Start a new node. */
start = i;
}
/* Advance the count. */
count += pageTable[i] >> 8;
/* Advance the index into the page table. */
i += (pageTable[i] >> 8) - 1;
break;
default:
gcmkFATAL("MMU page table correcupted at index %u!", i);
return gcvSTATUS_HEAP_CORRUPTED;
}
}
/* See if we have an open node left. */
if (count > 0)
{
/* Add the node to the list. */
gcmkONERROR(_AddFree(Mmu, previous, start, count));
}
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_MMU,
"Performed a garbage collection of the MMU heap.");
/* Success. */
return gcvSTATUS_OK;
OnError:
/* Return the staus. */
return status;
}
/*******************************************************************************
**
** gckMMU_Construct
**
** Construct a new gckMMU object.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctSIZE_T MmuSize
** Number of bytes for the page table.
**
** OUTPUT:
**
** gckMMU * Mmu
** Pointer to a variable that receives the gckMMU object pointer.
*/
gceSTATUS
gckMMU_Construct(
IN gckKERNEL Kernel,
IN gctSIZE_T MmuSize,
OUT gckMMU * Mmu
)
{
gckOS os;
gckHARDWARE hardware;
gceSTATUS status;
gckMMU mmu = gcvNULL;
gctUINT32_PTR pageTable;
gcmkHEADER_ARG("Kernel=0x%x MmuSize=%lu", Kernel, MmuSize);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(MmuSize > 0);
gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
/* Extract the gckOS object pointer. */
os = Kernel->os;
gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
/* Extract the gckHARDWARE object pointer. */
hardware = Kernel->hardware;
gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
/* Allocate memory for the gckMMU object. */
gcmkONERROR(
gckOS_Allocate(os, sizeof(struct _gckMMU), (gctPOINTER *) &mmu));
/* Initialize the gckMMU object. */
mmu->object.type = gcvOBJ_MMU;
mmu->os = os;
mmu->hardware = hardware;
mmu->pageTableMutex = gcvNULL;
mmu->pageTableLogical = gcvNULL;
#ifdef __QNXNTO__
mmu->nodeList = gcvNULL;
mmu->nodeMutex = gcvNULL;
#endif
/* Create the page table mutex. */
gcmkONERROR(gckOS_CreateMutex(os, &mmu->pageTableMutex));
#ifdef __QNXNTO__
/* Create the node list mutex. */
gcmkONERROR(gckOS_CreateMutex(os, &mmu->nodeMutex));
#endif
/* Allocate the page table (not more than 256 kB). */
mmu->pageTableSize = gcmMIN(MmuSize, 256 << 10);
gcmkONERROR(
gckOS_AllocateContiguous(os,
gcvFALSE,
&mmu->pageTableSize,
&mmu->pageTablePhysical,
(gctPOINTER *) &mmu->pageTableLogical));
/* Compute number of entries in page table. */
mmu->pageTableEntries = mmu->pageTableSize / sizeof(gctUINT32);
/* Mark all pages as free. */
pageTable = mmu->pageTableLogical;
pageTable[0] = (mmu->pageTableEntries << 8) | gcvMMU_FREE;
pageTable[1] = ~0U;
mmu->heapList = 0;
mmu->freeNodes = gcvFALSE;
/* Set page table address. */
gcmkONERROR(
gckHARDWARE_SetMMU(hardware, (gctPOINTER) mmu->pageTableLogical));
/* Return the gckMMU object pointer. */
*Mmu = mmu;
/* Success. */
gcmkFOOTER_ARG("*Mmu=0x%x", *Mmu);
return gcvSTATUS_OK;
OnError:
/* Roll back. */
if (mmu != gcvNULL)
{
if (mmu->pageTableLogical != gcvNULL)
{
/* Free the page table. */
gcmkVERIFY_OK(
gckOS_FreeContiguous(os,
mmu->pageTablePhysical,
(gctPOINTER) mmu->pageTableLogical,
mmu->pageTableSize));
}
if (mmu->pageTableMutex != gcvNULL)
{
/* Delete the mutex. */
gcmkVERIFY_OK(
gckOS_DeleteMutex(os, mmu->pageTableMutex));
}
#ifdef __QNXNTO__
if (mmu->nodeMutex != gcvNULL)
{
/* Delete the mutex. */
gcmkVERIFY_OK(
gckOS_DeleteMutex(os, mmu->nodeMutex));
}
#endif
/* Mark the gckMMU object as unknown. */
mmu->object.type = gcvOBJ_UNKNOWN;
/* Free the allocates memory. */
gcmkVERIFY_OK(gckOS_Free(os, mmu));
}
/* Return the status. */
gcmkFOOTER();
return status;
}
/*******************************************************************************
**
** gckMMU_Destroy
**
** Destroy a gckMMU object.
**
** INPUT:
**
** gckMMU Mmu
** Pointer to an gckMMU object.
**
** OUTPUT:
**
** Nothing.
*/
gceSTATUS
gckMMU_Destroy(
IN gckMMU Mmu
)
{
#ifdef __QNXNTO__
gcuVIDMEM_NODE_PTR node, next;
#endif
gcmkHEADER_ARG("Mmu=0x%x", Mmu);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
#ifdef __QNXNTO__
/* Free all associated virtual memory. */
for (node = Mmu->nodeList; node != gcvNULL; node = next)
{
next = node->Virtual.next;
gcmkVERIFY_OK(gckVIDMEM_Free(node, gcvNULL));
}
#endif
/* Free the page table. */
gcmkVERIFY_OK(
gckOS_FreeContiguous(Mmu->os,
Mmu->pageTablePhysical,
(gctPOINTER) Mmu->pageTableLogical,
Mmu->pageTableSize));
#ifdef __QNXNTO__
/* Delete the node list mutex. */
gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->nodeMutex));
#endif
/* Delete the page table mutex. */
gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->pageTableMutex));
/* Mark the gckMMU object as unknown. */
Mmu->object.type = gcvOBJ_UNKNOWN;
/* Free the gckMMU object. */
gcmkVERIFY_OK(gckOS_Free(Mmu->os, Mmu));
/* Success. */
gcmkFOOTER_NO();
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckMMU_AllocatePages
**
** Allocate pages inside the page table.
**
** INPUT:
**
** gckMMU Mmu
** Pointer to an gckMMU object.
**
** gctSIZE_T PageCount
** Number of pages to allocate.
**
** OUTPUT:
**
** gctPOINTER * PageTable
** Pointer to a variable that receives the base address of the page
** table.
**
** gctUINT32 * Address
** Pointer to a variable that receives the hardware specific address.
*/
gceSTATUS
gckMMU_AllocatePages(
IN gckMMU Mmu,
IN gctSIZE_T PageCount,
OUT gctPOINTER * PageTable,
OUT gctUINT32 * Address
)
{
gceSTATUS status;
gctBOOL mutex = gcvFALSE;
gctUINT32 index = 0, previous = ~0U, left;
gctUINT32_PTR pageTable;
gctBOOL gotIt;
gctUINT32 address;
gcmkHEADER_ARG("Mmu=0x%x PageCount=%lu", Mmu, PageCount);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
gcmkVERIFY_ARGUMENT(PageCount > 0);
gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
if (PageCount > Mmu->pageTableEntries)
{
/* Not enough pages avaiable. */
gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
}
/* Grab the mutex. */
gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
mutex = gcvTRUE;
/* Cast pointer to page table. */
for (pageTable = Mmu->pageTableLogical, gotIt = gcvFALSE; !gotIt;)
{
/* Walk the heap list. */
for (index = Mmu->heapList; !gotIt && (index < Mmu->pageTableEntries);)
{
/* Check the node type. */
switch (pageTable[index] & 0xFF)
{
case gcvMMU_SINGLE:
/* Single odes are valid if we only need 1 page. */
if (PageCount == 1)
{
gotIt = gcvTRUE;
}
else
{
/* Move to next node. */
previous = index;
index = pageTable[index] >> 8;
}
break;
case gcvMMU_FREE:
/* Test if the node has enough space. */
if (PageCount <= (pageTable[index] >> 8))
{
gotIt = gcvTRUE;
}
else
{
/* Move to next node. */
previous = index;
index = pageTable[index + 1];
}
break;
default:
gcmkFATAL("MMU table correcupted at index %u!", index);
gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
}
}
/* Test if we are out of memory. */
if (index >= Mmu->pageTableEntries)
{
if (Mmu->freeNodes)
{
/* Time to move out the trash! */
gcmkONERROR(_Collect(Mmu));
}
else
{
/* Out of resources. */
gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
}
}
}
switch (pageTable[index] & 0xFF)
{
case gcvMMU_SINGLE:
/* Unlink single node from free list. */
gcmkONERROR(
_Link(Mmu, previous, pageTable[index] >> 8));
break;
case gcvMMU_FREE:
/* Check how many pages will be left. */
left = (pageTable[index] >> 8) - PageCount;
switch (left)
{
case 0:
/* The entire node is consumed, just unlink it. */
gcmkONERROR(
_Link(Mmu, previous, pageTable[index + 1]));
break;
case 1:
/* One page will remain. Convert the node to a single node and
** advance the index. */
pageTable[index] = (pageTable[index + 1] << 8) | gcvMMU_SINGLE;
index ++;
break;
default:
/* Enough pages remain for a new node. However, we will just adjust
** the size of the current node and advance the index. */
pageTable[index] = (left << 8) | gcvMMU_FREE;
index += left;
break;
}
break;
}
/* Mark node as used. */
pageTable[index] = gcvMMU_USED;
/* Return pointer to page table. */
*PageTable = &pageTable[index];
/* Build virtual address. */
gcmkONERROR(
gckHARDWARE_BuildVirtualAddress(Mmu->hardware, index, 0, &address));
if (Address != gcvNULL)
{
*Address = address;
}
/* Release the mutex. */
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
/* Success. */
gcmkFOOTER_ARG("*PageTable=0x%x *Address=%08x",
*PageTable, gcmOPT_VALUE(Address));
return gcvSTATUS_OK;
OnError:
if (mutex)
{
/* Release the mutex. */
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
}
/* Return the status. */
gcmkFOOTER();
return status;
}
/*******************************************************************************
**
** gckMMU_FreePages
**
** Free pages inside the page table.
**
** INPUT:
**
** gckMMU Mmu
** Pointer to an gckMMU object.
**
** gctPOINTER PageTable
** Base address of the page table to free.
**
** gctSIZE_T PageCount
** Number of pages to free.
**
** OUTPUT:
**
** Nothing.
*/
gceSTATUS
gckMMU_FreePages(
IN gckMMU Mmu,
IN gctPOINTER PageTable,
IN gctSIZE_T PageCount
)
{
gctUINT32_PTR pageTable;
gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=%lu",
Mmu, PageTable, PageCount);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
gcmkVERIFY_ARGUMENT(PageCount > 0);
/* Convert the pointer. */
pageTable = (gctUINT32_PTR) PageTable;
if (PageCount == 1)
{
/* Single page node. */
pageTable[0] = (~0U << 8) | gcvMMU_SINGLE;
}
else
{
/* Mark the node as free. */
pageTable[0] = (PageCount << 8) | gcvMMU_FREE;
pageTable[1] = ~0U;
}
/* We have free nodes. */
Mmu->freeNodes = gcvTRUE;
/* Success. */
gcmkFOOTER_NO();
return gcvSTATUS_OK;
}
#ifdef __QNXNTO__
gceSTATUS
gckMMU_InsertNode(
IN gckMMU Mmu,
IN gcuVIDMEM_NODE_PTR Node)
{
gceSTATUS status;
gctBOOL mutex = gcvFALSE;
gcmkHEADER_ARG("Mmu=0x%x Node=0x%x", Mmu, Node);
gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
mutex = gcvTRUE;
Node->Virtual.next = Mmu->nodeList;
Mmu->nodeList = Node;
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
gcmkFOOTER();
return gcvSTATUS_OK;
OnError:
if (mutex)
{
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
}
gcmkFOOTER();
return status;
}
gceSTATUS
gckMMU_RemoveNode(
IN gckMMU Mmu,
IN gcuVIDMEM_NODE_PTR Node)
{
gceSTATUS status;
gctBOOL mutex = gcvFALSE;
gcuVIDMEM_NODE_PTR *iter;
gcmkHEADER_ARG("Mmu=0x%x Node=0x%x", Mmu, Node);
gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
mutex = gcvTRUE;
for (iter = &Mmu->nodeList; *iter; iter = &(*iter)->Virtual.next)
{
if (*iter == Node)
{
*iter = Node->Virtual.next;
break;
}
}
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
gcmkFOOTER();
return gcvSTATUS_OK;
OnError:
if (mutex)
{
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
}
gcmkFOOTER();
return status;
}
gceSTATUS
gckMMU_FreeHandleMemory(
IN gckMMU Mmu,
IN gctHANDLE Handle
)
{
gceSTATUS status;
gctBOOL acquired = gcvFALSE;
gcuVIDMEM_NODE_PTR curr, next;
gcmkHEADER_ARG("Mmu=0x%x Handle=0x%x", Mmu, Handle);
gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
acquired = gcvTRUE;
for (curr = Mmu->nodeList; curr != gcvNULL; curr = next)
{
next = curr->Virtual.next;
if (curr->Virtual.handle == Handle)
{
while (curr->Virtual.locked > 0 || curr->Virtual.unlockPending)
{
gcmkONERROR(gckVIDMEM_Unlock(curr, gcvSURF_TYPE_UNKNOWN, gcvNULL, gcvNULL));
}
gcmkVERIFY_OK(gckVIDMEM_Free(curr, gcvNULL));
}
}
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
gcmkFOOTER();
return gcvSTATUS_OK;
OnError:
if (acquired)
{
gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
}
gcmkFOOTER();
return status;
}
#endif
/******************************************************************************
****************************** T E S T C O D E ******************************
******************************************************************************/
#if defined gcdHAL_TEST
#include <stdlib.h>
#define gcmRANDOM(n) (rand() % n)
typedef struct
{
gctSIZE_T pageCount;
gctUINT32_PTR pageTable;
}
gcsMMU_TEST;
gceSTATUS
gckMMU_Test(
IN gckMMU Mmu,
IN gctSIZE_T Vectors,
IN gctINT MaxSize
)
{
const gctINT nodeCount = MaxSize / 4;
gcsMMU_TEST * nodes = gcvNULL;
gceSTATUS status, failure = gcvSTATUS_OK;
gctSIZE_T i, count;
gctUINT32_PTR pageTable;
gctINT index;
/* Allocate the node array. */
gcmkONERROR(
gckOS_Allocate(Mmu->os,
nodeCount * gcmSIZEOF(gcsMMU_TEST),
(gctPOINTER *) &nodes));
/* Mark all nodes as free. */
gcmkONERROR(
gckOS_ZeroMemory(nodes, nodeCount * gcmSIZEOF(gcsMMU_TEST)));
/* Loop through all vectors. */
while (Vectors-- > 0)
{
/* Get a random index. */
index = gcmRANDOM(nodeCount);
/* Test if we need to allocate pages. */
if (nodes[index].pageCount == 0)
{
/* Generate a random page count. */
do
{
count = gcmRANDOM(MaxSize);
}
while (count == 0);
/* Allocate pages. */
status = gckMMU_AllocatePages(Mmu,
count,
(gctPOINTER *) &pageTable,
gcvNULL);
if (gcmIS_SUCCESS(status))
{
/* Mark node as allocated. */
nodes[index].pageCount = count;
nodes[index].pageTable = pageTable;
/* Put signature in the page table. */
for (i = 0; i < count; ++i)
{
pageTable[i] = (index << 8) | gcvMMU_USED;
}
}
else
{
gcmkTRACE(gcvLEVEL_WARNING,
"gckMMU_Test: Failed to allocate %u pages",
count);
}
}
else
{
/* Verify the page table. */
pageTable = nodes[index].pageTable;
for (i = 0; i < nodes[index].pageCount; ++i)
{
if (pageTable[i] != ((index << 8) | gcvMMU_USED))
{
gcmkFATAL("gckMMU_Test: Corruption detected at page %u",
index);
failure = gcvSTATUS_HEAP_CORRUPTED;
}
}
/* Free the pages. */
status = gckMMU_FreePages(Mmu, pageTable, nodes[index].pageCount);
if (gcmIS_ERROR(status))
{
gcmkFATAL("gckMMU_Test: Cannot free %u pages at 0x%x (index=%u)",
nodes[index].pageCount, pageTable, index);
failure = status;
}
/* Mark the node as free. */
nodes[index].pageCount = 0;
}
}
/* Walk the entire array of nodes. */
for (index = 0; index < nodeCount; ++index)
{
/* Test if we need to free pages. */
if (nodes[index].pageCount != 0)
{
/* Verify the page table. */
pageTable = nodes[index].pageTable;
for (i = 0; i < nodes[index].pageCount; ++i)
{
if (pageTable[i] != ((index << 8) | gcvMMU_USED))
{
gcmkFATAL("gckMMU_Test: Corruption detected at page %u",
index);
failure = gcvSTATUS_HEAP_CORRUPTED;
}
}
/* Free the pages. */
status = gckMMU_FreePages(Mmu, pageTable, nodes[index].pageCount);
if (gcmIS_ERROR(status))
{
gcmkFATAL("gckMMU_Test: Cannot free %u pages at 0x%x (index=%u)",
nodes[index].pageCount, pageTable, index);
failure = status;
}
}
}
/* Perform garbage collection. */
gcmkONERROR(_Collect(Mmu));
/* Verify we did not loose any nodes. */
if ((Mmu->heapList != 0)
|| ((Mmu->pageTableLogical[0] & 0xFF) != gcvMMU_FREE)
|| (Mmu->pageTableEntries != (Mmu->pageTableLogical[0] >> 8))
)
{
gcmkFATAL("gckMMU_Test: Detected leaking in the page table.");
failure = gcvSTATUS_HEAP_CORRUPTED;
}
OnError:
/* Free the array of nodes. */
if (nodes != gcvNULL)
{
gcmkVERIFY_OK(gckOS_Free(Mmu->os, nodes));
}
/* Return test status. */
return failure;
}
#endif

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drivers/staging/rk29/vivante/hal/kernel/gc_hal_kernel_precomp.h Normal file
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/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_kernel_precomp_h_
#define __gc_hal_kernel_precomp_h_
#include "gc_hal.h"
#include "gc_hal_driver.h"
#include "gc_hal_kernel.h"
#endif /* __gc_hal_kernel_precomp_h_ */

1754
drivers/staging/rk29/vivante/hal/kernel/gc_hal_kernel_video_memory.c Normal file
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File diff suppressed because it is too large Load Diff

59
drivers/staging/rk29/vivante/hal/kernel/makefile.linux Normal file
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@ -0,0 +1,59 @@
##############################################################################
#
# Copyright (C) 2005 - 2010 by Vivante Corp.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the license, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
##############################################################################
#
# Linux build file for architecture dependent kernel HAL layer.
#
#
################################################################################
# Include common definitions.
include $(AQROOT)/makefile.linux.def
################################################################################
# Define a shortcut for the main target.
STATIC = 1
TARGET_NAME = libhalkernel.a
################################################################################
# Supply additional include directories.
INCLUDE += -I$(AQROOT)/hal/inc
INCLUDE += -I$(AQROOT)/hal/user
INCLUDE += -I$(AQARCH)/hal/kernel
CFLAGS += $(INCLUDE) -Werror -ansi
################################################################################
# Describe object files.
OBJECTS = $(OBJ_DIR)/gc_hal_kernel_command.o \
$(OBJ_DIR)/gc_hal_kernel_event.o \
$(OBJ_DIR)/gc_hal_kernel_heap.o \
$(OBJ_DIR)/gc_hal_kernel.o \
$(OBJ_DIR)/gc_hal_kernel_mmu.o \
$(OBJ_DIR)/gc_hal_kernel_video_memory.o
include $(AQROOT)/common.target

47
drivers/staging/rk29/vivante/hal/makefile.linux Normal file
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@ -0,0 +1,47 @@
##############################################################################
#
# Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
#
# The material in this file is confidential and contains trade secrets
# of Vivante Corporation. This is proprietary information owned by
# Vivante Corporation. No part of this work may be disclosed,
# reproduced, copied, transmitted, or used in any way for any purpose,
# without the express written permission of Vivante Corporation.
#
##############################################################################
#
# Auto-generated file on 10/12/2010. Do not edit!!!
#
##############################################################################
#
# Linux build file for the user level HAL libraries.
#
################################################################################
# Define make command.
MAKE = make --makefile=makefile.linux
################################################################################
# Define build directories.
HAL_USER_DRV_ARCH := $(AQARCH)/hal/user
ifeq ($(QNX), 1)
HAL_USER_DRV_OS := $(AQROOT)/hal/os/qnx/user
else
HAL_USER_DRV_OS := $(AQROOT)/hal/os/linux/user
endif
HAL_USER_DRV_MAIN := $(AQROOT)/hal/user
$(HAL_USER_DRV_MAIN): $(HAL_USER_DRV_ARCH) $(HAL_USER_DRV_OS)
MODULES := $(HAL_USER_DRV_ARCH) $(HAL_USER_DRV_OS) $(HAL_USER_DRV_MAIN)
MAIN_MODULE = $(HAL_USER_DRV_MAIN)
include $(AQROOT)/common.node

540
drivers/staging/rk29/vivante/hal/os/libGAL.def.mak Normal file
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@ -0,0 +1,540 @@
##############################################################################
#
# Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
#
# The material in this file is confidential and contains trade secrets
# of Vivante Corporation. This is proprietary information owned by
# Vivante Corporation. No part of this work may be disclosed,
# reproduced, copied, transmitted, or used in any way for any purpose,
# without the express written permission of Vivante Corporation.
#
##############################################################################
#
# Auto-generated file on 10/12/2010. Do not edit!!!
#
##############################################################################
"$(DEFFILE)" : $(AQROOT)\hal\os\libGAL.def.mak
@copy << "$(DEFFILE)"
;
; !! Do not edit this file - it is automatically generated !!
;
LIBRARY libGAL
EXPORTS
;gcoOS
gcoOS_SetDebugLevel
gcoOS_SetDebugZone
gcoOS_SetDebugFile
gcoOS_SetDebugZones
gcoOS_SetDebugLevelZone
gcoOS_SetDebugShaderFiles
gcoOS_DebugFatal
gcoOS_DebugTrace
gcoOS_DebugTraceZone
gcoOS_Print
gcoOS_DebugBreak
gcoOS_Verify
gcoOS_Construct
gcoOS_Destroy
gcoOS_QueryVideoMemory
gcoOS_Allocate
gcoOS_Free
gcoOS_AllocateNonPagedMemory
gcoOS_FreeNonPagedMemory
gcoOS_AllocateContiguous
gcoOS_FreeContiguous
gcoOS_CreateMutex
gcoOS_DeleteMutex
gcoOS_AcquireMutex
gcoOS_ReleaseMutex
gcoOS_CreateSignal
gcoOS_DestroySignal
gcoOS_Signal
gcoOS_WaitSignal
gcoOS_DeviceControl
gcoOS_Open
gcoOS_Close
gcoOS_Read
gcoOS_Write
gcoOS_Seek
gcoOS_SetPos
gcoOS_GetPos
gcoOS_MemCopy
gcoOS_ZeroMemory
gcoOS_MemFill
gcoOS_StrLen
gcoOS_StrFindReverse
gcoOS_StrCopySafe
gcoOS_StrCatSafe
gcoOS_StrCmp
gcoOS_StrNCmp
gcoOS_StrToFloat
gcoOS_StrToInt
gcoOS_MemCmp
gcoOS_PrintStrSafe
gcoOS_PrintStrVSafe
gcoOS_MapUserMemory
gcoOS_UnmapUserMemory
gcoOS_StrDup
gcoOS_LoadLibrary
gcoOS_FreeLibrary
gcoOS_GetProcAddress
gcoOS_Delay
gcoOS_GetCurrentProcessID
gcoOS_AtomConstruct
gcoOS_AtomDestroy
gcoOS_AtomIncrement
gcoOS_AtomDecrement
gcoOS_GetTicks
gcoOS_GetTime
gcoOS_GetCPUTime
gcoOS_GetMemoryUsage
gcoOS_GetBaseAddress
gcoOS_ReadRegister
gcoOS_WriteRegister
!IFNDEF VIVANTE_NO_3D
; gcsMEM
gcfMEM_InitFSMemPool
gcfMEM_FreeFSMemPool
gcfMEM_FSMemPoolGetANode
gcfMEM_FSMemPoolFreeANode
gcfMEM_FSMemPoolFreeAList
gcfMEM_InitAFSMemPool
gcfMEM_FreeAFSMemPool
gcfMEM_AFSMemPoolGetANode
gcfMEM_AFSMemPoolFreeANode
!ENDIF
; gcoHAL
gcoHAL_Construct
gcoHAL_Destroy
gcoHAL_IsFeatureAvailable
gcoHAL_QueryChipIdentity
gcoHAL_Call
gcoHAL_QueryVideoMemory
gcoHAL_MapMemory
gcoHAL_UnmapMemory
gcoHAL_ScheduleUnmapMemory
gcoHAL_ScheduleUnmapUserMemory
gcoHAL_Commit
gcoHAL_QueryTiled
gcoHAL_Get2DEngine
gcoHAL_Get3DEngine
gcoHAL_GetVGEngine
gcoHAL_GetDump
gcoHAL_ScheduleEvent
!IFNDEF VIVANTE_NO_3D
gcoHAL_QueryTargetCaps
gcoHAL_SetDepthOnly
gcoHAL_QueryShaderCaps
gcoHAL_QueryTextureCaps
gcoHAL_QueryStreamCaps
!ENDIF
gcoHAL_ProfileStart
gcoHAL_ProfileEnd
gcoHAL_Compact
gcoHAL_SetPowerManagementState
gcoHAL_QueryPowerManagementState
gcoHAL_DestroySurface
; gcoDUMP
gcoDUMP_Construct
gcoDUMP_Destroy
gcoDUMP_Control
gcoDUMP_IsEnabled
gcoDUMP_AddSurface
gcoDUMP_FrameBegin
gcoDUMP_FrameEnd
gcoDUMP_DumpData
gcoDUMP_Delete
gcfDump
; gcoSURF
gcoSURF_Construct
gcoSURF_Destroy
gcoSURF_MapUserSurface
gcoSURF_GetSize
gcoSURF_GetAlignedSize
gcoSURF_GetFormat
gcoSURF_Lock
gcoSURF_Unlock
gcoSURF_Fill
gcoSURF_Blend
gcoSURF_SetClipping
gcoSURF_Clear2D
gcoSURF_Line
gcoSURF_Blit
gcoSURF_MonoBlit
gcoSURF_FilterBlit
gcoSURF_EnableAlphaBlend
gcoSURF_DisableAlphaBlend
gcoSURF_CopyPixels
gcoSURF_ReadPixel
gcoSURF_WritePixel
gcoSURF_QueryFormat
gcoSURF_Flush
gcoSURF_SetColorType
gcoSURF_GetColorType
gcoSURF_SetRotation
gcoSURF_ConstructWrapper
gcoSURF_SetBuffer
gcoSURF_SetWindow
gcoSURF_ReferenceSurface
gcoSURF_SetOrientation
gcoSURF_QueryOrientation
gcoSURF_QueryReferenceCount
!IFNDEF VIVANTE_NO_3D
gcoSURF_IsTileStatusSupported
gcoSURF_EnableTileStatus
gcoSURF_DisableTileStatus
gcoSURF_SetSamples
gcoSURF_GetSamples
gcoSURF_Copy
gcoSURF_Clear
gcoSURF_ClearRect
gcoSURF_Resample
gcoSURF_Resolve
gcoSURF_ResolveRect
depr_gcoSURF_Resolve
depr_gcoSURF_ResolveRect
gcoSURF_SetResolvability
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcoINDEX
gcoINDEX_Construct
gcoINDEX_Destroy
gcoINDEX_Lock
gcoINDEX_Unlock
gcoINDEX_Load
gcoINDEX_Bind
gcoINDEX_BindOffset
gcoINDEX_Free
gcoINDEX_Upload
gcoINDEX_UploadOffset
gcoINDEX_QueryCaps
gcoINDEX_GetIndexRange
gcoINDEX_SetDynamic
gcoINDEX_UploadDynamic
!ENDIF
; gco2D
gco2D_Construct
gco2D_Destroy
gco2D_SetBrushLimit
gco2D_FlushBrush
gco2D_LoadSolidBrush
gco2D_SetMonochromeSource
gco2D_SetColorSource
gco2D_SetColorSourceEx
gco2D_SetColorSourceAdvanced
gco2D_SetMaskedSource
gco2D_SetMaskedSourceEx
gco2D_SetSource
gco2D_SetClipping
gco2D_SetTarget
gco2D_SetTargetEx
gco2D_SetStretchFactors
gco2D_SetStretchRectFactors
gco2D_ConstructSingleColorBrush
gco2D_ConstructMonochromeBrush
gco2D_ConstructColorBrush
gco2D_Clear
gco2D_Line
gco2D_ColorLine
gco2D_Blit
gco2D_BatchBlit
gco2D_StretchBlit
gco2D_MonoBlit
gco2D_SetKernelSize
gco2D_SetFilterType
gco2D_SetUserFilterKernel
gco2D_EnableUserFilterPasses
gco2D_FreeFilterBuffer
gco2D_FilterBlit
gco2D_FilterBlitEx
gco2D_EnableAlphaBlend
gco2D_EnableAlphaBlendAdvanced
gco2D_SetPorterDuffBlending
gco2D_DisableAlphaBlend
gco2D_GetPackSize
gco2D_Flush
gco2D_LoadPalette
gco2D_SetBitBlitMirror
gco2D_SetTransparencyAdvanced
gco2D_SetSourceColorKeyAdvanced
gco2D_SetSourceColorKeyRangeAdvanced
gco2D_SetTargetColorKeyAdvanced
gco2D_SetTargetColorKeyRangeAdvanced
gco2D_SetYUVColorMode
gco2D_SetSourceGlobalColorAdvanced
gco2D_SetTargetGlobalColorAdvanced
gco2D_SetPixelMultiplyModeAdvanced
gco2D_SetAutoFlushCycles
gco2D_ProfileEngine
gco2D_GetMaximumDataCount
!IFNDEF VIVANTE_NO_3D
gco3D_Construct
gco3D_Destroy
gco3D_SetAPI
gco3D_SetTarget
gco3D_SetDepth
gco3D_SetViewport
gco3D_SetScissors
gco3D_SetClearColor
gco3D_SetClearColorX
gco3D_SetClearColorF
gco3D_SetClearDepthX
gco3D_SetClearDepthF
gco3D_SetClearStencil
gco3D_Clear
gco3D_ClearRect
gco3D_ClearTileStatus
gco3D_ClearHzTileStatus
gco3D_SetShading
gco3D_EnableBlending
gco3D_SetBlendFunction
gco3D_SetBlendMode
gco3D_SetBlendColor
gco3D_SetBlendColorX
gco3D_SetBlendColorF
gco3D_SetCulling
gco3D_SetPointSizeEnable
gco3D_SetPointSprite
gco3D_SetFill
gco3D_SetDepthCompare
gco3D_EnableDepthWrite
gco3D_SetDepthRangeX
gco3D_SetDepthMode
gco3D_SetDepthRangeF
gco3D_SetLastPixelEnable
gco3D_SetDepthScaleBiasX
gco3D_SetDepthScaleBiasF
gco3D_EnableDither
gco3D_SetColorWrite
gco3D_SetEarlyDepth
gco3D_SetDepthOnly
gco3D_SetStencilMode
gco3D_SetStencilMask
gco3D_SetStencilWriteMask
gco3D_SetStencilReference
gco3D_SetStencilCompare
gco3D_SetStencilPass
gco3D_SetStencilFail
gco3D_SetStencilDepthFail
gco3D_SetAlphaTest
gco3D_SetAlphaCompare
gco3D_SetAlphaReference
gco3D_SetAlphaReferenceX
gco3D_SetAlphaReferenceF
gco3D_SetAntiAliasLine
gco3D_SetAALineTexSlot
gco3D_SetAALineWidth
gco3D_DrawPrimitives
gco3D_DrawPrimitivesOffset
gco3D_DrawIndexedPrimitives
gco3D_DrawIndexedPrimitivesOffset
gco3D_SetAntiAlias
gco3D_WriteBuffer
gco3D_SetFragmentConfiguration
gco3D_EnableTextureStage
gco3D_SetTextureColorMask
gco3D_SetTextureAlphaMask
gco3D_SetFragmentColorX
gco3D_SetFragmentColorF
gco3D_SetFogColorX
gco3D_SetFogColorF
gco3D_SetTetxureColorX
gco3D_SetTetxureColorF
gco3D_SetColorTextureFunction
gco3D_SetAlphaTextureFunction
gco3D_Semaphore
gco3D_SetCentroids
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcoTEXTURE
gcoTEXTURE_Construct
gcoTEXTURE_ConstructSized
gcoTEXTURE_Destroy
gcoTEXTURE_Upload
gcoTEXTURE_UploadSub
gcoTEXTURE_UploadCompressed
gcoTEXTURE_GetMipMap
gcoTEXTURE_GetMipMapFace
gcoTEXTURE_AddMipMap
gcoTEXTURE_AddMipMapFromClient
gcoTEXTURE_AddMipMapFromSurface
gcoTEXTURE_SetEndianHint
gcoTEXTURE_SetAddressingMode
gcoTEXTURE_SetBorderColor
gcoTEXTURE_SetBorderColorX
gcoTEXTURE_SetBorderColorF
gcoTEXTURE_SetMinFilter
gcoTEXTURE_SetMagFilter
gcoTEXTURE_SetMipFilter
gcoTEXTURE_SetLODBiasX
gcoTEXTURE_SetLODBiasF
gcoTEXTURE_SetLODMinX
gcoTEXTURE_SetLODMinF
gcoTEXTURE_SetLODMaxX
gcoTEXTURE_SetLODMaxF
gcoTEXTURE_Bind
gcoTEXTURE_Flush
gcoTEXTURE_QueryCaps
gcoTEXTURE_GetClosestFormat
gcoTEXTURE_Disable
gcoTEXTURE_RenderIntoMipMap
gcoTEXTURE_IsRenderable
gcoTEXTURE_IsComplete
!ENDIF
; gcsRECT
gcsRECT_Height
gcsRECT_Width
gcsRECT_Set
!IFNDEF VIVANTE_NO_3D
; gcoHARDWARE
gcoHARDWARE_QueryTextureCaps
gcoHARDWARE_QueryShaderCaps
gcoHARDWARE_QueryIndexCaps
gcoHARDWARE_QueryStreamCaps
!ENDIF
; gcoBRUSH
gcoBRUSH_Destroy
!IFNDEF VIVANTE_NO_3D
; gcSHADER
gcOptimizeShader
gcLinkShaders
gcLoadShaders
gcSaveProgram
gcSHADER_Construct
gcSHADER_Destroy
gcSHADER_AddUniform
gcSHADER_AddSource
gcSHADER_AddSourceAttributeIndexed
gcSHADER_AddSourceUniformIndexed
gcSHADER_AddSourceSamplerIndexed
gcSHADER_AddOpcodeIndexed
gcSHADER_AddSourceIndexed
gcSHADER_AddAttribute
gcSHADER_AddOutput
gcSHADER_AddOutputIndexed
gcSHADER_AddSourceAttribute
gcSHADER_AddSourceConstant
gcSHADER_AddSourceUniform
gcSHADER_AddLabel
gcSHADER_AddOpcode
gcSHADER_AddOpcode2
gcSHADER_AddOpcodeConditional
gcSHADER_AddVariable
gcSHADER_Pack
gcSHADER_Load
gcSHADER_Save
gcSHADER_GetUniform
gcSHADER_GetUniformCount
gcSHADER_GetAttribute
gcSHADER_GetAttributeCount
gcSHADER_GetPositionAttribute
gcSHADER_GetVariable
gcSHADER_GetVariableCount
gcSHADER_AddFunction
gcSHADER_BeginFunction
gcSHADER_EndFunction
gcSHADER_SetOptimizationOption
gcSHADER_GetPositionAttribute
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcATTRIBUTE
gcATTRIBUTE_GetName
gcATTRIBUTE_GetType
gcATTRIBUTE_IsEnabled
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcFUNCTION
gcFUNCTION_AddArgument
gcFUNCTION_GetArgument
gcFUNCTION_GetLabel
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcUNIFORM
gcUNIFORM_GetName
gcUNIFORM_GetType
gcUNIFORM_GetSampler
gcUNIFORM_SetValue
gcUNIFORM_SetValueX
gcUNIFORM_SetValueF
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcoSTREAM
gcoSTREAM_Construct
gcoSTREAM_Destroy
gcoSTREAM_Upload
gcoSTREAM_SetStride
gcoSTREAM_Lock
gcoSTREAM_Unlock
gcoSTREAM_Reserve
gcoSTREAM_Flush
gcoSTREAM_SetDynamic
gcoSTREAM_UploadDynamic
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcoVERTEX
gcoVERTEX_Construct
gcoVERTEX_Destroy
gcoVERTEX_Reset
gcoVERTEX_EnableAttribute
gcoVERTEX_DisableAttribute
gcoVERTEX_Bind
!ENDIF
!IFNDEF VIVANTE_NO_3D
; gcoBUFFER
gcoBUFFER_Construct
gcoBUFFER_Destroy
gcoBUFFER_Reserve
gcoBUFFER_Write
gcoBUFFER_Commit
!ENDIF
!IFNDEF VIVANTE_NO_PROFILER
; gcoPROFILER
;gcoPROFILER_Initialize
;gcoPROFILER_Destroy
;gcoPROFILER_EndFrame
;gcoPROFILER_ShaderFS
;gcoPROFILER_ShaderVS
!ENDIF
; gcoMATH
gcoMATH_Log2in5dot5
gcoMATH_Sine
gcoMATH_Cosine
gcoMATH_Floor
gcoMATH_Ceiling
gcoMATH_SquareRoot
gcoMATH_Log2
gcoMATH_Power
gcoMATH_Modulo
gcoMATH_ArcCosine
gcoMATH_Absolute
gcoMATH_Exp
gcoMATH_UInt2Float
gcoMATH_Float2UInt
gcoMATH_Multiply
<<

449
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_debug.c Normal file
View File

@ -0,0 +1,449 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#include "gc_hal_kernel_linux.h"
#include "linux/spinlock.h"
#include <stdarg.h>
/*
gcdBUFFERED_OUTPUT
When set to non-zero, all output is collected into a buffer with the
specified size. Once the buffer gets full, or the token "$$FLUSH$$" has
been received, the debug buffer will be printed to the console.
*/
#define gcdBUFFERED_OUTPUT 0
/******************************************************************************\
******************************** Debug Variables *******************************
\******************************************************************************/
static gceSTATUS _lastError = gcvSTATUS_OK;
static gctUINT32 _debugLevel = gcvLEVEL_WARNING;
static gctUINT32 _debugZones = gcvZONE_ALL;
static gctINT _indent = 0;
static spinlock_t _lock = SPIN_LOCK_UNLOCKED;
static void
OutputDebugString(
IN gctCONST_STRING String
)
{
#if gcdBUFFERED_OUTPUT
static gctCHAR outputBuffer[gcdBUFFERED_OUTPUT];
static gctINT outputBufferIndex = 0;
gctINT n, i;
n = (String != gcvNULL) ? strlen(String) + 1 : 0;
if ((n == 0) || (outputBufferIndex + n > gcmSIZEOF(outputBuffer)))
{
for (i = 0; i < outputBufferIndex; i += strlen(outputBuffer + i) + 1)
{
printk(outputBuffer + i);
}
outputBufferIndex = 0;
}
if (n > 0)
{
memcpy(outputBuffer + outputBufferIndex, String, n);
outputBufferIndex += n;
}
#else
if (String != gcvNULL)
{
printk(String);
}
#endif
}
static void
_Print(
IN gctCONST_STRING Message,
IN va_list Arguments
)
{
char buffer[1024];
int i, n;
if (strcmp(Message, "$$FLUSH$$") == 0)
{
spin_lock(&_lock);
{
OutputDebugString(gcvNULL);
}
spin_unlock(&_lock);
return;
}
if (strncmp(Message, "--", 2) == 0)
{
if (_indent == 0)
{
printk("ERROR: _indent=0\n");
}
_indent -= 2;
}
for (i = 0; i < _indent; ++i)
{
buffer[i] = ' ';
}
/* Print message to buffer. */
n = vsnprintf(buffer + i, sizeof(buffer) - i, Message, Arguments);
if ((n <= 0) || (buffer[i + n - 1] != '\n'))
{
/* Append new-line. */
strncat(buffer, "\n", sizeof(buffer));
}
/* Output to debugger. */
spin_lock(&_lock);
{
OutputDebugString(buffer);
}
spin_unlock(&_lock);
if (strncmp(Message, "++", 2) == 0)
{
_indent += 2;
}
}
/******************************************************************************\
********************************* Debug Macros *********************************
\******************************************************************************/
#define _DEBUGPRINT(Message) \
{ \
va_list arguments; \
\
va_start(arguments, Message); \
_Print(Message, arguments); \
va_end(arguments); \
}
/******************************************************************************\
********************************** Debug Code **********************************
\******************************************************************************/
/*******************************************************************************
**
** gckOS_Print
**
** Send a message to the debugger.
**
** INPUT:
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_Print(
IN gctCONST_STRING Message,
...
)
{
_DEBUGPRINT(Message);
}
/*******************************************************************************
**
** gckOS_DebugTrace
**
** Send a leveled message to the debugger.
**
** INPUT:
**
** gctUINT32 Level
** Debug level of message.
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugTrace(
IN gctUINT32 Level,
IN gctCONST_STRING Message,
...
)
{
if (Level > _debugLevel)
{
return;
}
_DEBUGPRINT(Message);
}
/*******************************************************************************
**
** gckOS_DebugTraceZone
**
** Send a leveled and zoned message to the debugger.
**
** INPUT:
**
** gctUINT32 Level
** Debug level for message.
**
** gctUINT32 Zone
** Debug zone for message.
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugTraceZone(
IN gctUINT32 Level,
IN gctUINT32 Zone,
IN gctCONST_STRING Message,
...
)
{
if ((Level > _debugLevel) || !(Zone & _debugZones))
{
return;
}
_DEBUGPRINT(Message);
}
/*******************************************************************************
**
** gckOS_DebugBreak
**
** Break into the debugger.
**
** INPUT:
**
** Nothing.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugBreak(
void
)
{
gckOS_DebugTrace(gcvLEVEL_ERROR, "gckOS_DebugBreak");
}
/*******************************************************************************
**
** gckOS_DebugFatal
**
** Send a message to the debugger and break into the debugger.
**
** INPUT:
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugFatal(
IN gctCONST_STRING Message,
...
)
{
_DEBUGPRINT(Message);
/* Break into the debugger. */
gckOS_DebugBreak();
}
/*******************************************************************************
**
** gckOS_SetDebugLevel
**
** Set the debug level.
**
** INPUT:
**
** gctUINT32 Level
** New debug level.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugLevel(
IN gctUINT32 Level
)
{
_debugLevel = Level;
}
/*******************************************************************************
**
** gckOS_SetDebugZone
**
** Set the debug zone.
**
** INPUT:
**
** gctUINT32 Zone
** New debug zone.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugZone(
IN gctUINT32 Zone
)
{
_debugZones = Zone;
}
/*******************************************************************************
**
** gckOS_SetDebugLevelZone
**
** Set the debug level and zone.
**
** INPUT:
**
** gctUINT32 Level
** New debug level.
**
** gctUINT32 Zone
** New debug zone.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugLevelZone(
IN gctUINT32 Level,
IN gctUINT32 Zone
)
{
_debugLevel = Level;
_debugZones = Zone;
}
/*******************************************************************************
**
** gckOS_SetDebugZones
**
** Enable or disable debug zones.
**
** INPUT:
**
** gctUINT32 Zones
** Debug zones to enable or disable.
**
** gctBOOL Enable
** Set to gcvTRUE to enable the zones (or the Zones with the current
** zones) or gcvFALSE to disable the specified Zones.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugZones(
IN gctUINT32 Zones,
IN gctBOOL Enable
)
{
if (Enable)
{
/* Enable the zones. */
_debugZones |= Zones;
}
else
{
/* Disable the zones. */
_debugZones &= ~Zones;
}
}
/*******************************************************************************
**
** gckOS_Verify
**
** Called to verify the result of a function call.
**
** INPUT:
**
** gceSTATUS Status
** Function call result.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_Verify(
IN gceSTATUS Status
)
{
_lastError = Status;
}

836
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_device.c Normal file
View File

@ -0,0 +1,836 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#include "gc_hal_kernel_linux.h"
#include <linux/pagemap.h>
#include <linux/seq_file.h>
#include <linux/mm.h>
#include <linux/mman.h>
#define _GC_OBJ_ZONE gcvZONE_DEVICE
#ifdef FLAREON
static struct dove_gpio_irq_handler gc500_handle;
#endif
/******************************************************************************\
******************************** gckGALDEVICE Code *******************************
\******************************************************************************/
gceSTATUS
gckGALDEVICE_AllocateMemory(
IN gckGALDEVICE Device,
IN gctSIZE_T Bytes,
OUT gctPOINTER *Logical,
OUT gctPHYS_ADDR *Physical,
OUT gctUINT32 *PhysAddr
)
{
gceSTATUS status;
gcmkVERIFY_ARGUMENT(Device != NULL);
gcmkVERIFY_ARGUMENT(Logical != NULL);
gcmkVERIFY_ARGUMENT(Physical != NULL);
gcmkVERIFY_ARGUMENT(PhysAddr != NULL);
status = gckOS_AllocateContiguous(Device->os,
gcvFALSE,
&Bytes,
Physical,
Logical);
if (gcmIS_ERROR(status))
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"gckGALDEVICE_AllocateMemory: error status->0x%x",
status);
return status;
}
*PhysAddr = ((PLINUX_MDL)*Physical)->dmaHandle - Device->baseAddress;
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"gckGALDEVICE_AllocateMemory: phys_addr->0x%x phsical->0x%x Logical->0x%x",
(gctUINT32)*Physical,
(gctUINT32)*PhysAddr,
(gctUINT32)*Logical);
/* Success. */
return gcvSTATUS_OK;
}
gceSTATUS
gckGALDEVICE_FreeMemory(
IN gckGALDEVICE Device,
IN gctPOINTER Logical,
IN gctPHYS_ADDR Physical)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
return gckOS_FreeContiguous(Device->os,
Physical,
Logical,
((PLINUX_MDL)Physical)->numPages*PAGE_SIZE);
}
irqreturn_t isrRoutine(int irq, void *ctxt)
{
gckGALDEVICE device = (gckGALDEVICE) ctxt;
int handled = 0;
/* Call kernel interrupt notification. */
if (gckKERNEL_Notify(device->kernel,
gcvNOTIFY_INTERRUPT,
gcvTRUE) == gcvSTATUS_OK)
{
device->dataReady = gcvTRUE;
up(&device->sema);
handled = 1;
}
return IRQ_RETVAL(handled);
}
int threadRoutine(void *ctxt)
{
gckGALDEVICE device = (gckGALDEVICE) ctxt;
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"Starting isr Thread with extension->%p",
device);
for (;;)
{
static int down;
down = down_interruptible(&device->sema);
device->dataReady = gcvFALSE;
if (device->killThread == gcvTRUE)
{
/* The daemon exits. */
while (!kthread_should_stop())
{
gckOS_Delay(device->os, 1);
}
return 0;
}
else
{
gckKERNEL_Notify(device->kernel, gcvNOTIFY_INTERRUPT, gcvFALSE);
}
}
}
/*******************************************************************************
**
** gckGALDEVICE_Setup_ISR
**
** Start the ISR routine.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** gcvSTATUS_OK
** Setup successfully.
** gcvSTATUS_GENERIC_IO
** Setup failed.
*/
gceSTATUS
gckGALDEVICE_Setup_ISR(
IN gckGALDEVICE Device
)
{
gctINT ret;
gcmkVERIFY_ARGUMENT(Device != NULL);
if (Device->irqLine == 0)
{
return gcvSTATUS_GENERIC_IO;
}
/* Hook up the isr based on the irq line. */
#ifdef FLAREON
gc500_handle.dev_name = "galcore interrupt service";
gc500_handle.dev_id = Device;
gc500_handle.handler = isrRoutine;
gc500_handle.intr_gen = GPIO_INTR_LEVEL_TRIGGER;
gc500_handle.intr_trig = GPIO_TRIG_HIGH_LEVEL;
ret = dove_gpio_request (DOVE_GPIO0_7, &gc500_handle);
#else
ret = request_irq(Device->irqLine,
isrRoutine,
IRQF_DISABLED,
"galcore interrupt service",
Device);
#endif
if (ret != 0) {
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Setup_ISR: "
"Could not register irq line->%d",
Device->irqLine);
Device->isrInitialized = gcvFALSE;
return gcvSTATUS_GENERIC_IO;
}
Device->isrInitialized = gcvTRUE;
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Setup_ISR: "
"Setup the irq line->%d",
Device->irqLine);
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Release_ISR
**
** Release the irq line.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Release_ISR(
IN gckGALDEVICE Device
)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
/* release the irq */
if (Device->isrInitialized)
{
#ifdef FLAREON
dove_gpio_free (DOVE_GPIO0_7, "galcore interrupt service");
#else
free_irq(Device->irqLine, Device);
#endif
}
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Start_Thread
**
** Start the daemon thread.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** gcvSTATUS_OK
** Start successfully.
** gcvSTATUS_GENERIC_IO
** Start failed.
*/
gceSTATUS
gckGALDEVICE_Start_Thread(
IN gckGALDEVICE Device
)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
/* start the kernel thread */
Device->threadCtxt = kthread_run(threadRoutine,
Device,
"galcore daemon thread");
Device->threadInitialized = gcvTRUE;
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Start_Thread: "
"Start the daemon thread.");
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Stop_Thread
**
** Stop the gal device, including the following actions: stop the daemon
** thread, release the irq.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Stop_Thread(
gckGALDEVICE Device
)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
/* stop the thread */
if (Device->threadInitialized)
{
Device->killThread = gcvTRUE;
up(&Device->sema);
kthread_stop(Device->threadCtxt);
}
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Start
**
** Start the gal device, including the following actions: setup the isr routine
** and start the daemoni thread.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** gcvSTATUS_OK
** Start successfully.
*/
gceSTATUS
gckGALDEVICE_Start(
IN gckGALDEVICE Device
)
{
/* start the daemon thread */
gcmkVERIFY_OK(gckGALDEVICE_Start_Thread(Device));
/* setup the isr routine */
gcmkVERIFY_OK(gckGALDEVICE_Setup_ISR(Device));
/* Switch to SUSPEND power state. */
gcmkVERIFY_OK(
gckHARDWARE_SetPowerManagementState(Device->kernel->hardware,
gcvPOWER_SUSPEND_ATPOWERON));
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Stop
**
** Stop the gal device, including the following actions: stop the daemon
** thread, release the irq.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Stop(
gckGALDEVICE Device
)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
/* Switch to ON power state. */
gcmkVERIFY_OK(
gckHARDWARE_SetPowerManagementState(Device->kernel->hardware,
gcvPOWER_ON));
if (Device->isrInitialized)
{
gckGALDEVICE_Release_ISR(Device);
}
if (Device->threadInitialized)
{
gckGALDEVICE_Stop_Thread(Device);
}
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Construct
**
** Constructor.
**
** INPUT:
**
** OUTPUT:
**
** gckGALDEVICE * Device
** Pointer to a variable receiving the gckGALDEVICE object pointer on
** success.
*/
gceSTATUS
gckGALDEVICE_Construct(
IN gctINT IrqLine,
IN gctUINT32 RegisterMemBase,
IN gctSIZE_T RegisterMemSize,
IN gctUINT32 ContiguousBase,
IN gctSIZE_T ContiguousSize,
IN gctSIZE_T BankSize,
IN gctINT FastClear,
IN gctINT Compression,
IN gctUINT32 BaseAddress,
IN gctINT Signal,
OUT gckGALDEVICE *Device
)
{
gctUINT32 internalBaseAddress = 0, internalAlignment = 0;
gctUINT32 externalBaseAddress = 0, externalAlignment = 0;
gctUINT32 horizontalTileSize, verticalTileSize;
gctUINT32 physAddr;
gctUINT32 physical;
gckGALDEVICE device;
gceSTATUS status;
gcmkTRACE(gcvLEVEL_VERBOSE, "[galcore] Enter gckGALDEVICE_Construct");
/* Allocate device structure. */
device = kmalloc(sizeof(struct _gckGALDEVICE), GFP_KERNEL);
if (!device)
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Can't allocate memory.");
return gcvSTATUS_OUT_OF_MEMORY;
}
memset(device, 0, sizeof(struct _gckGALDEVICE));
physical = RegisterMemBase;
/* Set up register memory region */
if (physical != 0)
{
/* Request a region. */
request_mem_region(RegisterMemBase, RegisterMemSize, "galcore register region");
device->registerBase = (gctPOINTER) ioremap_nocache(RegisterMemBase,
RegisterMemSize);
if (!device->registerBase)
{
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Unable to map location->0x%lX for size->%ld",
RegisterMemBase,
RegisterMemSize);
return gcvSTATUS_OUT_OF_RESOURCES;
}
physical += RegisterMemSize;
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: "
"RegisterBase after mapping Address->0x%x is 0x%x",
(gctUINT32)RegisterMemBase,
(gctUINT32)device->registerBase);
}
/* construct the gckOS object */
device->baseAddress = BaseAddress;
gcmkVERIFY_OK(gckOS_Construct(device, &device->os));
/* construct the gckKERNEL object. */
gcmkVERIFY_OK(gckKERNEL_Construct(device->os, device, &device->kernel));
gcmkVERIFY_OK(gckHARDWARE_SetFastClear(device->kernel->hardware,
FastClear,
Compression));
/* query the ceiling of the system memory */
gcmkVERIFY_OK(gckHARDWARE_QuerySystemMemory(device->kernel->hardware,
&device->systemMemorySize,
&device->systemMemoryBaseAddress));
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: "
"Will be trying to allocate contiguous memory of 0x%x bytes",
(gctUINT32)device->systemMemoryBaseAddress);
#if COMMAND_PROCESSOR_VERSION == 1
/* start the command queue */
gcmkVERIFY_OK(gckCOMMAND_Start(device->kernel->command));
#endif
/* initialize the thread daemon */
sema_init(&device->sema, 0);
device->threadInitialized = gcvFALSE;
device->killThread = gcvFALSE;
/* initialize the isr */
device->isrInitialized = gcvFALSE;
device->dataReady = gcvFALSE;
device->irqLine = IrqLine;
device->signal = Signal;
/* query the amount of video memory */
gcmkVERIFY_OK(gckHARDWARE_QueryMemory(device->kernel->hardware,
&device->internalSize,
&internalBaseAddress,
&internalAlignment,
&device->externalSize,
&externalBaseAddress,
&externalAlignment,
&horizontalTileSize,
&verticalTileSize));
/* set up the internal memory region */
if (device->internalSize > 0)
{
gceSTATUS status = gckVIDMEM_Construct(device->os,
internalBaseAddress,
device->internalSize,
internalAlignment,
0,
&device->internalVidMem);
if (gcmIS_ERROR(status))
{
/* error, remove internal heap */
device->internalSize = 0;
}
else
{
/* map internal memory */
device->internalPhysical = (gctPHYS_ADDR)physical;
device->internalLogical = (gctPOINTER)ioremap_nocache(
physical, device->internalSize);
gcmkASSERT(device->internalLogical != NULL);
physical += device->internalSize;
}
}
if (device->externalSize > 0)
{
/* create the external memory heap */
gceSTATUS status = gckVIDMEM_Construct(device->os,
externalBaseAddress,
device->externalSize,
externalAlignment,
0,
&device->externalVidMem);
if (gcmIS_ERROR(status))
{
/* error, remove internal heap */
device->externalSize = 0;
}
else
{
/* map internal memory */
device->externalPhysical = (gctPHYS_ADDR)physical;
device->externalLogical = (gctPOINTER)ioremap_nocache(
physical, device->externalSize);
gcmkASSERT(device->externalLogical != NULL);
physical += device->externalSize;
}
}
/* set up the contiguous memory */
device->contiguousSize = ContiguousSize;
if (ContiguousBase == 0)
{
status = gcvSTATUS_OUT_OF_MEMORY;
while (device->contiguousSize > 0)
{
gcmkTRACE_ZONE(
gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Will be trying to allocate contiguous memory of %ld bytes",
device->contiguousSize
);
/* allocate contiguous memory */
status = gckGALDEVICE_AllocateMemory(
device,
device->contiguousSize,
&device->contiguousBase,
&device->contiguousPhysical,
&physAddr
);
if (gcmIS_SUCCESS(status))
{
gcmkTRACE_ZONE(
gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Contiguous allocated size->0x%08X Virt->0x%08lX physAddr->0x%08X",
device->contiguousSize,
device->contiguousBase,
physAddr
);
status = gckVIDMEM_Construct(
device->os,
physAddr | device->systemMemoryBaseAddress,
device->contiguousSize,
64,
BankSize,
&device->contiguousVidMem
);
if (gcmIS_SUCCESS(status))
{
device->contiguousMapped = gcvFALSE;
/* success, abort loop */
gcmkTRACE_ZONE(
gcvLEVEL_INFO, gcvZONE_DRIVER,
"Using %u bytes of contiguous memory.",
device->contiguousSize
);
break;
}
gcmkVERIFY_OK(gckGALDEVICE_FreeMemory(
device,
device->contiguousBase,
device->contiguousPhysical
));
device->contiguousBase = NULL;
}
if (device->contiguousSize <= (4 << 20))
{
device->contiguousSize = 0;
}
else
{
device->contiguousSize -= (4 << 20);
}
}
}
else
{
/* Create the contiguous memory heap. */
status = gckVIDMEM_Construct(
device->os,
(ContiguousBase - device->baseAddress) | device->systemMemoryBaseAddress,
ContiguousSize,
64,
BankSize,
&device->contiguousVidMem
);
if (gcmIS_ERROR(status))
{
/* Error, roll back. */
device->contiguousVidMem = gcvNULL;
device->contiguousSize = 0;
}
else
{
/* Map the contiguous memory. */
request_mem_region(
ContiguousBase,
ContiguousSize,
"galcore managed memory"
);
device->contiguousPhysical = (gctPHYS_ADDR) ContiguousBase;
device->contiguousSize = ContiguousSize;
device->contiguousBase = (gctPOINTER) ioremap_nocache(ContiguousBase, ContiguousSize);
device->contiguousMapped = gcvTRUE;
if (device->contiguousBase == gcvNULL)
{
/* Error, roll back. */
gcmkVERIFY_OK(gckVIDMEM_Destroy(device->contiguousVidMem));
device->contiguousVidMem = gcvNULL;
device->contiguousSize = 0;
status = gcvSTATUS_OUT_OF_RESOURCES;
}
}
}
*Device = device;
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Initialized device->%p contiguous->%lu @ %p (0x%08X)",
device,
device->contiguousSize,
device->contiguousBase,
device->contiguousPhysical);
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Destroy
**
** Class destructor.
**
** INPUT:
**
** Nothing.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Destroy(
gckGALDEVICE Device)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
gcmkTRACE(gcvLEVEL_VERBOSE, "[ENTER] gckGALDEVICE_Destroy");
/* Destroy the gckKERNEL object. */
gcmkVERIFY_OK(gckKERNEL_Destroy(Device->kernel));
if (Device->internalVidMem != gcvNULL)
{
/* destroy the internal heap */
gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->internalVidMem));
/* unmap the internal memory */
iounmap(Device->internalLogical);
}
if (Device->externalVidMem != gcvNULL)
{
/* destroy the internal heap */
gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->externalVidMem));
/* unmap the external memory */
iounmap(Device->externalLogical);
}
if (Device->contiguousVidMem != gcvNULL)
{
/* Destroy the contiguous heap */
gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->contiguousVidMem));
if (Device->contiguousMapped)
{
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Destroy: "
"Unmapping contiguous memory->0x%08lX",
Device->contiguousBase);
iounmap(Device->contiguousBase);
}
else
{
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Destroy: "
"Freeing contiguous memory->0x%08lX",
Device->contiguousBase);
gcmkVERIFY_OK(gckGALDEVICE_FreeMemory(Device,
Device->contiguousBase,
Device->contiguousPhysical));
}
}
if (Device->registerBase)
{
iounmap(Device->registerBase);
}
/* Destroy the gckOS object. */
gcmkVERIFY_OK(gckOS_Destroy(Device->os));
kfree(Device);
gcmkTRACE(gcvLEVEL_VERBOSE, "[galcore] Leave gckGALDEVICE_Destroy");
return gcvSTATUS_OK;
}

148
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_device.h Normal file
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@ -0,0 +1,148 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_kernel_device_h_
#define __gc_hal_kernel_device_h_
#define gcdkUSE_MEMORY_RECORD 1
#ifdef ANDROID
#define gcdkREPORT_VIDMEM_LEAK 0
#else
#define gcdkREPORT_VIDMEM_LEAK 1
#endif
/******************************************************************************\
******************************* gckGALDEVICE Structure *******************************
\******************************************************************************/
typedef struct _gckGALDEVICE
{
/* Objects. */
gckOS os;
gckKERNEL kernel;
/* Attributes. */
gctSIZE_T internalSize;
gctPHYS_ADDR internalPhysical;
gctPOINTER internalLogical;
gckVIDMEM internalVidMem;
gctSIZE_T externalSize;
gctPHYS_ADDR externalPhysical;
gctPOINTER externalLogical;
gckVIDMEM externalVidMem;
gckVIDMEM contiguousVidMem;
gctPOINTER contiguousBase;
gctPHYS_ADDR contiguousPhysical;
gctSIZE_T contiguousSize;
gctBOOL contiguousMapped;
gctPOINTER contiguousMappedUser;
gctSIZE_T systemMemorySize;
gctUINT32 systemMemoryBaseAddress;
gctPOINTER registerBase;
gctSIZE_T registerSize;
gctUINT32 baseAddress;
/* IRQ management. */
gctINT irqLine;
gctBOOL isrInitialized;
gctBOOL dataReady;
/* Thread management. */
struct task_struct *threadCtxt;
struct semaphore sema;
gctBOOL threadInitialized;
gctBOOL killThread;
/* Signal management. */
gctINT signal;
}
* gckGALDEVICE;
#if gcdkUSE_MEMORY_RECORD
typedef struct MEMORY_RECORD
{
gcuVIDMEM_NODE_PTR node;
struct MEMORY_RECORD * prev;
struct MEMORY_RECORD * next;
}
MEMORY_RECORD, * MEMORY_RECORD_PTR;
#endif
typedef struct _gcsHAL_PRIVATE_DATA
{
gckGALDEVICE device;
gctPOINTER mappedMemory;
gctPOINTER contiguousLogical;
#if gcdkUSE_MEMORY_RECORD
MEMORY_RECORD memoryRecordList;
#endif
}
gcsHAL_PRIVATE_DATA, * gcsHAL_PRIVATE_DATA_PTR;
gceSTATUS gckGALDEVICE_Setup_ISR(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Release_ISR(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Start_Thread(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Stop_Thread(
gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Start(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Stop(
gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Construct(
IN gctINT IrqLine,
IN gctUINT32 RegisterMemBase,
IN gctSIZE_T RegisterMemSize,
IN gctUINT32 ContiguousBase,
IN gctSIZE_T ContiguousSize,
IN gctSIZE_T BankSize,
IN gctINT FastClear,
IN gctINT Compression,
IN gctUINT32 BaseAddress,
IN gctINT Signal,
OUT gckGALDEVICE *Device
);
gceSTATUS gckGALDEVICE_Destroy(
IN gckGALDEVICE Device
);
#endif /* __gc_hal_kernel_device_h_ */

804
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_driver.c Normal file
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@ -0,0 +1,804 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#include <linux/device.h>
#include <linux/miscdevice.h>
#include "gc_hal_kernel_linux.h"
#include "gc_hal_driver.h"
#include "gc_hal_user_context.h"
#if USE_PLATFORM_DRIVER
#include <linux/platform_device.h>
#endif
MODULE_DESCRIPTION("Vivante Graphics Driver");
MODULE_LICENSE("GPL");
struct class *gpuClass;
static gckGALDEVICE galDevice;
static int major = 199;
module_param(major, int, 0644);
int irqLine = 0;
module_param(irqLine, int, 0644);
long registerMemBase = 0x80000000;
module_param(registerMemBase, long, 0644);
ulong registerMemSize = 256 << 10;
module_param(registerMemSize, ulong, 0644);
long contiguousSize = 4 << 20;
module_param(contiguousSize, long, 0644);
ulong contiguousBase = 0;
module_param(contiguousBase, ulong, 0644);
long bankSize = 32 << 20;
module_param(bankSize, long, 0644);
int fastClear = -1;
module_param(fastClear, int, 0644);
int compression = -1;
module_param(compression, int, 0644);
int signal = 48;
module_param(signal, int, 0644);
ulong baseAddress = 0;
module_param(baseAddress, ulong, 0644);
int showArgs = 0;
module_param(showArgs, int, 0644);
static int drv_open(struct inode *inode, struct file *filp);
static int drv_release(struct inode *inode, struct file *filp);
static int drv_ioctl(struct inode *inode, struct file *filp,
unsigned int ioctlCode, unsigned long arg);
static int drv_mmap(struct file * filp, struct vm_area_struct * vma);
struct file_operations driver_fops =
{
.open = drv_open,
.release = drv_release,
.ioctl = drv_ioctl,
.mmap = drv_mmap,
};
int drv_open(struct inode *inode, struct file* filp)
{
gcsHAL_PRIVATE_DATA_PTR private;
gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_DRIVER,
"Entering drv_open\n");
private = kmalloc(sizeof(gcsHAL_PRIVATE_DATA), GFP_KERNEL);
if (private == gcvNULL)
{
return -ENOTTY;
}
private->device = galDevice;
private->mappedMemory = gcvNULL;
private->contiguousLogical = gcvNULL;
#if gcdkUSE_MEMORY_RECORD
private->memoryRecordList.prev = &private->memoryRecordList;
private->memoryRecordList.next = &private->memoryRecordList;
#endif
/* A process gets attached. */
gcmkVERIFY_OK(
gckKERNEL_AttachProcess(galDevice->kernel, gcvTRUE));
if (!galDevice->contiguousMapped)
{
gcmkVERIFY_OK(gckOS_MapMemory(galDevice->os,
galDevice->contiguousPhysical,
galDevice->contiguousSize,
&private->contiguousLogical));
}
filp->private_data = private;
return 0;
}
extern void
OnProcessExit(
IN gckOS Os,
IN gckKERNEL Kernel
);
int drv_release(struct inode* inode, struct file* filp)
{
gcsHAL_PRIVATE_DATA_PTR private;
gckGALDEVICE device;
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"Entering drv_close\n");
private = filp->private_data;
gcmkASSERT(private != gcvNULL);
device = private->device;
#if gcdkUSE_MEMORY_RECORD
FreeAllMemoryRecord(galDevice->os, &private->memoryRecordList);
#ifdef ANDROID
gcmkVERIFY_OK(gckOS_Delay(galDevice->os, 1000));
#else
gcmkVERIFY_OK(gckCOMMAND_Stall(device->kernel->command));
#endif
#endif
if (!device->contiguousMapped)
{
if (private->contiguousLogical != gcvNULL)
{
gcmkVERIFY_OK(gckOS_UnmapMemory(galDevice->os,
galDevice->contiguousPhysical,
galDevice->contiguousSize,
private->contiguousLogical));
}
}
/* A process gets detached. */
gcmkVERIFY_OK(
gckKERNEL_AttachProcess(galDevice->kernel, gcvFALSE));
kfree(private);
filp->private_data = NULL;
return 0;
}
int drv_ioctl(struct inode *inode,
struct file *filp,
unsigned int ioctlCode,
unsigned long arg)
{
gcsHAL_INTERFACE iface;
gctUINT32 copyLen;
DRIVER_ARGS drvArgs;
gckGALDEVICE device;
gceSTATUS status;
gcsHAL_PRIVATE_DATA_PTR private;
private = filp->private_data;
if (private == gcvNULL)
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] drv_ioctl: private_data is NULL\n");
return -ENOTTY;
}
device = private->device;
if (device == gcvNULL)
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] drv_ioctl: device is NULL\n");
return -ENOTTY;
}
if (ioctlCode != IOCTL_GCHAL_INTERFACE
&& ioctlCode != IOCTL_GCHAL_KERNEL_INTERFACE)
{
/* Unknown command. Fail the I/O. */
return -ENOTTY;
}
/* Get the drvArgs to begin with. */
copyLen = copy_from_user(&drvArgs,
(void *) arg,
sizeof(DRIVER_ARGS));
if (copyLen != 0)
{
/* The input buffer is not big enough. So fail the I/O. */
return -ENOTTY;
}
/* Now bring in the gcsHAL_INTERFACE structure. */
if ((drvArgs.InputBufferSize != sizeof(gcsHAL_INTERFACE))
|| (drvArgs.OutputBufferSize != sizeof(gcsHAL_INTERFACE))
)
{
return -ENOTTY;
}
copyLen = copy_from_user(&iface,
drvArgs.InputBuffer,
sizeof(gcsHAL_INTERFACE));
if (copyLen != 0)
{
/* The input buffer is not big enough. So fail the I/O. */
return -ENOTTY;
}
#if gcdkUSE_MEMORY_RECORD
if (iface.command == gcvHAL_EVENT_COMMIT)
{
MEMORY_RECORD_PTR mr;
gcsQUEUE_PTR queue = iface.u.Event.queue;
while (queue != gcvNULL)
{
gcsQUEUE_PTR record, next;
/* Map record into kernel memory. */
gcmkERR_BREAK(gckOS_MapUserPointer(device->os,
queue,
gcmSIZEOF(gcsQUEUE),
(gctPOINTER *) &record));
switch (record->iface.command)
{
case gcvHAL_FREE_VIDEO_MEMORY:
mr = FindMemoryRecord(device->os,
&private->memoryRecordList,
record->iface.u.FreeVideoMemory.node);
if (mr != gcvNULL)
{
DestoryMemoryRecord(device->os, mr);
}
else
{
printk("*ERROR* Invalid video memory (%p) for free\n",
record->iface.u.FreeVideoMemory.node);
}
break;
default:
break;
}
/* Next record in the queue. */
next = record->next;
/* Unmap record from kernel memory. */
gcmkERR_BREAK(gckOS_UnmapUserPointer(device->os,
queue,
gcmSIZEOF(gcsQUEUE),
(gctPOINTER *) record));
queue = next;
}
}
#endif
status = gckKERNEL_Dispatch(device->kernel,
(ioctlCode == IOCTL_GCHAL_INTERFACE) , &iface);
if (gcmIS_ERROR(status))
{
gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DRIVER,
"[galcore] gckKERNEL_Dispatch returned %d.\n",
status);
}
else if (gcmIS_ERROR(iface.status))
{
gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DRIVER,
"[galcore] IOCTL %d returned %d.\n",
iface.command,
iface.status);
}
/* See if this was a LOCK_VIDEO_MEMORY command. */
else if (iface.command == gcvHAL_LOCK_VIDEO_MEMORY)
{
/* Special case for mapped memory. */
if (private->mappedMemory != gcvNULL
&& iface.u.LockVideoMemory.node->VidMem.memory->object.type
== gcvOBJ_VIDMEM)
{
/* Compute offset into mapped memory. */
gctUINT32 offset = (gctUINT8 *) iface.u.LockVideoMemory.memory
- (gctUINT8 *) device->contiguousBase;
/* Compute offset into user-mapped region. */
iface.u.LockVideoMemory.memory =
(gctUINT8 *) private->mappedMemory + offset;
}
}
#if gcdkUSE_MEMORY_RECORD
else if (iface.command == gcvHAL_ALLOCATE_VIDEO_MEMORY)
{
CreateMemoryRecord(device->os,
&private->memoryRecordList,
iface.u.AllocateVideoMemory.node);
}
else if (iface.command == gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY)
{
CreateMemoryRecord(device->os,
&private->memoryRecordList,
iface.u.AllocateLinearVideoMemory.node);
}
else if (iface.command == gcvHAL_FREE_VIDEO_MEMORY)
{
MEMORY_RECORD_PTR mr;
mr = FindMemoryRecord(device->os,
&private->memoryRecordList,
iface.u.FreeVideoMemory.node);
if (mr != gcvNULL)
{
DestoryMemoryRecord(device->os, mr);
}
else
{
printk("*ERROR* Invalid video memory for free\n");
}
}
#endif
/* Copy data back to the user. */
copyLen = copy_to_user(drvArgs.OutputBuffer,
&iface,
sizeof(gcsHAL_INTERFACE));
if (copyLen != 0)
{
/* The output buffer is not big enough. So fail the I/O. */
return -ENOTTY;
}
return 0;
}
static int drv_mmap(struct file * filp, struct vm_area_struct * vma)
{
gcsHAL_PRIVATE_DATA_PTR private = filp->private_data;
gckGALDEVICE device;
int ret;
unsigned long size = vma->vm_end - vma->vm_start;
if (private == gcvNULL)
{
return -ENOTTY;
}
device = private->device;
if (device == gcvNULL)
{
return -ENOTTY;
}
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND;
vma->vm_pgoff = 0;
if (device->contiguousMapped)
{
ret = io_remap_pfn_range(vma,
vma->vm_start,
(gctUINT32) device->contiguousPhysical >> PAGE_SHIFT,
size,
vma->vm_page_prot);
private->mappedMemory = (ret == 0) ? (gctPOINTER) vma->vm_start : gcvNULL;
return ret;
}
else
{
return -ENOTTY;
}
}
static struct miscdevice miscdev = {
.name = "galcore",
.fops = &driver_fops,
.minor = MISC_DYNAMIC_MINOR,
};
#if !USE_PLATFORM_DRIVER
static int __init drv_init(void)
#else
static int drv_init(void)
#endif
{
int ret;
gckGALDEVICE device;
#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
struct clk * clk = NULL;
#endif
gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_DRIVER,
"Entering drv_init\n");
#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
clk = clk_get(NULL, "GCCLK");
if (IS_ERR(clk))
{
int retval = PTR_ERR(clk);
printk("clk get error: %d\n", retval);
return -ENODEV;
}
/* APMU_GC_156M, APMU_GC_624M, APMU_GC_PLL2, APMU_GC_PLL2_DIV2 currently */
if (clk_set_rate(clk, 624000000))
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] Can't set core clock.");
return -EAGAIN;
}
clk_enable(clk);
#endif
if (showArgs)
{
printk("galcore options:\n");
printk(" irqLine = %d\n", irqLine);
printk(" registerMemBase = 0x%08lX\n", registerMemBase);
printk(" contiguousSize = %ld\n", contiguousSize);
printk(" contiguousBase = 0x%08lX\n", contiguousBase);
printk(" bankSize = 0x%08lX\n", bankSize);
printk(" fastClear = %d\n", fastClear);
printk(" compression = %d\n", compression);
printk(" signal = %d\n", signal);
printk(" baseAddress = 0x%08lX\n", baseAddress);
}
/* Create the GAL device. */
gcmkVERIFY_OK(gckGALDEVICE_Construct(irqLine,
registerMemBase,
registerMemSize,
contiguousBase,
contiguousSize,
bankSize,
fastClear,
compression,
baseAddress,
signal,
&device));
/* Start the GAL device. */
if (gcmIS_ERROR(gckGALDEVICE_Start(device)))
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] Can't start the gal device.\n");
/* Roll back. */
gckGALDEVICE_Stop(device);
gckGALDEVICE_Destroy(device);
return -1;
}
#if 1
ret = misc_register(&miscdev);
if (ret < 0)
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] Could not register misc.\n");
/* Roll back. */
gckGALDEVICE_Stop(device);
gckGALDEVICE_Destroy(device);
return -1;
}
galDevice = device;
#else
/* Register the character device. */
ret = register_chrdev(major, DRV_NAME, &driver_fops);
if (ret < 0)
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] Could not allocate major number for mmap.\n");
/* Roll back. */
gckGALDEVICE_Stop(device);
gckGALDEVICE_Destroy(device);
return -1;
}
else
{
if (major == 0)
{
major = ret;
}
}
galDevice = device;
gpuClass = class_create(THIS_MODULE, "graphics_class");
if (IS_ERR(gpuClass)) {
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"Failed to create the class.\n");
return -1;
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
device_create(gpuClass, NULL, MKDEV(major, 0), NULL, "galcore");
#else
device_create(gpuClass, NULL, MKDEV(major, 0), "galcore");
#endif
#endif
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] irqLine->%ld, contiguousSize->%lu, memBase->0x%lX\n",
irqLine,
contiguousSize,
registerMemBase);
gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_DRIVER,
"[galcore] driver registered successfully.\n");
return 0;
}
#if !USE_PLATFORM_DRIVER
static void __exit drv_exit(void)
#else
static void drv_exit(void)
#endif
{
#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
struct clk * clk = NULL;
#endif
gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_DRIVER,
"[galcore] Entering drv_exit\n");
#if 1
misc_deregister(&miscdev);
#else
device_destroy(gpuClass, MKDEV(major, 0));
class_destroy(gpuClass);
unregister_chrdev(major, DRV_NAME);
#endif
gckGALDEVICE_Stop(galDevice);
gckGALDEVICE_Destroy(galDevice);
#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
clk = clk_get(NULL, "GCCLK");
clk_disable(clk);
#endif
}
#if !USE_PLATFORM_DRIVER
module_init(drv_init);
module_exit(drv_exit);
#else
#ifdef CONFIG_DOVE_GPU
#define DEVICE_NAME "dove_gpu"
#else
#define DEVICE_NAME "galcore"
#endif
static int __devinit gpu_probe(struct platform_device *pdev)
{
int ret = -ENODEV;
struct resource *res;
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,"gpu_irq");
if (!res) {
printk(KERN_ERR "%s: No irq line supplied.\n",__FUNCTION__);
goto gpu_probe_fail;
}
irqLine = res->start;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,"gpu_base");
if (!res) {
printk(KERN_ERR "%s: No register base supplied.\n",__FUNCTION__);
goto gpu_probe_fail;
}
registerMemBase = res->start;
registerMemSize = res->end - res->start;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,"gpu_mem");
if (!res) {
printk(KERN_ERR "%s: No memory base supplied.\n",__FUNCTION__);
goto gpu_probe_fail;
}
contiguousBase = res->start;
contiguousSize = res->end-res->start;
ret = drv_init();
if(!ret) {
platform_set_drvdata(pdev,galDevice);
return ret;
}
gpu_probe_fail:
printk(KERN_INFO "Failed to register gpu driver.\n");
return ret;
}
static int __devinit gpu_remove(struct platform_device *pdev)
{
drv_exit();
return 0;
}
static int __devinit gpu_suspend(struct platform_device *dev, pm_message_t state)
{
gceSTATUS status;
gckGALDEVICE device;
device = platform_get_drvdata(dev);
status = gckHARDWARE_SetPowerManagementState(device->kernel->hardware, gcvPOWER_OFF);
if (gcmIS_ERROR(status))
{
return -1;
}
return 0;
}
static int __devinit gpu_resume(struct platform_device *dev)
{
gceSTATUS status;
gckGALDEVICE device;
device = platform_get_drvdata(dev);
status = gckHARDWARE_SetPowerManagementState(device->kernel->hardware, gcvPOWER_ON);
if (gcmIS_ERROR(status))
{
return -1;
}
return 0;
}
static struct platform_driver gpu_driver = {
.probe = gpu_probe,
.remove = gpu_remove,
.suspend = gpu_suspend,
.resume = gpu_resume,
.driver = {
.name = DEVICE_NAME,
}
};
#if 0
#ifndef CONFIG_DOVE_GPU
static struct resource gpu_resources[] = {
{
.name = "gpu_irq",
.flags = IORESOURCE_IRQ,
},
{
.name = "gpu_base",
.flags = IORESOURCE_MEM,
},
{
.name = "gpu_mem",
.flags = IORESOURCE_MEM,
},
};
static struct platform_device * gpu_device;
#endif
#endif
static int __init gpu_init(void)
{
int ret = 0;
#if 0 //add by dkm
#ifndef CONFIG_DOVE_GPU
gpu_resources[0].start = gpu_resources[0].end = irqLine;
gpu_resources[1].start = registerMemBase;
gpu_resources[1].end = registerMemBase + registerMemSize;
gpu_resources[2].start = contiguousBase;
gpu_resources[2].end = contiguousBase + contiguousSize;
/* Allocate device */
gpu_device = platform_device_alloc(DEVICE_NAME, -1);
if (!gpu_device)
{
printk(KERN_ERR "galcore: platform_device_alloc failed.\n");
ret = -ENOMEM;
goto out;
}
/* Insert resource */
ret = platform_device_add_resources(gpu_device, gpu_resources, 3);
if (ret)
{
printk(KERN_ERR "galcore: platform_device_add_resources failed.\n");
goto put_dev;
}
/* Add device */
ret = platform_device_add(gpu_device);
if (ret)
{
printk(KERN_ERR "galcore: platform_device_add failed.\n");
goto del_dev;
}
#endif
#endif
ret = platform_driver_register(&gpu_driver);
if (!ret)
{
goto out;
}
#if 0 //add by dkm
#ifndef CONFIG_DOVE_GPU
del_dev:
platform_device_del(gpu_device);
put_dev:
platform_device_put(gpu_device);
#endif
#endif
out:
return ret;
}
static void __exit gpu_exit(void)
{
platform_driver_unregister(&gpu_driver);
#if 0 //add by dkm
#ifndef CONFIG_DOVE_GPU
platform_device_unregister(gpu_device);
#endif
#endif
}
module_init(gpu_init);
module_exit(gpu_exit);
#endif

411
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_linux.c Normal file
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@ -0,0 +1,411 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#include "gc_hal_kernel_linux.h"
#define _GC_OBJ_ZONE gcvZONE_KERNEL
/******************************************************************************\
******************************* gckKERNEL API Code ******************************
\******************************************************************************/
/*******************************************************************************
**
** gckKERNEL_QueryVideoMemory
**
** Query the amount of video memory.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** OUTPUT:
**
** gcsHAL_INTERFACE * Interface
** Pointer to an gcsHAL_INTERFACE structure that will be filled in with
** the memory information.
*/
gceSTATUS
gckKERNEL_QueryVideoMemory(
IN gckKERNEL Kernel,
OUT gcsHAL_INTERFACE * Interface
)
{
gckGALDEVICE device;
gcmkHEADER_ARG("Kernel=%p", Kernel);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(Interface != NULL);
/* Extract the pointer to the gckGALDEVICE class. */
device = (gckGALDEVICE) Kernel->context;
/* Get internal memory size and physical address. */
Interface->u.QueryVideoMemory.internalSize = device->internalSize;
Interface->u.QueryVideoMemory.internalPhysical = device->internalPhysical;
/* Get external memory size and physical address. */
Interface->u.QueryVideoMemory.externalSize = device->externalSize;
Interface->u.QueryVideoMemory.externalPhysical = device->externalPhysical;
/* Get contiguous memory size and physical address. */
Interface->u.QueryVideoMemory.contiguousSize = device->contiguousSize;
Interface->u.QueryVideoMemory.contiguousPhysical = device->contiguousPhysical;
/* Success. */
gcmkFOOTER_NO();
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckKERNEL_GetVideoMemoryPool
**
** Get the gckVIDMEM object belonging to the specified pool.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gcePOOL Pool
** Pool to query gckVIDMEM object for.
**
** OUTPUT:
**
** gckVIDMEM * VideoMemory
** Pointer to a variable that will hold the pointer to the gckVIDMEM
** object belonging to the requested pool.
*/
gceSTATUS
gckKERNEL_GetVideoMemoryPool(
IN gckKERNEL Kernel,
IN gcePOOL Pool,
OUT gckVIDMEM * VideoMemory
)
{
gckGALDEVICE device;
gckVIDMEM videoMemory;
gcmkHEADER_ARG("Kernel=%p Pool=%d", Kernel, Pool);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(VideoMemory != NULL);
/* Extract the pointer to the gckGALDEVICE class. */
device = (gckGALDEVICE) Kernel->context;
/* Dispatch on pool. */
switch (Pool)
{
case gcvPOOL_LOCAL_INTERNAL:
/* Internal memory. */
videoMemory = device->internalVidMem;
break;
case gcvPOOL_LOCAL_EXTERNAL:
/* External memory. */
videoMemory = device->externalVidMem;
break;
case gcvPOOL_SYSTEM:
/* System memory. */
videoMemory = device->contiguousVidMem;
break;
default:
/* Unknown pool. */
videoMemory = NULL;
}
/* Return pointer to the gckVIDMEM object. */
*VideoMemory = videoMemory;
/* Return status. */
gcmkFOOTER_ARG("*VideoMemory=%p", *VideoMemory);
return (videoMemory == NULL) ? gcvSTATUS_OUT_OF_MEMORY : gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckKERNEL_MapMemory
**
** Map video memory into the current process space.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctPHYS_ADDR Physical
** Physical address of video memory to map.
**
** gctSIZE_T Bytes
** Number of bytes to map.
**
** OUTPUT:
**
** gctPOINTER * Logical
** Pointer to a variable that will hold the base address of the mapped
** memory region.
*/
gceSTATUS
gckKERNEL_MapMemory(
IN gckKERNEL Kernel,
IN gctPHYS_ADDR Physical,
IN gctSIZE_T Bytes,
OUT gctPOINTER * Logical
)
{
return gckOS_MapMemory(Kernel->os, Physical, Bytes, Logical);
}
/*******************************************************************************
**
** gckKERNEL_UnmapMemory
**
** Unmap video memory from the current process space.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctPHYS_ADDR Physical
** Physical address of video memory to map.
**
** gctSIZE_T Bytes
** Number of bytes to map.
**
** gctPOINTER Logical
** Base address of the mapped memory region.
**
** OUTPUT:
**
** Nothing.
*/
gceSTATUS
gckKERNEL_UnmapMemory(
IN gckKERNEL Kernel,
IN gctPHYS_ADDR Physical,
IN gctSIZE_T Bytes,
IN gctPOINTER Logical
)
{
return gckOS_UnmapMemory(Kernel->os, Physical, Bytes, Logical);
}
/*******************************************************************************
**
** gckKERNEL_MapVideoMemory
**
** Get the logical address for a hardware specific memory address for the
** current process.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctBOOL InUserSpace
** gcvTRUE to map the memory into the user space.
**
** gctUINT32 Address
** Hardware specific memory address.
**
** OUTPUT:
**
** gctPOINTER * Logical
** Pointer to a variable that will hold the logical address of the
** specified memory address.
*/
gceSTATUS
gckKERNEL_MapVideoMemory(
IN gckKERNEL Kernel,
IN gctBOOL InUserSpace,
IN gctUINT32 Address,
OUT gctPOINTER * Logical
)
{
gckGALDEVICE device;
PLINUX_MDL mdl;
PLINUX_MDL_MAP mdlMap;
gcePOOL pool;
gctUINT32 offset, base;
gceSTATUS status;
gctPOINTER logical;
gcmkHEADER_ARG("Kernel=%p InUserSpace=%d Address=%08x",
Kernel, InUserSpace, Address);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(Logical != NULL);
/* Extract the pointer to the gckGALDEVICE class. */
device = (gckGALDEVICE) Kernel->context;
/* Split the memory address into a pool type and offset. */
gcmkONERROR(
gckHARDWARE_SplitMemory(Kernel->hardware, Address, &pool, &offset));
/* Dispatch on pool. */
switch (pool)
{
case gcvPOOL_LOCAL_INTERNAL:
/* Internal memory. */
logical = device->internalLogical;
break;
case gcvPOOL_LOCAL_EXTERNAL:
/* External memory. */
logical = device->externalLogical;
break;
case gcvPOOL_SYSTEM:
/* System memory. */
if (device->contiguousMapped)
{
logical = device->contiguousBase;
}
else
{
mdl = (PLINUX_MDL) device->contiguousPhysical;
mdlMap = FindMdlMap(mdl, current->tgid);
gcmkASSERT(mdlMap);
logical = (gctPOINTER) mdlMap->vmaAddr;
}
gcmkVERIFY_OK(
gckHARDWARE_SplitMemory(Kernel->hardware,
device->contiguousVidMem->baseAddress,
&pool,
&base));
offset -= base;
break;
default:
/* Invalid memory pool. */
gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
}
/* Build logical address of specified address. */
*Logical = (gctPOINTER) ((gctUINT8_PTR) logical + offset);
/* Success. */
gcmkFOOTER_ARG("*Logical=%p", *Logical);
return gcvSTATUS_OK;
OnError:
/* Retunn the status. */
gcmkFOOTER();
return status;
}
/*******************************************************************************
**
** gckKERNEL_Notify
**
** This function iscalled by clients to notify the gckKERNRL object of an event.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gceNOTIFY Notification
** Notification event.
**
** OUTPUT:
**
** Nothing.
*/
gceSTATUS
gckKERNEL_Notify(
IN gckKERNEL Kernel,
IN gceNOTIFY Notification,
IN gctBOOL Data
)
{
gceSTATUS status;
gcmkHEADER_ARG("Kernel=%p Notification=%d Data=%d",
Kernel, Notification, Data);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
/* Dispatch on notifcation. */
switch (Notification)
{
case gcvNOTIFY_INTERRUPT:
/* Process the interrupt. */
#if COMMAND_PROCESSOR_VERSION > 1
status = gckINTERRUPT_Notify(Kernel->interrupt, Data);
#else
status = gckHARDWARE_Interrupt(Kernel->hardware, Data);
#endif
break;
default:
status = gcvSTATUS_OK;
break;
}
/* Success. */
gcmkFOOTER();
return status;
}
gceSTATUS
gckKERNEL_QuerySettings(
IN gckKERNEL Kernel,
OUT gcsKERNEL_SETTINGS * Settings
)
{
gckGALDEVICE device;
gcmkHEADER_ARG("Kernel=%p", Kernel);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(Settings != gcvNULL);
/* Extract the pointer to the gckGALDEVICE class. */
device = (gckGALDEVICE) Kernel->context;
/* Fill in signal. */
Settings->signal = device->signal;
/* Success. */
gcmkFOOTER_ARG("Settings->signal=%d", Settings->signal);
return gcvSTATUS_OK;
}

89
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_linux.h Normal file
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@ -0,0 +1,89 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_kernel_linux_h_
#define __gc_hal_kernel_linux_h_
#include <linux/version.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/signal.h>
#ifdef FLAREON
# include <asm/arch-realview/dove_gpio_irq.h>
#endif
#include <linux/interrupt.h>
#include <linux/vmalloc.h>
#include <linux/dma-mapping.h>
#include <linux/kthread.h>
#ifdef MODVERSIONS
# include <linux/modversions.h>
#endif
#include <asm/io.h>
#include <asm/uaccess.h>
#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
#include <linux/clk.h>
#endif
#define NTSTRSAFE_NO_CCH_FUNCTIONS
#include "gc_hal.h"
#include "gc_hal_driver.h"
#include "gc_hal_kernel.h"
#include "gc_hal_kernel_device.h"
#include "gc_hal_kernel_os.h"
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
#define FIND_TASK_BY_PID(x) pid_task(find_vpid(x), PIDTYPE_PID)
#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
#define FIND_TASK_BY_PID(x) find_task_by_vpid(x)
#else
#define FIND_TASK_BY_PID(x) find_task_by_pid(x)
#endif
#define _WIDE(string) L##string
#define WIDE(string) _WIDE(string)
#define countof(a) (sizeof(a) / sizeof(a[0]))
#define DRV_NAME "galcore"
#define GetPageCount(size, offset) ((((size) + ((offset) & ~PAGE_CACHE_MASK)) + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT)
static inline gctINT
GetOrder(
IN gctINT numPages
)
{
gctINT order = 0;
while ((1 << order) < numPages) order++;
return order;
}
#endif /* __gc_hal_kernel_linux_h_ */

5698
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_os.c Normal file
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File diff suppressed because it is too large Load Diff

106
drivers/staging/rk29/vivante/hal/os/linux/kernel/gc_hal_kernel_os.h Normal file
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@ -0,0 +1,106 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_kernel_os_h_
#define __gc_hal_kernel_os_h_
typedef struct _LINUX_MDL_MAP
{
gctINT pid;
gctPOINTER vmaAddr;
struct vm_area_struct * vma;
struct _LINUX_MDL_MAP * next;
}
LINUX_MDL_MAP, *PLINUX_MDL_MAP;
typedef struct _LINUX_MDL
{
gctINT pid;
char * addr;
#ifdef NO_DMA_COHERENT
gctPOINTER kaddr;
#endif /* NO_DMA_COHERENT */
gctINT numPages;
gctINT pagedMem;
gctBOOL contiguous;
dma_addr_t dmaHandle;
PLINUX_MDL_MAP maps;
struct _LINUX_MDL * prev;
struct _LINUX_MDL * next;
}
LINUX_MDL, *PLINUX_MDL;
extern PLINUX_MDL_MAP
FindMdlMap(
IN PLINUX_MDL Mdl,
IN gctINT PID
);
typedef struct _DRIVER_ARGS
{
gctPOINTER InputBuffer;
gctUINT32 InputBufferSize;
gctPOINTER OutputBuffer;
gctUINT32 OutputBufferSize;
}
DRIVER_ARGS;
/* Cleanup the signal table. */
gceSTATUS
gckOS_CleanProcessSignal(
gckOS Os,
gctHANDLE Process
);
#ifdef gcdkUSE_MEMORY_RECORD
MEMORY_RECORD_PTR
CreateMemoryRecord(
gckOS Os,
MEMORY_RECORD_PTR List,
gcuVIDMEM_NODE_PTR Node
);
void
DestoryMemoryRecord(
gckOS Os,
MEMORY_RECORD_PTR Mr
);
MEMORY_RECORD_PTR
FindMemoryRecord(
gckOS Os,
MEMORY_RECORD_PTR List,
gcuVIDMEM_NODE_PTR Node
);
void
FreeAllMemoryRecord(
gckOS Os,
MEMORY_RECORD_PTR List
);
#endif
#endif /* __gc_hal_kernel_os_h_ */

79
drivers/staging/rk29/vivante/hal/os/qnx/inc/gc_hal_common_qnx.h Normal file
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/****************************************************************************
*
* Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
*
* The material in this file is confidential and contains trade secrets
* of Vivante Corporation. This is proprietary information owned by
* Vivante Corporation. No part of this work may be disclosed,
* reproduced, copied, transmitted, or used in any way for any purpose,
* without the express written permission of Vivante Corporation.
*
*****************************************************************************
*
* Auto-generated file on 10/12/2010. Do not edit!!!
*
*****************************************************************************/
/*
* gc_hal_common_qnx.h
*
* Created on: Jul 7, 2010
* Author: tarang
*/
#ifndef GC_HAL_COMMON_QNX_H_
#define GC_HAL_COMMON_QNX_H_
/******************************************************************************\
******************************* QNX Control Codes ******************************
\******************************************************************************/
#ifndef _IOMGR_VIVANTE
#define _IOMGR_VIVANTE (_IOMGR_PRIVATE_BASE + 0x301)
#endif
/*******************************************************************************
** Signal management.
**
** Is much simpler in Neutrino versus Linux :-)
**
** Neutrino pulses are equivalent to RT signals (queued, small payload) except
** they are explicitly received on a channel. We therefore dedicate a thread
** to handle them.
**
** We don't use RT signals because:
** 1. They can be delivered on any thread.
** 2. We don't support SA_RESTART so blocking kernel calls can fail. It would be
** impossible to robustly handle this condition in all libraries.
**
** Only downside is that more information needs to be passed between client/server
** (signals require only PID, pulses require connection ID and receive ID).
*/
typedef struct _gcsSIGNAL
{
/* Pointer to gcoOS object. */
gcoOS os;
/* Signaled state. */
gctBOOL state;
/* Manual reset flag. */
gctBOOL manual;
/* Mutex. */
pthread_mutex_t mutex;
/* Condition. */
pthread_cond_t condition;
/* Number of signals pending in the command queue. */
gctINT pending;
/* Number of signals received. */
gctINT received;
}
gcsSIGNAL;
#endif /* GC_HAL_COMMON_QNX_H_ */

435
drivers/staging/rk29/vivante/hal/os/qnx/kernel/gc_hal_kernel_debug.c Normal file
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/****************************************************************************
*
* Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
*
* The material in this file is confidential and contains trade secrets
* of Vivante Corporation. This is proprietary information owned by
* Vivante Corporation. No part of this work may be disclosed,
* reproduced, copied, transmitted, or used in any way for any purpose,
* without the express written permission of Vivante Corporation.
*
*****************************************************************************
*
* Auto-generated file on 10/12/2010. Do not edit!!!
*
*****************************************************************************/
#include "gc_hal_kernel_qnx.h"
#include <stdarg.h>
/*
gcdBUFFERED_OUTPUT
When set to non-zero, all output is collected into a buffer with the
specified size. Once the buffer gets full, or the token "$$FLUSH$$" has
been received, the debug buffer will be printed to the console.
*/
#define gcdBUFFERED_OUTPUT 0
/******************************************************************************\
******************************** Debug Variables *******************************
\******************************************************************************/
static gceSTATUS _lastError = gcvSTATUS_OK;
static gctUINT32 _debugLevel = gcvLEVEL_ERROR;
static gctUINT32 _debugZones = gcvZONE_NONE;
static gctINT _indent = 0;
static void
OutputDebugString(
IN gctCONST_STRING String
)
{
#if gcdBUFFERED_OUTPUT
static gctCHAR outputBuffer[gcdBUFFERED_OUTPUT];
static gctINT outputBufferIndex = 0;
gctINT n, i;
n = (String != gcvNULL) ? strlen(String) + 1 : 0;
if ((n == 0) || (outputBufferIndex + n > gcmSIZEOF(outputBuffer)))
{
for (i = 0; i < outputBufferIndex; i += strlen(outputBuffer + i) + 1)
{
printf(outputBuffer + i);
}
outputBufferIndex = 0;
}
if (n > 0)
{
memcpy(outputBuffer + outputBufferIndex, String, n);
outputBufferIndex += n;
}
#else
if (String != gcvNULL)
{
printf(String);
}
#endif
}
static void
_Print(
IN gctCONST_STRING Message,
IN va_list Arguments
)
{
char buffer[1024];
int i, n;
if (strcmp(Message, "$$FLUSH$$") == 0)
{
OutputDebugString(gcvNULL);
return;
}
if (strncmp(Message, "--", 2) == 0)
{
if (_indent == 0)
{
printf("ERROR: _indent=0\n");
}
_indent -= 2;
}
for (i = 0; i < _indent; ++i)
{
buffer[i] = ' ';
}
/* Print message to buffer. */
n = vsnprintf(buffer + i, sizeof(buffer) - i, Message, Arguments);
if ((n <= 0) || (buffer[i + n - 1] != '\n'))
{
/* Append new-line. */
strncat(buffer, "\n", sizeof(buffer));
}
/* Output to debugger. */
OutputDebugString(buffer);
if (strncmp(Message, "++", 2) == 0)
{
_indent += 2;
}
}
/******************************************************************************\
********************************* Debug Macros *********************************
\******************************************************************************/
#define _DEBUGPRINT(Message) \
{ \
va_list arguments; \
\
va_start(arguments, Message); \
_Print(Message, arguments); \
va_end(arguments); \
}
/******************************************************************************\
********************************** Debug Code **********************************
\******************************************************************************/
/*******************************************************************************
**
** gckOS_Print
**
** Send a message to the debugger.
**
** INPUT:
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_Print(
IN gctCONST_STRING Message,
...
)
{
_DEBUGPRINT(Message);
}
/*******************************************************************************
**
** gckOS_DebugTrace
**
** Send a leveled message to the debugger.
**
** INPUT:
**
** gctUINT32 Level
** Debug level of message.
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugTrace(
IN gctUINT32 Level,
IN gctCONST_STRING Message,
...
)
{
if (Level > _debugLevel)
{
return;
}
_DEBUGPRINT(Message);
}
/*******************************************************************************
**
** gckOS_DebugTraceZone
**
** Send a leveled and zoned message to the debugger.
**
** INPUT:
**
** gctUINT32 Level
** Debug level for message.
**
** gctUINT32 Zone
** Debug zone for message.
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugTraceZone(
IN gctUINT32 Level,
IN gctUINT32 Zone,
IN gctCONST_STRING Message,
...
)
{
if ((Level > _debugLevel) || !(Zone & _debugZones))
{
return;
}
_DEBUGPRINT(Message);
}
/*******************************************************************************
**
** gckOS_DebugBreak
**
** Break into the debugger.
**
** INPUT:
**
** Nothing.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugBreak(
void
)
{
gckOS_DebugTrace(gcvLEVEL_ERROR, "gckOS_DebugBreak");
}
/*******************************************************************************
**
** gckOS_DebugFatal
**
** Send a message to the debugger and break into the debugger.
**
** INPUT:
**
** gctCONST_STRING Message
** Pointer to message.
**
** ...
** Optional arguments.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_DebugFatal(
IN gctCONST_STRING Message,
...
)
{
_DEBUGPRINT(Message);
/* Break into the debugger. */
gckOS_DebugBreak();
}
/*******************************************************************************
**
** gckOS_SetDebugLevel
**
** Set the debug level.
**
** INPUT:
**
** gctUINT32 Level
** New debug level.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugLevel(
IN gctUINT32 Level
)
{
_debugLevel = Level;
}
/*******************************************************************************
**
** gckOS_SetDebugZone
**
** Set the debug zone.
**
** INPUT:
**
** gctUINT32 Zone
** New debug zone.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugZone(
IN gctUINT32 Zone
)
{
_debugZones = Zone;
}
/*******************************************************************************
**
** gckOS_SetDebugLevelZone
**
** Set the debug level and zone.
**
** INPUT:
**
** gctUINT32 Level
** New debug level.
**
** gctUINT32 Zone
** New debug zone.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugLevelZone(
IN gctUINT32 Level,
IN gctUINT32 Zone
)
{
_debugLevel = Level;
_debugZones = Zone;
}
/*******************************************************************************
**
** gckOS_SetDebugZones
**
** Enable or disable debug zones.
**
** INPUT:
**
** gctUINT32 Zones
** Debug zones to enable or disable.
**
** gctBOOL Enable
** Set to gcvTRUE to enable the zones (or the Zones with the current
** zones) or gcvFALSE to disable the specified Zones.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_SetDebugZones(
IN gctUINT32 Zones,
IN gctBOOL Enable
)
{
if (Enable)
{
/* Enable the zones. */
_debugZones |= Zones;
}
else
{
/* Disable the zones. */
_debugZones &= ~Zones;
}
}
/*******************************************************************************
**
** gckOS_Verify
**
** Called to verify the result of a function call.
**
** INPUT:
**
** gceSTATUS Status
** Function call result.
**
** OUTPUT:
**
** Nothing.
*/
void
gckOS_Verify(
IN gceSTATUS Status
)
{
_lastError = Status;
}

812
drivers/staging/rk29/vivante/hal/os/qnx/kernel/gc_hal_kernel_device.c Normal file
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@ -0,0 +1,812 @@
/****************************************************************************
*
* Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
*
* The material in this file is confidential and contains trade secrets
* of Vivante Corporation. This is proprietary information owned by
* Vivante Corporation. No part of this work may be disclosed,
* reproduced, copied, transmitted, or used in any way for any purpose,
* without the express written permission of Vivante Corporation.
*
*****************************************************************************
*
* Auto-generated file on 10/12/2010. Do not edit!!!
*
*****************************************************************************/
#include "gc_hal_kernel_qnx.h"
#include <sys/mman.h>
#include <sys/siginfo.h>
#define _GC_OBJ_ZONE gcvZONE_DEVICE
/******************************************************************************\
******************************** gckGALDEVICE Code *******************************
\******************************************************************************/
gceSTATUS
gckGALDEVICE_AllocateMemory(
IN gckGALDEVICE Device,
IN gctSIZE_T Bytes,
OUT gctPOINTER *Logical,
OUT gctPHYS_ADDR *Physical,
OUT gctUINT32 *PhysAddr
)
{
gceSTATUS status;
gcmkVERIFY_ARGUMENT(Device != NULL);
gcmkVERIFY_ARGUMENT(Logical != NULL);
gcmkVERIFY_ARGUMENT(Physical != NULL);
gcmkVERIFY_ARGUMENT(PhysAddr != NULL);
status = gckOS_AllocateContiguous(Device->os,
gcvFALSE,
&Bytes,
Physical,
Logical);
if (gcmIS_ERROR(status))
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"gckGALDEVICE_AllocateMemory: error status->0x%x",
status);
return status;
}
*PhysAddr = (gctUINT32)(*(off_t*) Physical) - Device->baseAddress;
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"gckGALDEVICE_AllocateMemory: phys_addr->0x%x phsical->0x%x Logical->0x%x",
(gctUINT32)*Physical,
(gctUINT32)*PhysAddr,
(gctUINT32)*Logical);
/* Success. */
return gcvSTATUS_OK;
}
gceSTATUS
gckGALDEVICE_FreeMemory(
IN gckGALDEVICE Device,
IN gctPOINTER Logical,
IN gctPHYS_ADDR Physical)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
return gckOS_FreeContiguous(Device->os,
Physical,
Logical,
0);
}
/* TODO. fix global sigevent to be part of device. */
struct sigevent irqEvent;
const struct sigevent* isrRoutine(void* arg, int id)
{
gckGALDEVICE device = (gckGALDEVICE)arg;
/* Call kernel interrupt notification. */
if (gckKERNEL_Notify(device->kernel,
gcvNOTIFY_INTERRUPT,
gcvTRUE) == gcvSTATUS_OK)
{
InterruptUnmask(device->irqLine, device->irqId);
return &irqEvent;
}
return gcvNULL;
}
static void* threadRoutine(void *ctxt)
{
gckGALDEVICE device = (gckGALDEVICE) ctxt;
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"Starting ISR Thread with irq:%d\n",
device->irqLine);
SIGEV_INTR_INIT(&irqEvent);
/* Obtain I/O privileges */
ThreadCtl( _NTO_TCTL_IO, 0 );
device->irqId = InterruptAttach(device->irqLine,
isrRoutine,
(void*)device,
gcmSIZEOF(struct _gckGALDEVICE),
0);
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"irqId:%d\n",
device->irqId);
if (device->irqId < 0) {
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Setup_ISR: "
"Could not register irq line->%d\n",
device->irqLine);
device->isrInitialized = gcvFALSE;
return (void *)1;
}
printf("[Interrupt] Attached irqLine %d with id %d.\n",
device->irqLine, device->irqId);
device->isrInitialized = gcvTRUE;
while (1)
{
if (InterruptWait(0, NULL) == -1)
{
printf("[Interrupt] IST exiting\n");
/* Either something is wrong or the thread got canceled */
InterruptUnmask(device->irqLine, device->irqId);
pthread_exit(NULL);
}
gckKERNEL_Notify(device->kernel, gcvNOTIFY_INTERRUPT, gcvFALSE);
}
return (void *)0;
}
/*******************************************************************************
**
** gckGALDEVICE_Setup_ISR
**
** Start the ISR routine.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** gcvSTATUS_OK
** Setup successfully.
** gcvSTATUS_GENERIC_IO
** Setup failed.
*/
gceSTATUS
gckGALDEVICE_Setup_ISR(
IN gckGALDEVICE Device
)
{
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Release_ISR
**
** Release the irq line.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Release_ISR(
IN gckGALDEVICE Device
)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
return gcvSTATUS_OK;
}
int
gsl_free_interrupts()
{
return 0;
}
/*******************************************************************************
**
** gckGALDEVICE_Start_Thread
**
** Start the daemon thread.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** gcvSTATUS_OK
** Start successfully.
** gcvSTATUS_GENERIC_IO
** Start failed.
*/
gceSTATUS
gckGALDEVICE_Start_Thread(
IN gckGALDEVICE Device
)
{
pthread_attr_t attr;
struct sched_param sched;
gctINT ret;
gcmkVERIFY_ARGUMENT(Device != NULL);
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Start_Thread: Creating threadRoutine\n");
pthread_attr_init(&attr);
pthread_attr_getschedparam(&attr, &sched);
sched.sched_priority += 10;
pthread_attr_setschedparam(&attr, &sched);
pthread_attr_setinheritsched(&attr, PTHREAD_EXPLICIT_SCHED);
/* Start the interrupt service thread */
if ((ret = pthread_create(&Device->threadCtxt, &attr, threadRoutine, Device)) != 0)
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Start_Thread: Failed with code %d\n",
ret);
return gcvSTATUS_OUT_OF_RESOURCES;
}
pthread_setname_np(Device->threadCtxt, "galcore-IST");
Device->threadInitialized = gcvTRUE;
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Start_Thread: "
"Start the daemon thread.\n");
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Stop_Thread
**
** Stop the gal device, including the following actions: stop the daemon
** thread, release the irq.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Stop_Thread(
gckGALDEVICE Device
)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
/* stop the thread */
if (Device->threadInitialized)
{
InterruptDetach(Device->irqId);
Device->irqId = 0;
ConnectDetach(Device->coid);
Device->coid = 0;
ChannelDestroy(Device->chid);
Device->chid = 0;
pthread_cancel(Device->threadCtxt);
pthread_join(Device->threadCtxt, NULL);
Device->threadCtxt = 0;
Device->threadInitialized = gcvFALSE;
Device->isrInitialized = gcvFALSE;
}
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Start
**
** Start the gal device, including the following actions: setup the isr routine
** and start the daemon thread.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** gcvSTATUS_OK
** Start successfully.
*/
gceSTATUS
gckGALDEVICE_Start(
IN gckGALDEVICE Device
)
{
gceSTATUS ret;
/* Start the daemon thread. */
gcmkVERIFY_OK((ret = gckGALDEVICE_Start_Thread(Device)));
return ret;
}
/*******************************************************************************
**
** gckGALDEVICE_Stop
**
** Stop the gal device, including the following actions: stop the daemon
** thread, release the irq.
**
** INPUT:
**
** gckGALDEVICE Device
** Pointer to an gckGALDEVICE object.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Stop(
gckGALDEVICE Device
)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
if (Device->threadInitialized)
{
gckGALDEVICE_Stop_Thread(Device);
}
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckGALDEVICE_Construct
**
** Constructor.
**
** INPUT:
**
** OUTPUT:
**
** gckGALDEVICE * Device
** Pointer to a variable receiving the gckGALDEVICE object pointer on
** success.
*/
gceSTATUS
gckGALDEVICE_Construct(
IN gctINT IrqLine,
IN gctUINT32 RegisterMemBase,
IN gctSIZE_T RegisterMemSize,
IN gctUINT32 ContiguousBase,
IN gctSIZE_T ContiguousSize,
IN gctSIZE_T BankSize,
IN gctINT FastClear,
IN gctINT Compression,
IN gctUINT32 BaseAddress,
OUT gckGALDEVICE *Device
)
{
gctUINT32 internalBaseAddress, internalAlignment;
gctUINT32 externalBaseAddress, externalAlignment;
gctUINT32 horizontalTileSize, verticalTileSize;
gctUINT32 physAddr;
gctUINT32 physical;
gckGALDEVICE device;
gceSTATUS status;
gcmkTRACE(gcvLEVEL_VERBOSE, "[galcore] Enter gckGALDEVICE_Construct\n");
/* Allocate device structure. */
device = calloc(1, sizeof(struct _gckGALDEVICE));
if (!device)
{
gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Can't allocate memory.\n");
return gcvSTATUS_OUT_OF_MEMORY;
}
physical = RegisterMemBase;
/* Set up register memory region */
if (physical != 0)
{
/* Request a region. */
device->registerBase = (gctPOINTER)mmap_device_io(RegisterMemSize, RegisterMemBase);
if ((uintptr_t)device->registerBase == MAP_DEVICE_FAILED)
{
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Unable to map location->0x%lX for size->%ld\n",
RegisterMemBase,
RegisterMemSize);
return gcvSTATUS_OUT_OF_RESOURCES;
}
physical += RegisterMemSize;
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: "
"RegisterBase after mapping Address->0x%x is 0x%x\n",
(gctUINT32)RegisterMemBase,
(gctUINT32)device->registerBase);
}
/* construct the gckOS object */
device->baseAddress = BaseAddress;
gcmkONERROR(
gckOS_Construct(device, &device->os));
/* construct the gckKERNEL object. */
gcmkONERROR(
gckKERNEL_Construct(device->os, device, &device->kernel));
gcmkONERROR(
gckHARDWARE_SetFastClear(device->kernel->hardware,
FastClear,
Compression));
/* query the ceiling of the system memory */
gcmkONERROR(
gckHARDWARE_QuerySystemMemory(device->kernel->hardware,
&device->systemMemorySize,
&device->systemMemoryBaseAddress));
gcmkTRACE_ZONE(gcvLEVEL_INFO,
gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: "
"Will be trying to allocate contiguous memory of 0x%x bytes\n",
(gctUINT32)device->systemMemoryBaseAddress);
#if COMMAND_PROCESSOR_VERSION == 1
/* start the command queue */
gcmkVERIFY_OK(gckCOMMAND_Start(device->kernel->command));
#endif
/* initialize the thread daemon */
memset(&device->isrLock, 0, sizeof(device->isrLock));
device->threadInitialized = gcvFALSE;
device->killThread = gcvFALSE;
/* initialize the isr */
device->isrInitialized = gcvFALSE;
device->dataReady = gcvFALSE;
device->irqLine = IrqLine;
/* query the amount of video memory */
gcmkVERIFY_OK(gckHARDWARE_QueryMemory(device->kernel->hardware,
&device->internalSize,
&internalBaseAddress,
&internalAlignment,
&device->externalSize,
&externalBaseAddress,
&externalAlignment,
&horizontalTileSize,
&verticalTileSize));
/* set up the internal memory region */
if (device->internalSize > 0)
{
gceSTATUS status = gckVIDMEM_Construct(device->os,
internalBaseAddress,
device->internalSize,
internalAlignment,
0,
&device->internalVidMem);
if (gcmIS_ERROR(status))
{
/* error, remove internal heap */
device->internalSize = 0;
}
else
{
/* map internal memory */
device->internalPhysical = (gctPHYS_ADDR)physical;
device->internalLogical = (gctPOINTER)mmap_device_io(device->internalSize, physical);
gcmkASSERT(device->internalLogical != NULL);
physical += device->internalSize;
}
}
if (device->externalSize > 0)
{
/* create the external memory heap */
gceSTATUS status = gckVIDMEM_Construct(device->os,
externalBaseAddress,
device->externalSize,
externalAlignment,
0,
&device->externalVidMem);
if (gcmIS_ERROR(status))
{
/* error, remove internal heap */
device->externalSize = 0;
}
else
{
/* map internal memory */
device->externalPhysical = (gctPHYS_ADDR)physical;
device->externalLogical = (gctPOINTER)mmap_device_io(device->externalSize, physical);
gcmkASSERT(device->externalLogical != NULL);
physical += device->externalSize;
}
}
/* set up the contiguous memory */
device->contiguousSize = ContiguousSize;
if (ContiguousBase == 0)
{
status = gcvSTATUS_OUT_OF_MEMORY;
while (device->contiguousSize > 0)
{
gcmkTRACE_ZONE(
gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Will be trying to allocate contiguous memory of %ld bytes\n",
device->contiguousSize
);
/* allocate contiguous memory */
status = gckGALDEVICE_AllocateMemory(
device,
device->contiguousSize,
&device->contiguousBase,
&device->contiguousPhysical,
&physAddr
);
if (gcmIS_SUCCESS(status))
{
gcmkTRACE_ZONE(
gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Contiguous allocated size->0x%08X Virt->0x%08lX physAddr->0x%08X\n",
device->contiguousSize,
device->contiguousBase,
physAddr
);
status = gckVIDMEM_Construct(
device->os,
physAddr | device->systemMemoryBaseAddress,
device->contiguousSize,
64,
BankSize,
&device->contiguousVidMem
);
if (gcmIS_SUCCESS(status))
{
device->contiguousMapped = gcvFALSE;
/* success, abort loop */
gcmkTRACE_ZONE(
gcvLEVEL_INFO, gcvZONE_DRIVER,
"Using %u bytes of contiguous memory.\n",
device->contiguousSize
);
break;
}
gcmkVERIFY_OK(gckGALDEVICE_FreeMemory(
device,
device->contiguousBase,
device->contiguousPhysical
));
device->contiguousBase = NULL;
}
device->contiguousSize -= (4 << 20);
}
}
else
{
/* Create the contiguous memory heap. */
status = gckVIDMEM_Construct(
device->os,
(ContiguousBase - device->baseAddress) | device->systemMemoryBaseAddress,
ContiguousSize,
64,
BankSize,
&device->contiguousVidMem
);
if (gcmIS_ERROR(status))
{
/* Error, roll back. */
device->contiguousVidMem = gcvNULL;
device->contiguousSize = 0;
}
else
{
/* Map the contiguous memory. */
device->contiguousPhysical = (gctPHYS_ADDR) ContiguousBase;
device->contiguousSize = ContiguousSize;
device->contiguousBase = (gctPOINTER) mmap_device_io(ContiguousSize, ContiguousBase);
device->contiguousMapped = gcvTRUE;
if (device->contiguousBase == gcvNULL)
{
/* Error, roll back. */
gcmkVERIFY_OK(gckVIDMEM_Destroy(device->contiguousVidMem));
device->contiguousVidMem = gcvNULL;
device->contiguousSize = 0;
status = gcvSTATUS_OUT_OF_RESOURCES;
}
}
}
*Device = device;
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Construct: Initialized device->0x%x contiguous->%lu @ 0x%x (0x%08X)\n",
device,
device->contiguousSize,
device->contiguousBase,
device->contiguousPhysical);
return gcvSTATUS_OK;
OnError:
/* Roll back. */
/* Destroy the gckKERNEL object. */
if ( Device != gcvNULL)
{
gcmkVERIFY_OK(gckGALDEVICE_Destroy(*Device));
}
/* Return the status. */
return status;
}
/*******************************************************************************
**
** gckGALDEVICE_Destroy
**
** Class destructor.
**
** INPUT:
**
** Nothing.
**
** OUTPUT:
**
** Nothing.
**
** RETURNS:
**
** Nothing.
*/
gceSTATUS
gckGALDEVICE_Destroy(
gckGALDEVICE Device)
{
gcmkVERIFY_ARGUMENT(Device != NULL);
gcmkTRACE(gcvLEVEL_VERBOSE, "[ENTER] gckGALDEVICE_Destroy\n");
/* Destroy the gckKERNEL object. */
gcmkVERIFY_OK(gckKERNEL_Destroy(Device->kernel));
if (Device->internalVidMem != gcvNULL)
{
/* destroy the internal heap */
gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->internalVidMem));
/* unmap the internal memory */
munmap_device_io((uintptr_t)Device->internalLogical, Device->internalSize);
}
if (Device->externalVidMem != gcvNULL)
{
/* destroy the internal heap */
gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->externalVidMem));
/* unmap the external memory */
munmap_device_io((uintptr_t)Device->externalLogical, Device->externalSize);
}
if (Device->contiguousVidMem != gcvNULL)
{
/* Destroy the contiguous heap */
gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->contiguousVidMem));
if (Device->contiguousMapped)
{
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Destroy: "
"Unmapping contiguous memory->0x%08lX\n",
Device->contiguousBase);
munmap_device_io((uintptr_t)Device->contiguousBase, Device->contiguousSize);
}
else
{
gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
"[galcore] gckGALDEVICE_Destroy: "
"Freeing contiguous memory->0x%08lX\n",
Device->contiguousBase);
gcmkVERIFY_OK(gckGALDEVICE_FreeMemory(Device,
Device->contiguousBase,
Device->contiguousPhysical));
}
}
if (Device->registerBase)
{
munmap_device_io((uintptr_t)Device->registerBase, Device->registerSize);
}
/* Destroy the gckOS object. */
gcmkVERIFY_OK(gckOS_Destroy(Device->os));
free(Device);
gcmkTRACE(gcvLEVEL_VERBOSE, "[galcore] Leave gckGALDEVICE_Destroy\n");
return gcvSTATUS_OK;
}

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/****************************************************************************
*
* Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
*
* The material in this file is confidential and contains trade secrets
* of Vivante Corporation. This is proprietary information owned by
* Vivante Corporation. No part of this work may be disclosed,
* reproduced, copied, transmitted, or used in any way for any purpose,
* without the express written permission of Vivante Corporation.
*
*****************************************************************************
*
* Auto-generated file on 10/12/2010. Do not edit!!!
*
*****************************************************************************/
#ifndef __gc_hal_kernel_device_h_
#define __gc_hal_kernel_device_h_
/******************************************************************************\
******************************* gckGALDEVICE Structure *******************************
\******************************************************************************/
#define GALCORE_INTERRUPT_PULSE 0x5D
typedef struct _gckGALDEVICE
{
/* Objects. */
gckOS os;
gckKERNEL kernel;
/* Attributes. */
gctSIZE_T internalSize;
gctPHYS_ADDR internalPhysical;
gctPOINTER internalLogical;
gckVIDMEM internalVidMem;
gctSIZE_T externalSize;
gctPHYS_ADDR externalPhysical;
gctPOINTER externalLogical;
gckVIDMEM externalVidMem;
gckVIDMEM contiguousVidMem;
gctPOINTER contiguousBase;
gctPHYS_ADDR contiguousPhysical;
gctSIZE_T contiguousSize;
gctBOOL contiguousMapped;
gctPOINTER contiguousMappedUser;
gctSIZE_T systemMemorySize;
gctUINT32 systemMemoryBaseAddress;
gctPOINTER registerBase;
gctSIZE_T registerSize;
gctUINT32 baseAddress;
/* IRQ management. */
gctINT irqLine;
gctINT irqId;
gctBOOL isrInitialized;
gctBOOL dataReady;
intrspin_t isrLock;
struct sigevent event;
int chid;
int coid;
/* Thread management. */
pthread_t threadCtxt;
gctBOOL threadInitialized;
gctBOOL killThread;
}
* gckGALDEVICE;
typedef struct _gcsHAL_PRIVATE_DATA
{
gckGALDEVICE device;
gctPOINTER mappedMemory;
gctPOINTER contiguousLogical;
}
gcsHAL_PRIVATE_DATA, * gcsHAL_PRIVATE_DATA_PTR;
gceSTATUS gckGALDEVICE_Setup_ISR(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Release_ISR(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Start_Thread(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Stop_Thread(
gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Start(
IN gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Stop(
gckGALDEVICE Device
);
gceSTATUS gckGALDEVICE_Construct(
IN gctINT IrqLine,
IN gctUINT32 RegisterMemBase,
IN gctSIZE_T RegisterMemSize,
IN gctUINT32 ContiguousBase,
IN gctSIZE_T ContiguousSize,
IN gctSIZE_T BankSize,
IN gctINT FastClear,
IN gctINT Compression,
IN gctUINT32 BaseAddress,
OUT gckGALDEVICE *Device
);
gceSTATUS gckGALDEVICE_Destroy(
IN gckGALDEVICE Device
);
#endif /* __gc_hal_kernel_device_h_ */

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/****************************************************************************
*
* Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
*
* The material in this file is confidential and contains trade secrets
* of Vivante Corporation. This is proprietary information owned by
* Vivante Corporation. No part of this work may be disclosed,
* reproduced, copied, transmitted, or used in any way for any purpose,
* without the express written permission of Vivante Corporation.
*
*****************************************************************************
*
* Auto-generated file on 10/12/2010. Do not edit!!!
*
*****************************************************************************/
/*
* Os.h
*
* Created on: Feb 2, 2010
* Author: Tarang Vaish
*/
#ifndef __gc_hal_kernel_os_h_
#define __gc_hal_kernel_os_h_
typedef struct
{
io_msg_t iomsg;
gcsHAL_INTERFACE iface;
} gcsDRIVER_ARGS;
struct _gckPAGE_USAGE
{
gctUINT16 pageCount;
};
struct _gckSHM_POOL
{
gctHANDLE Handle;
gctINT32 fd;
gctUINT32 pid;
gctUINT32 freePage;
gctUINT32 pageCount;
gctUINT32 pageSize;
pthread_mutex_t mutex;
gctUINT32 Logical;
gctUINT32 Physical;
struct _gckPAGE_USAGE* pageUsage;
struct _gckSHM_POOL* nextPool;
};
typedef struct _gckSHM_POOL* gckSHM_POOL;
typedef struct _gckPAGE_USAGE* gckPAGE_USAGE;
gceSTATUS
drv_mempool_init();
void
drv_mempool_destroy();
void
drv_mempool_alloc_contiguous(
IN gctUINT32 Bytes,
OUT gctPHYS_ADDR * Physical,
OUT gctPOINTER * Logical
);
int
drv_mempool_free(
IN gctPOINTER Logical
);
gctUINT32
drv_mempool_get_baseAddress();
gctUINT32
drv_mempool_get_basePAddress();
gctUINT32
drv_mempool_get_page_size();
gctINT
drv_mempool_get_fileDescriptor();
gceSTATUS
drv_mempool_mem_offset(
IN gctPOINTER Logical,
OUT gctUINT32 * Address);
/* Shared memory pool functions. */
gckSHM_POOL drv_shmpool_create(
IN gctUINT32 Pid,
IN gctHANDLE Handle,
IN gctUINT32 PoolSize,
IN gctUINT32 PageSize);
void
drv_shmpool_destroy(
IN gckSHM_POOL ShmPool);
gckSHM_POOL
drv_shm_acquire_pool(
IN gctUINT32 Pid,
IN gctHANDLE Handle
);
gckSHM_POOL
drv_shm_acquire_pool2(
IN gctPOINTER Logical
);
gceSTATUS
drv_shm_remove_pool(
IN gctHANDLE Handle
);
gctUINT32
drv_shmpool_get_BaseAddress(
IN gckSHM_POOL ShmPool
);
gctUINT32
drv_shmpool_get_page_size(
IN gckSHM_POOL ShmPool
);
gceSTATUS
drv_shmpool_mem_offset(
IN gctPOINTER Logical,
OUT gctUINT32 * Address);
gctPOINTER
drv_shmpool_alloc_contiguous(
IN gctUINT32 Pid,
IN gctHANDLE Handle,
IN gctUINT32 Bytes
);
gctUINT32
drv_shmpool_free(
IN gctPOINTER Logical
);
void *
mmap64_join(pid_t pid, void *addr, size_t len, int prot, int flags, int fd, off64_t off);
int
mem_offset64_peer(pid_t pid, const uintptr_t addr, size_t len,
off64_t *offset, size_t *contig_len);
int
munmap_peer(pid_t pid, void *addr, size_t len);
void *
mmap64_peer(pid_t pid, void *addr, size_t len, int prot, int flags, int fd, off64_t off);
#endif /* __gc_hal_kernel_os_h_ */

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/****************************************************************************
*
* Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
*
* The material in this file is confidential and contains trade secrets
* of Vivante Corporation. This is proprietary information owned by
* Vivante Corporation. No part of this work may be disclosed,
* reproduced, copied, transmitted, or used in any way for any purpose,
* without the express written permission of Vivante Corporation.
*
*****************************************************************************
*
* Auto-generated file on 10/12/2010. Do not edit!!!
*
*****************************************************************************/
#include "gc_hal_kernel_qnx.h"
#define _GC_OBJ_ZONE gcvZONE_KERNEL
/******************************************************************************\
******************************* gckKERNEL API Code ******************************
\******************************************************************************/
/*******************************************************************************
**
** gckKERNEL_QueryVideoMemory
**
** Query the amount of video memory.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** OUTPUT:
**
** gcsHAL_INTERFACE * Interface
** Pointer to an gcsHAL_INTERFACE structure that will be filled in with
** the memory information.
*/
gceSTATUS
gckKERNEL_QueryVideoMemory(
IN gckKERNEL Kernel,
OUT gcsHAL_INTERFACE * Interface
)
{
gckGALDEVICE device;
gcmkHEADER_ARG("Kernel=0x%x", Kernel);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(Interface != NULL);
/* Extract the pointer to the gckGALDEVICE class. */
device = (gckGALDEVICE) Kernel->context;
/* Get internal memory size and physical address. */
Interface->u.QueryVideoMemory.internalSize = device->internalSize;
Interface->u.QueryVideoMemory.internalPhysical = device->internalPhysical;
/* Get external memory size and physical address. */
Interface->u.QueryVideoMemory.externalSize = device->externalSize;
Interface->u.QueryVideoMemory.externalPhysical = device->externalPhysical;
/* Get contiguous memory size and physical address. */
Interface->u.QueryVideoMemory.contiguousSize = device->contiguousSize;
Interface->u.QueryVideoMemory.contiguousPhysical = device->contiguousPhysical;
/* Success. */
gcmkFOOTER_NO();
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckKERNEL_GetVideoMemoryPool
**
** Get the gckVIDMEM object belonging to the specified pool.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gcePOOL Pool
** Pool to query gckVIDMEM object for.
**
** OUTPUT:
**
** gckVIDMEM * VideoMemory
** Pointer to a variable that will hold the pointer to the gckVIDMEM
** object belonging to the requested pool.
*/
gceSTATUS
gckKERNEL_GetVideoMemoryPool(
IN gckKERNEL Kernel,
IN gcePOOL Pool,
OUT gckVIDMEM * VideoMemory
)
{
gckGALDEVICE device;
gckVIDMEM videoMemory;
gcmkHEADER_ARG("Kernel=0x%x Pool=0x%x", Kernel, Pool);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(VideoMemory != NULL);
/* Extract the pointer to the gckGALDEVICE class. */
device = (gckGALDEVICE) Kernel->context;
/* Dispatch on pool. */
switch (Pool)
{
case gcvPOOL_LOCAL_INTERNAL:
/* Internal memory. */
videoMemory = device->internalVidMem;
break;
case gcvPOOL_LOCAL_EXTERNAL:
/* External memory. */
videoMemory = device->externalVidMem;
break;
case gcvPOOL_SYSTEM:
/* System memory. */
videoMemory = device->contiguousVidMem;
break;
default:
/* Unknown pool. */
videoMemory = NULL;
}
/* Return pointer to the gckVIDMEM object. */
*VideoMemory = videoMemory;
/* Return status. */
gcmkFOOTER_ARG("*VideoMemory=0x%x", *VideoMemory);
return (videoMemory == NULL) ? gcvSTATUS_OUT_OF_MEMORY : gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckKERNEL_MapMemory
**
** Map video memory into the current process space.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctPHYS_ADDR Physical
** Physical address of video memory to map.
**
** gctSIZE_T Bytes
** Number of bytes to map.
**
** OUTPUT:
**
** gctPOINTER * Logical
** Pointer to a variable that will hold the base address of the mapped
** memory region.
*/
gceSTATUS
gckKERNEL_MapMemory(
IN gckKERNEL Kernel,
IN gctPHYS_ADDR Physical,
IN gctSIZE_T Bytes,
OUT gctPOINTER * Logical
)
{
return gckOS_MapMemory(Kernel->os, Physical, Bytes, Logical);
}
/*******************************************************************************
**
** gckKERNEL_UnmapMemory
**
** Unmap video memory from the current process space.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctPHYS_ADDR Physical
** Physical address of video memory to map.
**
** gctSIZE_T Bytes
** Number of bytes to map.
**
** gctPOINTER Logical
** Base address of the mapped memory region.
**
** OUTPUT:
**
** Nothing.
*/
gceSTATUS
gckKERNEL_UnmapMemory(
IN gckKERNEL Kernel,
IN gctPHYS_ADDR Physical,
IN gctSIZE_T Bytes,
IN gctPOINTER Logical
)
{
return gckOS_UnmapMemory(Kernel->os, Physical, Bytes, Logical);
}
/*******************************************************************************
**
** gckKERNEL_MapVideoMemory
**
** Map video memory for the current process.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctBOOL InUserSpace
** gcvTRUE to map the memory into the user space.
**
** gctUINT32 Address
** Hardware specific memory address.
**
** gctUINT32 Pid
** Process ID of the current process.
**
** gctUINT32 Bytes
** Number of bytes to map.
**
** OUTPUT:
**
** gctPOINTER * Logical
** Pointer to a variable that will hold the logical address of the
** specified memory address.
*/
gceSTATUS
gckKERNEL_MapVideoMemory(
IN gckKERNEL Kernel,
IN gctBOOL InUserSpace,
IN gctUINT32 Address,
IN gctUINT32 Pid,
IN gctUINT32 Bytes,
OUT gctPOINTER * Logical
)
{
off64_t offset = (off64_t)Address - (off64_t)drv_mempool_get_basePAddress();
gcmkHEADER_ARG("Kernel=0x%x InUserSpace=%d Address=%08x",
Kernel, InUserSpace, Address);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
*Logical = (gctPOINTER)mmap64_peer(Pid, gcvNULL, Bytes,
PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NOINIT,
drv_mempool_get_fileDescriptor(), offset);
if (*Logical == MAP_FAILED) {
*Logical = NULL;
return gcvSTATUS_INVALID_ADDRESS;
}
/* Success. */
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckKERNEL_UnmapVideoMemory
**
** Unmap video memory for the current process.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gctUINT32 Address
** Hardware specific memory address.
**
** gctUINT32 Pid
** Process ID of the current process.
**
** gctUINT32 Bytes
** Number of bytes to map.
**
** OUTPUT:
**
** Nothing.
*/
gceSTATUS
gckKERNEL_UnmapVideoMemory(
IN gckKERNEL Kernel,
IN gctPOINTER Logical,
IN gctUINT32 Pid,
IN gctUINT32 Bytes
)
{
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
if (munmap_peer(Pid, Logical, Bytes) == -1)
{
return gcvSTATUS_INVALID_ADDRESS;
}
/* Success. */
return gcvSTATUS_OK;
}
/*******************************************************************************
**
** gckKERNEL_Notify
**
** This function is called by clients to notify the gckKERNEL object of an event.
**
** INPUT:
**
** gckKERNEL Kernel
** Pointer to an gckKERNEL object.
**
** gceNOTIFY Notification
** Notification event.
**
** OUTPUT:
**
** Nothing.
*/
gceSTATUS
gckKERNEL_Notify(
IN gckKERNEL Kernel,
IN gceNOTIFY Notification,
IN gctBOOL Data
)
{
gceSTATUS status;
gcmkHEADER_ARG("Kernel=0x%x Notification=%d Data=%d",
Kernel, Notification, Data);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
/* Dispatch on notifcation. */
switch (Notification)
{
case gcvNOTIFY_INTERRUPT:
/* Process the interrupt. */
#if COMMAND_PROCESSOR_VERSION > 1
status = gckINTERRUPT_Notify(Kernel->interrupt, Data);
#else
status = gckHARDWARE_Interrupt(Kernel->hardware, Data);
#endif
break;
default:
status = gcvSTATUS_OK;
break;
}
/* Success. */
gcmkFOOTER();
return status;
}
gceSTATUS
gckKERNEL_QuerySettings(
IN gckKERNEL Kernel,
OUT gcsKERNEL_SETTINGS * Settings
)
{
gckGALDEVICE device;
gcmkHEADER_ARG("Kernel=0x%x", Kernel);
/* Verify the arguments. */
gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
gcmkVERIFY_ARGUMENT(Settings != gcvNULL);
/* Extract the pointer to the gckGALDEVICE class. */
device = (gckGALDEVICE) Kernel->context;
/* Fill in signal. */
Settings->signal = -1;
/* Success. */
gcmkFOOTER_ARG("Settings->signal=%d", Settings->signal);
return gcvSTATUS_OK;
}

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/****************************************************************************
*
* Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
*
* The material in this file is confidential and contains trade secrets
* of Vivante Corporation. This is proprietary information owned by
* Vivante Corporation. No part of this work may be disclosed,
* reproduced, copied, transmitted, or used in any way for any purpose,
* without the express written permission of Vivante Corporation.
*
*****************************************************************************
*
* Auto-generated file on 10/12/2010. Do not edit!!!
*
*****************************************************************************/
#ifndef __gc_hal_kernel_qnx_h_
#define __gc_hal_kernel_qnx_h_
#define _QNX_SOURCE
#include <errno.h>
#include <stdio.h>
#include <stddef.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <sys/iofunc.h>
#include <sys/dispatch.h>
#include <sys/procmgr.h>
#include <sys/memmsg.h>
#include <fcntl.h>
#include <sys/syspage.h>
#include <hw/inout.h>
#include <atomic.h>
#define NTSTRSAFE_NO_CCH_FUNCTIONS
#include "gc_hal.h"
#include "gc_hal_driver.h"
#include "gc_hal_kernel.h"
#include "gc_hal_kernel_device.h"
#include "gc_hal_kernel_os.h"
#include "../inc/gc_hal_common_qnx.h"
#define _WIDE(string) L##string
#define WIDE(string) _WIDE(string)
#define countof(a) (sizeof(a) / sizeof(a[0]))
#ifndef GAL_DEV
#define GAL_DEV "/dev/galcore"
#endif
#endif /* __gc_hal_kernel_qnx_h_ */

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##############################################################################
#
# Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
#
# The material in this file is confidential and contains trade secrets
# of Vivante Corporation. This is proprietary information owned by
# Vivante Corporation. No part of this work may be disclosed,
# reproduced, copied, transmitted, or used in any way for any purpose,
# without the express written permission of Vivante Corporation.
#
##############################################################################
#
# Auto-generated file on 10/12/2010. Do not edit!!!
#
##############################################################################
#
# Qnx build file for kernel HAL layer.
#
################################################################################
# Include common definitions.
include $(AQROOT)/makefile.linux.def
################################################################################
# Define a shortcut for the main target.
#ifeq ($(STATIC_LINK),1)
STATIC = 1
#else
DYNAMIC = 1
#endif
PROGRAM := 1
#ifeq ($(STATIC), 1)
TARGET_NAME = galcore.a
#else
TARGET_NAME = galcore
#endif
################################################################################
# Installation directory
INSTALL_DIR := $(SDK_DIR)/drivers
################################################################################
# Supply additional include directories.
INCLUDE += -I$(AQROOT)/hal/inc
INCLUDE += -I$(AQROOT)/hal/user
INCLUDE += -I$(AQROOT)/hal/kernel
INCLUDE += -I$(AQARCH)/hal/kernel
INCLUDE += -I$(AQARCH)/hal/kernel
CFLAGS += $(INCLUDE)
CFLAGS += -fPIC
################################################################################
# Supply necessary libraries.
# Specify Vivante library paths.
LIBS += -L $(AQARCH)/hal/kernel/$(OBJ_DIR)
LIBS += -L $(AQROOT)/hal/kernel/$(OBJ_DIR)
LIBS += -l halarchkernel -l halkernel
################################################################################
# Describe object files.
OBJECTS = \
$(OBJ_DIR)/gc_hal_kernel_driver.o \
$(OBJ_DIR)/gc_hal_kernel_os.o \
$(OBJ_DIR)/gc_hal_kernel_qnx.o \
$(OBJ_DIR)/gc_hal_kernel_device.o \
$(OBJ_DIR)/gc_hal_kernel_debug.o \
include $(AQROOT)/common.target

40
drivers/staging/rk29/vivante/hal/os/qnx/makefile.linux Normal file
View File

@ -0,0 +1,40 @@
##############################################################################
#
# Copyright (c) 2005 - 2010 by Vivante Corp. All rights reserved.
#
# The material in this file is confidential and contains trade secrets
# of Vivante Corporation. This is proprietary information owned by
# Vivante Corporation. No part of this work may be disclosed,
# reproduced, copied, transmitted, or used in any way for any purpose,
# without the express written permission of Vivante Corporation.
#
##############################################################################
#
# Auto-generated file on 10/12/2010. Do not edit!!!
#
##############################################################################
#
# QNX build file for the kernel level HAL libraries.
#
################################################################################
# Define make command.
MAKE = make --makefile=makefile.linux
################################################################################
# Define build directories.
HAL_KERNEL_DRV_ARCH := $(AQARCH)/hal/kernel
HAL_KERNEL_DRV_OS := $(AQROOT)/hal/os/qnx/kernel
HAL_KERNEL_DRV_MAIN := $(AQROOT)/hal/kernel
$(HAL_KERNEL_DRV_OS): $(HAL_KERNEL_DRV_ARCH) $(HAL_KERNEL_DRV_MAIN)
MODULES := $(HAL_KERNEL_DRV_ARCH) $(HAL_KERNEL_DRV_OS) $(HAL_KERNEL_DRV_MAIN)
MAIN_MODULE = $(HAL_KERNEL_DRV_OS)
include $(AQROOT)/common.node

170
drivers/staging/rk29/vivante/hal/user/gc_hal_user_context.h Normal file
View File

@ -0,0 +1,170 @@
/****************************************************************************
*
* Copyright (C) 2005 - 2010 by Vivante Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the license, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*****************************************************************************/
#ifndef __gc_hal_user_context_h_
#define __gc_hal_user_context_h_
#ifdef __cplusplus
extern "C" {
#endif
/* gcoCONTEXT structure that hold the current context. */
struct _gcoCONTEXT
{
/* Object. */
gcsOBJECT object;
/* Pointer to gcoOS object. */
gcoOS os;
/* Pointer to gcoHARDWARE object. */
gcoHARDWARE hardware;
/* Context ID. */
gctUINT64 id;
/* State mapping. */
gctUINT32_PTR map;
gctSIZE_T stateCount;
/* State hinting. */
gctUINT8_PTR hint;
gctUINT8 hintValue;
gctSIZE_T hintCount;
/* Context buffer. */
gctUINT32_PTR buffer;
gctUINT32 pipe3DIndex;
gctUINT32 pipe2DIndex;
gctUINT32 linkIndex;
gctUINT32 inUseIndex;
gctSIZE_T bufferSize;
/* Context buffer used for commitment. */
gctSIZE_T bytes;
gctPHYS_ADDR physical;
gctPOINTER logical;
/* Pointer to final LINK command. */
gctPOINTER link;
/* Requested pipe select for context. */
gctUINT32 initialPipe;
gctUINT32 entryPipe;
gctUINT32 currentPipe;
/* Flag to specify whether PostCommit needs to be called. */
gctBOOL postCommit;
/* Busy flag. */
volatile gctBOOL * inUse;
/* Variables used for building state buffer. */
gctUINT32 lastAddress;
gctSIZE_T lastSize;
gctUINT32 lastIndex;
gctBOOL lastFixed;
/* Hint array. */
gctUINT32_PTR hintArray;
gctUINT32_PTR hintIndex;
};
struct _gcoCMDBUF
{
/* The object. */
gcsOBJECT object;
/* Pointer to gcoOS object. */
gcoOS os;
/* Pointer to gcoHARDWARE object. */
gcoHARDWARE hardware;
/* Physical address of command buffer. */
gctPHYS_ADDR physical;
/* Logical address of command buffer. */
gctPOINTER logical;
/* Number of bytes in command buffer. */
gctSIZE_T bytes;
/* Start offset into the command buffer. */
gctUINT32 startOffset;
/* Current offset into the command buffer. */
gctUINT32 offset;
/* Number of free bytes in command buffer. */
gctSIZE_T free;
#if gcdSECURE_USER
/* Table of offsets that define the physical addresses to be mapped. */
gctUINT32_PTR hintTable;
/* Current index into map table. */
gctUINT32_PTR hintIndex;
/* Commit index for map table. */
gctUINT32_PTR hintCommit;
#endif
};
typedef struct _gcsQUEUE * gcsQUEUE_PTR;
typedef struct _gcsQUEUE
{
/* Pointer to next gcsQUEUE structure. */
gcsQUEUE_PTR next;
#ifdef __QNXNTO__
/* Size of this object. */
gctSIZE_T bytes;
#endif
/* Event information. */
gcsHAL_INTERFACE iface;
}
gcsQUEUE;
/* Event queue. */
struct _gcoQUEUE
{
/* The object. */
gcsOBJECT object;
/* Pointer to gcoOS object. */
gcoOS os;
/* Pointer to current event queue. */
gcsQUEUE_PTR head;
gcsQUEUE_PTR tail;
};
#ifdef __cplusplus
}
#endif
#endif /* __gc_hal_user_context_h_ */

52
drivers/video/Kconfig Normal file → Executable file
View File

@ -18,7 +18,7 @@ config VGASTATE
config VIDEO_OUTPUT_CONTROL
tristate "Lowlevel video output switch controls"
help
This framework adds support for low-level control of the video
This framework adds support for low-level control of the video
output switch.
menuconfig FB
@ -626,7 +626,7 @@ config FB_STI
BIOS routines contained in a ROM chip in HP PA-RISC based machines.
Enabling this option will implement the linux framebuffer device
using calls to the STI BIOS routines for initialisation.
If you enable this option, you will get a planar framebuffer device
/dev/fb which will work on the most common HP graphic cards of the
NGLE family, including the artist chips (in the 7xx and Bxxx series),
@ -1065,36 +1065,36 @@ config FB_I810
select FB_CFB_IMAGEBLIT
select VGASTATE
help
This driver supports the on-board graphics built in to the Intel 810
This driver supports the on-board graphics built in to the Intel 810
and 815 chipsets. Say Y if you have and plan to use such a board.
To compile this driver as a module, choose M here: the
module will be called i810fb.
For more information, please read
For more information, please read
<file:Documentation/fb/intel810.txt>
config FB_I810_GTF
bool "use VESA Generalized Timing Formula"
depends on FB_I810
help
If you say Y, then the VESA standard, Generalized Timing Formula
If you say Y, then the VESA standard, Generalized Timing Formula
or GTF, will be used to calculate the required video timing values
per video mode. Since the GTF allows nondiscrete timings
per video mode. Since the GTF allows nondiscrete timings
(nondiscrete being a range of values as opposed to discrete being a
set of values), you'll be able to use any combination of horizontal
set of values), you'll be able to use any combination of horizontal
and vertical resolutions, and vertical refresh rates without having
to specify your own timing parameters. This is especially useful
to maximize the performance of an aging display, or if you just
have a display with nonstandard dimensions. A VESA compliant
to maximize the performance of an aging display, or if you just
have a display with nonstandard dimensions. A VESA compliant
monitor is recommended, but can still work with non-compliant ones.
If you need or want this, then select this option. The timings may
not be compliant with Intel's recommended values. Use at your own
If you need or want this, then select this option. The timings may
not be compliant with Intel's recommended values. Use at your own
risk.
If you say N, the driver will revert to discrete video timings
If you say N, the driver will revert to discrete video timings
using a set recommended by Intel in their documentation.
If unsure, say N.
config FB_I810_I2C
@ -1212,10 +1212,10 @@ config FB_MATROX_G
G450/G550 secondary head and digital output are supported without
additional modules.
The driver starts in monitor mode. You must use the matroxset tool
(available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
swap primary and secondary head outputs, or to change output mode.
Secondary head driver always start in 640x480 resolution and you
The driver starts in monitor mode. You must use the matroxset tool
(available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
swap primary and secondary head outputs, or to change output mode.
Secondary head driver always start in 640x480 resolution and you
must use fbset to change it.
Do not forget that second head supports only 16 and 32 bpp
@ -1298,7 +1298,7 @@ config FB_RADEON_I2C
select FB_DDC
default y
help
Say Y here if you want DDC/I2C support for your Radeon board.
Say Y here if you want DDC/I2C support for your Radeon board.
config FB_RADEON_BACKLIGHT
bool "Support for backlight control"
@ -1498,7 +1498,7 @@ config FB_NEOMAGIC
select VGASTATE
help
This driver supports notebooks with NeoMagic PCI chips.
Say Y if you have such a graphics card.
Say Y if you have such a graphics card.
To compile this driver as a module, choose M here: the
module will be called neofb.
@ -1553,7 +1553,7 @@ config FB_VOODOO1
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
Voodoo2 (cvg) based graphics card.
To compile this driver as a module, choose M here: the
@ -1935,7 +1935,17 @@ config FB_RK2818
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for RK2818 Platform,select it if you using rk2818
config FB_RK29
tristate "RK29 lcd control"
depends on FB
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for RK29 Platform,select it if you using rk29
config FB_SM501
tristate "Silicon Motion SM501 framebuffer support"
depends on FB && MFD_SM501

1
drivers/video/Makefile Normal file → Executable file
View File

@ -121,6 +121,7 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
obj-$(CONFIG_FB_PS3) += ps3fb.o
obj-$(CONFIG_FB_RK2818) += rk2818_fb.o
obj-$(CONFIG_FB_RK29) += rk29_fb.o
obj-$(CONFIG_FB_SM501) += sm501fb.o
obj-$(CONFIG_FB_XILINX) += xilinxfb.o
obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o

6
drivers/video/display/screen/hdmi_anx7150.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -39,9 +39,9 @@ int anx7150_init(void);
int anx7150_standby(u8 enable);
void set_hdmi_info(struct rk28fb_screen *screen)
void set_hdmi_info(struct rk29fb_screen *screen)
{
struct rk28fb_screen *screen2 = screen + 1;
struct rk29fb_screen *screen2 = screen + 1;
/* ****************** 576p ******************* */
/* screen type & face */

6
drivers/video/display/screen/hdmi_null.c
View File

@ -1,14 +1,14 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
void set_hdmi_info(struct rk28fb_screen *screen)
void set_hdmi_info(struct rk29fb_screen *screen)
{
memset(screen, 0, sizeof(struct rk28fb_screen));
memset(screen, 0, sizeof(struct rk29fb_screen));
screen->face = OUT_P666;
}

4
drivers/video/display/screen/lcd_a060se02.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -117,7 +117,7 @@ int lcd_refresh(u8 arg)
void set_lcd_info(struct rk28fb_screen *screen)
void set_lcd_info(struct rk29fb_screen *screen)
{
/* screen type & face */
screen->type = OUT_TYPE;

14
drivers/video/display/screen/lcd_hl070vm4.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -13,7 +13,7 @@
/* Timing */
#define H_PW 10
#define H_BP 206
#define H_BP 206
#define H_VD 800
#define H_FP 40
@ -33,21 +33,21 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
#define DRVDelayUs(i) udelay(i*2)
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
@ -153,7 +153,7 @@ void spi_screenreg_set(u32 Data)
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
DRVDelayUs(2);
}

24
drivers/video/display/screen/lcd_hsd800x480.c
View File

@ -1,7 +1,7 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -35,21 +35,21 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
#define DRVDelayUs(i) udelay(i*2)
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
@ -83,12 +83,12 @@ void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->init = NULL;
screen->standby = standby;
if(lcd_info)
gLcd_info = lcd_info;
}
//cannot need init,so set screen->init = null at rk28_fb.c file
//cannot need init,so set screen->init = null at rk29_fb.c file
void spi_screenreg_set(u32 Addr, u32 Data)
{
@ -218,19 +218,19 @@ int standby(u8 enable)
if(gLcd_info)
gLcd_info->io_deinit();
#else
GPIOSetPinDirection(GPIOPortB_Pin3, GPIO_OUT);
GPIOSetPinDirection(GPIOPortB_Pin2, GPIO_OUT);
if(enable)
{
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_HIGH);
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_HIGH);
}
else
{
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_LOW);
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_LOW);
}
#endif
return 0;

316
drivers/video/display/screen/lcd_hx8357.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -15,7 +15,7 @@
/* Timing */
#define H_PW 8
#define H_BP 6
#define H_VD 320 //***800
#define H_VD 320 //***800
#define H_FP 60
#define V_PW 12
@ -24,10 +24,10 @@
#define V_FP 40
/* Other */
#define DCLK_POL 0
#define DCLK_POL 0
#define SWAP_RB 0
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
int init(void);
int standby(u8 enable);
@ -39,10 +39,10 @@ int standby(u8 enable);
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
@ -52,41 +52,41 @@ static void screen_set_iomux(u8 enable)
int ret=-1;
if(enable)
{
rk2818_mux_api_set(GPIOH6_IQ_SEL_NAME, 0);
ret = gpio_request(RK2818_PIN_PH6, NULL);
rk29_mux_api_set(GPIOH6_IQ_SEL_NAME, 0);
ret = gpio_request(RK29_PIN_PH6, NULL);
if(0)//(ret != 0)
{
gpio_free(RK2818_PIN_PH6);
printk(">>>>>> lcd cs gpio_request err \n ");
gpio_free(RK29_PIN_PH6);
printk(">>>>>> lcd cs gpio_request err \n ");
goto pin_err;
}
rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, 1);
}
ret = gpio_request(RK2818_PIN_PE5, NULL);
rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 1);
ret = gpio_request(RK29_PIN_PE5, NULL);
if(0)//(ret != 0)
{
gpio_free(RK2818_PIN_PE5);
printk(">>>>>> lcd clk gpio_request err \n ");
gpio_free(RK29_PIN_PE5);
printk(">>>>>> lcd clk gpio_request err \n ");
goto pin_err;
}
ret = gpio_request(RK2818_PIN_PE4, NULL);
}
ret = gpio_request(RK29_PIN_PE4, NULL);
if(0)//(ret != 0)
{
gpio_free(RK2818_PIN_PE4);
printk(">>>>>> lcd txd gpio_request err \n ");
gpio_free(RK29_PIN_PE4);
printk(">>>>>> lcd txd gpio_request err \n ");
goto pin_err;
}
}
}
else
{
gpio_free(RK2818_PIN_PH6);
// rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1);
gpio_free(RK29_PIN_PH6);
// rk29_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1);
gpio_free(RK2818_PIN_PE5);
gpio_free(RK2818_PIN_PE4);
rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, 0);
gpio_free(RK29_PIN_PE5);
gpio_free(RK29_PIN_PE4);
rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 0);
}
return ;
pin_err:
@ -100,8 +100,8 @@ void spi_screenreg_set(u32 Addr, u32 Data)
#define DRVDelayUs(i) udelay(i*2)
u32 i;
u32 control_bit;
u32 control_bit;
TXD_OUT();
CLK_OUT();
@ -114,10 +114,10 @@ void spi_screenreg_set(u32 Addr, u32 Data)
CLK_SET();
DRVDelayUs(2);
CS_CLR();
control_bit = 0x70<<8;
Addr = (control_bit | Addr);
//printk("addr is 0x%x \n", Addr);
CS_CLR();
control_bit = 0x70<<8;
Addr = (control_bit | Addr);
//printk("addr is 0x%x \n", Addr);
for(i = 0; i < 16; i++) //reg
{
if(Addr &(1<<(15-i)))
@ -130,17 +130,17 @@ void spi_screenreg_set(u32 Addr, u32 Data)
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
}
CS_SET();
TXD_SET();
CLK_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
CS_CLR();
control_bit = 0x72<<8;
Data = (control_bit | Data);
//printk("data is 0x%x \n", Data);
CS_CLR();
control_bit = 0x72<<8;
Data = (control_bit | Data);
//printk("data is 0x%x \n", Data);
for(i = 0; i < 16; i++) //data
{
if(Data &(1<<(15-i)))
@ -161,29 +161,29 @@ void spi_screenreg_set(u32 Addr, u32 Data)
DRVDelayUs(2);
}
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
//printk("lcd_hx8357 set_lcd_info \n");
//printk("lcd_hx8357 set_lcd_info \n");
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
/* Timing */
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP; /*>2*/
screen->right_margin = H_FP; /*>2*/
screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4<PW+BP<15,
screen->upper_margin = V_BP; /*>2*/
screen->lower_margin = V_FP; /*>2*/
screen->vsync_len = V_PW; /*>6*/
screen->left_margin = H_BP; /*>2*/
screen->right_margin = H_FP; /*>2*/
screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4<PW+BP<15,
screen->upper_margin = V_BP; /*>2*/
screen->lower_margin = V_FP; /*>2*/
screen->vsync_len = V_PW; /*>6*/
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
@ -202,12 +202,12 @@ void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info
}
int init(void)
{
{
if(gLcd_info)
gLcd_info->io_init();
#if 0 //***Õâ¾ä´úÂëÊDz»ÊÇд´íÁË
#if 0 //***Õâ¾ä´úÂëÊDz»ÊÇд´íÁË
spi_screenreg_set(0x02, 0x07);
spi_screenreg_set(0x03, 0x5f);
spi_screenreg_set(0x04, 0x17);
@ -243,136 +243,136 @@ int init(void)
spi_screenreg_set(0x20, 0xF0);
spi_screenreg_set(0x21, 0xF0);
spi_screenreg_set(0x22, 0x09);
#else
spi_screenreg_set(0xff, 0x00);
spi_screenreg_set(0x16, 0x08);
spi_screenreg_set(0x01, 0x02);
spi_screenreg_set(0xe2, 0x00);
spi_screenreg_set(0xe3, 0x00);
spi_screenreg_set(0xf2, 0x00);
spi_screenreg_set(0xe4, 0x1c);
spi_screenreg_set(0xe5, 0x1c);
spi_screenreg_set(0xe6, 0x00);
spi_screenreg_set(0xe7, 0x1c);
spi_screenreg_set(0x19, 0x01);
mdelay(10);
spi_screenreg_set(0x2a, 0x00);
spi_screenreg_set(0x2b, 0x13);
spi_screenreg_set(0x2f, 0x01);
spi_screenreg_set(0x02, 0x00);
spi_screenreg_set(0x03, 0x00);
spi_screenreg_set(0x04, 0x01);
spi_screenreg_set(0x05, 0x3f);
spi_screenreg_set(0x06, 0x00);
spi_screenreg_set(0x07, 0x00);
#else
spi_screenreg_set(0xff, 0x00);
spi_screenreg_set(0x16, 0x08);
spi_screenreg_set(0x01, 0x02);
spi_screenreg_set(0xe2, 0x00);
spi_screenreg_set(0xe3, 0x00);
spi_screenreg_set(0xf2, 0x00);
spi_screenreg_set(0xe4, 0x1c);
spi_screenreg_set(0xe5, 0x1c);
spi_screenreg_set(0xe6, 0x00);
spi_screenreg_set(0xe7, 0x1c);
spi_screenreg_set(0x08, 0x01);
spi_screenreg_set(0x09, 0xdf);
spi_screenreg_set(0x24, 0x91);
spi_screenreg_set(0x25, 0x8a);
spi_screenreg_set(0x29, 0x01);
spi_screenreg_set(0x18, 0x22);
spi_screenreg_set(0x1b, 0x30);
mdelay(10);
spi_screenreg_set(0x1d, 0x22);
mdelay(10);
spi_screenreg_set(0x40, 0x00);
spi_screenreg_set(0x41, 0x3c);
spi_screenreg_set(0x42, 0x38);
spi_screenreg_set(0x43, 0x34);
spi_screenreg_set(0x44, 0x2e);
spi_screenreg_set(0x45, 0x2f);
spi_screenreg_set(0x46, 0x41);
spi_screenreg_set(0x47, 0x7d);
spi_screenreg_set(0x48, 0x0b);
spi_screenreg_set(0x49, 0x05);
spi_screenreg_set(0x4a, 0x06);
spi_screenreg_set(0x4b, 0x12);
spi_screenreg_set(0x4c, 0x16);
spi_screenreg_set(0x50, 0x10);
spi_screenreg_set(0x51, 0x11);
spi_screenreg_set(0x52, 0x0b);
spi_screenreg_set(0x53, 0x07);
spi_screenreg_set(0x54, 0x03);
spi_screenreg_set(0x55, 0x3f);
spi_screenreg_set(0x56, 0x02);
spi_screenreg_set(0x57, 0x3e);
spi_screenreg_set(0x58, 0x09);
spi_screenreg_set(0x59, 0x0d);
spi_screenreg_set(0x5a, 0x19);
spi_screenreg_set(0x5b, 0x1a);
spi_screenreg_set(0x5c, 0x14);
spi_screenreg_set(0x5d, 0xc0);
spi_screenreg_set(0x1a, 0x05);
mdelay(10);
spi_screenreg_set(0x1c, 0x03);
mdelay(10);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x1f, 0xd2);
mdelay(10);
spi_screenreg_set(0x28, 0x04);
mdelay(40);
spi_screenreg_set(0x28, 0x38);
mdelay(40);
spi_screenreg_set(0x28, 0x3c);
mdelay(40);
spi_screenreg_set(0x80, 0x00);
spi_screenreg_set(0x81, 0x00);
spi_screenreg_set(0x82, 0x00);
spi_screenreg_set(0x83, 0x00);
spi_screenreg_set(0x60, 0x08);
spi_screenreg_set(0x31, 0x02);
spi_screenreg_set(0x32, 0x08 /*0x00*/);
spi_screenreg_set(0x17, 0x60); //***RGB666
spi_screenreg_set(0x2d, 0x1f);
spi_screenreg_set(0xe8, 0x90);
#endif
spi_screenreg_set(0x19, 0x01);
mdelay(10);
spi_screenreg_set(0x2a, 0x00);
spi_screenreg_set(0x2b, 0x13);
spi_screenreg_set(0x2f, 0x01);
spi_screenreg_set(0x02, 0x00);
spi_screenreg_set(0x03, 0x00);
spi_screenreg_set(0x04, 0x01);
spi_screenreg_set(0x05, 0x3f);
spi_screenreg_set(0x06, 0x00);
spi_screenreg_set(0x07, 0x00);
spi_screenreg_set(0x08, 0x01);
spi_screenreg_set(0x09, 0xdf);
spi_screenreg_set(0x24, 0x91);
spi_screenreg_set(0x25, 0x8a);
spi_screenreg_set(0x29, 0x01);
spi_screenreg_set(0x18, 0x22);
spi_screenreg_set(0x1b, 0x30);
mdelay(10);
spi_screenreg_set(0x1d, 0x22);
mdelay(10);
spi_screenreg_set(0x40, 0x00);
spi_screenreg_set(0x41, 0x3c);
spi_screenreg_set(0x42, 0x38);
spi_screenreg_set(0x43, 0x34);
spi_screenreg_set(0x44, 0x2e);
spi_screenreg_set(0x45, 0x2f);
spi_screenreg_set(0x46, 0x41);
spi_screenreg_set(0x47, 0x7d);
spi_screenreg_set(0x48, 0x0b);
spi_screenreg_set(0x49, 0x05);
spi_screenreg_set(0x4a, 0x06);
spi_screenreg_set(0x4b, 0x12);
spi_screenreg_set(0x4c, 0x16);
spi_screenreg_set(0x50, 0x10);
spi_screenreg_set(0x51, 0x11);
spi_screenreg_set(0x52, 0x0b);
spi_screenreg_set(0x53, 0x07);
spi_screenreg_set(0x54, 0x03);
spi_screenreg_set(0x55, 0x3f);
spi_screenreg_set(0x56, 0x02);
spi_screenreg_set(0x57, 0x3e);
spi_screenreg_set(0x58, 0x09);
spi_screenreg_set(0x59, 0x0d);
spi_screenreg_set(0x5a, 0x19);
spi_screenreg_set(0x5b, 0x1a);
spi_screenreg_set(0x5c, 0x14);
spi_screenreg_set(0x5d, 0xc0);
spi_screenreg_set(0x1a, 0x05);
mdelay(10);
spi_screenreg_set(0x1c, 0x03);
mdelay(10);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x1f, 0xd2);
mdelay(10);
spi_screenreg_set(0x28, 0x04);
mdelay(40);
spi_screenreg_set(0x28, 0x38);
mdelay(40);
spi_screenreg_set(0x28, 0x3c);
mdelay(40);
spi_screenreg_set(0x80, 0x00);
spi_screenreg_set(0x81, 0x00);
spi_screenreg_set(0x82, 0x00);
spi_screenreg_set(0x83, 0x00);
spi_screenreg_set(0x60, 0x08);
spi_screenreg_set(0x31, 0x02);
spi_screenreg_set(0x32, 0x08 /*0x00*/);
spi_screenreg_set(0x17, 0x60); //***RGB666
spi_screenreg_set(0x2d, 0x1f);
spi_screenreg_set(0xe8, 0x90);
#endif
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
int standby(u8 enable) //***enable =1 means suspend, 0 means resume
int standby(u8 enable) //***enable =1 means suspend, 0 means resume
{
if(gLcd_info)
gLcd_info->io_init();
if(enable) {
//printk("---------hx8357 screen suspend--------------\n");
#if 0
spi_screenreg_set(0x03, 0xde);
#if 0
spi_screenreg_set(0x03, 0xde);
#else
//modify by robert
#if 0
spi_screenreg_set(0x1f, 0x91);
spi_screenreg_set(0x1f, 0x91);
spi_screenreg_set(0x19, 0x00);
#else
spi_screenreg_set(0x28, 0x38);
spi_screenreg_set(0x28, 0x38);
msleep(10);
spi_screenreg_set(0x28, 0x24);
msleep(10);
spi_screenreg_set(0x28, 0x04);
#endif
//modify end
#endif
} else {
#endif
} else {
//printk("--------- hx8357 screen resume--------------\n ");
#if 0
spi_screenreg_set(0x03, 0x5f);
#else
#if 0
spi_screenreg_set(0x03, 0x5f);
#else
//modify by robert
#if 0
spi_screenreg_set(0x19, 0x01);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x19, 0x01);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x1f, 0xd2);
#else
spi_screenreg_set(0x28, 0x38);
spi_screenreg_set(0x28, 0x38);
msleep(10);
spi_screenreg_set(0x28, 0x3c);
msleep(10);
@ -380,10 +380,10 @@ int standby(u8 enable) //***enable =1 means suspend, 0 means resume
spi_screenreg_set(0x81, 0x00);
spi_screenreg_set(0x82, 0x00);
spi_screenreg_set(0x83, 0x00);
#endif
//modify end
#endif
#endif
}
if(gLcd_info)

10
drivers/video/display/screen/lcd_nt35580.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -34,10 +34,10 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define TXD_IN() gpio_direction_input(TXD_PORT)
@ -45,7 +45,7 @@
#define delay_us(i) udelay(i)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
u32 spi_screenreg_get(u32 Addr)
{
@ -422,7 +422,7 @@ int lcd_standby(u8 enable)
}
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;

4
drivers/video/display/screen/lcd_nt35582.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -378,7 +378,7 @@ int lcd_disparea(u8 area)
}
void set_lcd_info(struct rk28fb_screen *screen)
void set_lcd_info(struct rk29fb_screen *screen)
{
/* screen type & face */
screen->type = OUT_TYPE;

6
drivers/video/display/screen/lcd_null.c
View File

@ -1,13 +1,13 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
void set_lcd_info(struct rk28fb_screen *screen)
void set_lcd_info(struct rk29fb_screen *screen)
{
memset(screen, 0, sizeof(struct rk28fb_screen));
memset(screen, 0, sizeof(struct rk29fb_screen));
screen->face = OUT_P666;
}

26
drivers/video/display/screen/lcd_s1d13521.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -118,41 +118,41 @@ void s1d13521if_init_gpio(void)
{
int i;
int ret=0;
rk2818_mux_api_set(GPIOC_LCDC18BIT_SEL_NAME, IOMUXB_GPIO0_C01);
rk2818_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7);
rk29_mux_api_set(GPIOC_LCDC18BIT_SEL_NAME, IOMUXB_GPIO0_C01);
rk29_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7);
for(i = 0; i < 8; i++)
{
if(i == 1 || i == 6)//HIRQ, HRDY
{
ret = gpio_request(GPIO_RESET_L+i, NULL);
ret = gpio_request(GPIO_RESET_L+i, NULL);
if(ret != 0)
{
gpio_free(GPIO_RESET_L+i);
printk(">>>>>> lcd cs gpio_request err \n ");
}
printk(">>>>>> lcd cs gpio_request err \n ");
}
gpio_direction_input(GPIO_RESET_L+i);
gpio_free(GPIO_RESET_L+i);
}
}
else //RESET_L, HD/C, HCS_L, HRD_L, HWE_L, RMODE
{
ret = gpio_request(GPIO_RESET_L+i, NULL);
if(ret != 0)
{
gpio_free(GPIO_RESET_L+i);
printk(">>>>>> lcd cs gpio_request err \n ");
}
printk(">>>>>> lcd cs gpio_request err \n ");
}
gpio_direction_output(GPIO_RESET_L+i, 0);
gpio_set_value(GPIO_RESET_L+i, GPIO_HIGH);
gpio_free(GPIO_RESET_L+i);
gpio_free(GPIO_RESET_L+i);
}
}
}
void s1d13521if_set_reset(void)
{
gpio_request(GPIO_RMODE, 0);
gpio_request(GPIO_RMODE, 0);
gpio_set_value(GPIO_RMODE, GPIO_HIGH);
gpio_request(GPIO_RESET_L, 0);

24
drivers/video/display/screen/lcd_td043mgea1.c
View File

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -31,21 +31,24 @@
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#if 0
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#endif
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
@ -84,7 +87,7 @@ void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info
gLcd_info = lcd_info;
}
#if 0
void spi_screenreg_set(u32 Addr, u32 Data)
{
@ -155,13 +158,15 @@ void spi_screenreg_set(u32 Addr, u32 Data)
DRVDelayUs(2);
}
#endif
int init(void)
{
{
if(gLcd_info)
gLcd_info->io_init();
#if 0
spi_screenreg_set(0x02, 0x07);
spi_screenreg_set(0x03, 0x5f);
spi_screenreg_set(0x04, 0x17);
@ -197,6 +202,7 @@ int init(void)
spi_screenreg_set(0x20, 0xF0);
spi_screenreg_set(0x21, 0xF0);
spi_screenreg_set(0x22, 0x09);
#endif
if(gLcd_info)
gLcd_info->io_deinit();
@ -204,14 +210,16 @@ int init(void)
}
int standby(u8 enable)
{
{
if(gLcd_info)
gLcd_info->io_init();
#if 0
if(enable) {
spi_screenreg_set(0x03, 0xde);
} else {
spi_screenreg_set(0x03, 0x5f);
}
#endif
if(gLcd_info)
gLcd_info->io_deinit();
return 0;

12
drivers/video/display/screen/lcd_tj048nc01ca.c
View File

@ -1,12 +1,12 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
@ -34,20 +34,20 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define DRVDelayUs(i) udelay(i*2)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
int lcd_init(void);
int lcd_standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;

8
drivers/video/display/screen/screen.h
View File

@ -33,7 +33,7 @@ typedef enum _MCU_STATUS {
/* Sceen description */
struct rk28fb_screen {
struct rk29fb_screen {
/* screen type & out face */
u16 type;
u16 face;
@ -79,8 +79,8 @@ struct rk28fb_screen {
};
extern void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info);
extern void set_tv_info(struct rk28fb_screen *screen);
extern void set_hdmi_info(struct rk28fb_screen *screen);
extern void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info);
extern void set_tv_info(struct rk29fb_screen *screen);
extern void set_hdmi_info(struct rk29fb_screen *screen);

6
drivers/video/display/screen/tv_null.c
View File

@ -1,15 +1,15 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
void set_tv_info(struct rk28fb_screen *screen)
void set_tv_info(struct rk29fb_screen *screen)
{
memset(screen, 0, sizeof(struct rk28fb_screen));
memset(screen, 0, sizeof(struct rk29fb_screen));
screen->face = OUT_P666;
}

2150
drivers/video/rk29_fb.c Executable file
View File

File diff suppressed because it is too large Load Diff

436
drivers/video/rk29_fb.h Executable file
View File

@ -0,0 +1,436 @@
/* drivers/video/rk29_fb.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK29_FB_H
#define __ARCH_ARM_MACH_RK29_FB_H
/********************************************************************
** 宏定义 *
********************************************************************/
/* 输往屏的数据格式 */
#define OUT_P888 0
#define OUT_P666 1
#define OUT_P565 2
#define OUT_S888x 4
#define OUT_CCIR656 6
#define OUT_S888 8
#define OUT_S888DUMY 12
#define OUT_P16BPP4 24 //模拟方式,控制器并不支持
/* SYS_CONFIG */
#define m_W2_FORMAT (3<<0)
#define m_W1_FORMAT (1<<2)
#define m_W0_FORMAT (7<<3)
#define m_W0_CBR_DEFLICK_EN (1<<6)
#define m_W0_YRGB_DEFLICK_EN (1<<7)
#define m_INTERIACE_EN (1<<8)
#define m_W2_ENABLE (1<<9)
#define m_W1_ENABLE (1<<10)
#define m_W0_ENABLE (1<<11)
#define m_HWC_ENABLE (1<<12)
#define m_HWC_RELOAD_EN (1<<13)
#define m_W2_INTERLACE_READ (1<<14)
#define m_W1_INTERLACE_READ (1<<15)
#define m_W0_INTERLACE_READ (1<<16)
#define m_STANDBY (1<<17)
#define m_HWC_BURST (3<<18)
#define m_W2_BURST (3<<20)
#define m_W1_BURST (3<<22)
#define m_W0_BURST (3<<24)
#define m_W2_LUT_CTL (1<<26)
#define m_DSIP_LUT_CTL (1<<27)
#define m_HWC_REVERSED_COLOR (1<<28)
#define m_W1_AXI_OUTSTANDING2 (1<<29)
#define m_W0_AXI_OUTSTANDING2 (1<<30)
#define v_W2_FORMAT(x) (((x)&3)<<0)
#define v_W1_FORMAT(x) (((x)&1)<<2)
#define v_W0_FORMAT(x) (((x)&7)<<3)
#define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6)
#define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7)
#define v_INTERIACE_EN(x) (((x)&1)<<8)
#define v_W2_ENABLE(x) (((x)&)1<<9)
#define v_W1_ENABLE(x) (((x)&1)<<10)
#define v_W0_ENABLE(x) (((x)&1)<<11)
#define v_HWC_ENABLE(x) (((x)&1)<<12)
#define v_HWC_RELOAD_EN(x) (((x)&1)<<13)
#define v_W2_INTERLACE_READ(x) (((x)&1)<<14)
#define v_W1_INTERLACE_READ(x) (((x)&1)<<15)
#define v_W0_INTERLACE_READ(x) (((x)&1)<<16)
#define v_STANDBY(x) (((x)&1)<<17)
#define v_HWC_BURST(x) (((x)&3)<<18)
#define v_W2_BURST(x) (((x)&3)<<20)
#define v_W1_BURST(x) (((x)&3)<<22)
#define v_W0_BURST(x) (((x)&3)<<24)
#define v_W2_LUT_CTL(x) (((x)&1)<<26)
#define v_DSIP_LUT_CTL(x) (((x)&1)<<27)
#define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28)
#define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29)
#define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30)
//LCDC_SWAP_CTRL
#define m_W1_565_RB_SWAP (1<<0)
#define m_W0_565_RB_SWAP (1<<1)
#define m_W0_YRGB_M8_SWAP (1<<2)
#define m_W0_YRGB_R_SHIFT_SWAP (1<<3)
#define m_W0_CBR_R_SHIFT_SWAP (1<<4)
#define m_W0_YRGB_16_SWAP (1<<5)
#define m_W0_YRGB_8_SWAP (1<<6)
#define m_W0_CBR_16_SWAP (1<<7)
#define m_W0_CBR_8_SWAP (1<<8)
#define m_W1_16_SWAP (1<<9)
#define m_W1_8_SWAP (1<<10)
#define m_W1_R_SHIFT_SWAP (1<<11)
#define m_OUTPUT_BG_SWAP (1<<12)
#define m_OUTPUT_RB_SWAP (1<<13)
#define m_OUTPUT_RG_SWAP (1<<14)
#define m_DELTA_SWAP (1<<15)
#define m_DUMMY_SWAP (1<<16)
#define m_W2_BYTE_SWAP (1<<17)
#define v_W1_565_RB_SWAP(x) (((x)&1)<<0)
#define v_W0_565_RB_SWAP(x) (((x)&1)<<1)
#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2)
#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3)
#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4)
#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5)
#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6)
#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7)
#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8)
#define v_W1_16_SWAP(x) (((x)&1)<<9)
#define v_W1_8_SWAP(x) (((x)&1)<<10)
#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11)
#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12)
#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13)
#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14)
#define v_DELTA_SWAP(x) (((x)&1)<<15)
#define v_DUMMY_SWAP(x) (((x)&1)<<16)
#define v_W2_BYTE_SWAP(x) (((x)&1)<<17)
//LCDC_MCU_TIMING_CTRL
#define m_MCU_WRITE_PERIOD (31<<0)
#define m_MCU_CS_ST (31<<5)
#define m_MCU_CS_END (31<<10)
#define m_MCU_RW_ST (31<<15)
#define m_MCU_RW_END (31<<20)
#define m_MCU_HOLD_STATUS (1<<26)
#define m_MCU_HOLDMODE_SELECT (1<<27)
#define m_MCU_HOLDMODE_FRAME_ST (1<<28)
#define m_MCU_RS_SELECT (1<<29)
#define m_MCU_BYPASSMODE_SELECT (1<<30)
#define m_MCU_OUTPUT_SELECT (1<<31)
#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0)
#define v_MCU_CS_ST(x) (((x)&31)<<5)
#define v_MCU_CS_END(x) (((x)&31)<<10)
#define v_MCU_RW_ST(x) (((x)&31)<<15)
#define v_MCU_RW_END(x) (((x)&31)<<20)
#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26)
#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
#define v_MCU_RS_SELECT(x) (((x)&1)<<29)
#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
//LCDC_ BLEND_CTRL
#define m_HWC_BLEND_EN (1<<0)
#define m_W2_BLEND_EN (1<<1)
#define m_W1_BLEND_EN (1<<2)
#define m_W0_BLEND_EN (1<<3)
#define m_HWC_BLEND_FACTOR (15<<4)
#define m_W2_BLEND_FACTOR (0xff<<8)
#define m_W1_BLEND_FACTOR (0xff<<16)
#define m_W0_BLEND_FACTOR (0xff<<24)
#define v_HWC_BLEND_EN(x) (((x)&1)<<0)
#define v_W2_BLEND_EN(x) (((x)&1)<<1)
#define v_W1_BLEND_EN(x) (((x)&1)<<2)
#define v_W0_BLEND_EN(x) (((x)&1)<<3)
#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
#define m_KEYCOLOR (0xffffff<<0)
#define m_KEYCOLOR_B (0xff<<0)
#define m_KEYCOLOR_G (0xff<<8)
#define m_KEYCOLOR_R (0xff<<16)
#define m_COLORKEY_EN (1<<24)
#define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
#define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
#define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
#define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
#define v_COLORKEY_EN(x) (((x)&1)<<24)
//LCDC_DEFLICKER_SCL_OFFSET
#define m_W0_YRGB_VSD_OFFSET (0xff<<0)
#define m_W0_YRGB_VSP_OFFSET (0xff<<8)
#define m_W1_VSD_OFFSET (0xff<<16)
#define m_W1_VSP_OFFSET (0xff<<24)
#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
//LCDC_DSP_CTRL_REG0
#define m_DISPLAY_FORMAT (0xf<<0)
#define m_HSYNC_POLARITY (1<<4)
#define m_VSYNC_POLARITY (1<<5)
#define m_DEN_POLARITY (1<<6)
#define m_DCLK_POLARITY (1<<7)
#define m_COLOR_SPACE_CONVERSION (3<<8)
#define m_DITHER_UP_EN (1<<10)
#define m_DITHER_DOWN_MODE (1<<11)
#define m_DITHER_DOWN_EN (1<<12)
#define m_INTERLACE_FIELD_POLARITY (1<<13)
#define m_YUV_CLIP (1<<14)
#define m_W1_TRANSP_FROM (1<<15)
#define m_W0_TRANSP_FROM (1<<16)
#define m_W0_ON_TOP (1<<17)
#define m_W1_CLIP_EN (1<<18)
#define m_W0_CLIP_EN (1<<19)
#define m_W0_YCBR_PRIORITY_MODE (1<<20)
#define m_CBR_FILTER_656 (1<<21)
#define m_W2_CHIP_EN (1<<22)
#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
#define v_HSYNC_POLARITY(x) (((x)&1)<<4)
#define v_VSYNC_POLARITY(x) (((x)&1)<<5)
#define v_DEN_POLARITY(x) (((x)&1)<<6)
#define v_DCLK_POLARITY(x) (((x)&1)<<7)
#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8)
#define v_DITHER_UP_EN(x) (((x)&1)<<10)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<11)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<12)
#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
#define v_YUV_CLIP(x) (((x)&1)<<14)
#define v_W1_TRANSP_FROM(x) (((x)&1)<<15)
#define v_W0_TRANSP_FROM(x) (((x)&1)<<16)
#define v_W0_ON_TOP(x) (((x)&1)<<17)
#define v_W1_CLIP_EN(x) (((x)&1)<<18)
#define v_W0_CLIP_EN(x) (((x)&1)<<19)
#define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20)
#define v_CBR_FILTER_656(x) (((x)&1)<<21)
#define v_W2_CHIP_EN(x) (((x)&1)<<22)
//LCDC_DSP_CTRL_REG1
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define m_BLANK_MODE (1<<24)
#define m_BLACK_MODE (1<<25)
#define m_DISP_FILTER_FACTOR (3<<26)
#define m_DISP_FILTER_MODE (1<<28)
#define m_DISP_FILTER_EN (1<<29)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
#define v_BLANK_MODE(x) (((x)&1)<<24)
#define v_BLACK_MODE(x) (((x)&1)<<25)
#define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26)
#define v_DISP_FILTER_MODE(x) (((x)&1)<<28)
#define v_DISP_FILTER_EN(x) (((x)&1)<<29)
//LCDC_INT_STATUS
#define m_HOR_START (1<<0)
#define m_FRM_START (1<<1)
#define m_SCANNING_FLAG (1<<2)
#define m_HOR_STARTMASK (1<<3)
#define m_FRM_STARTMASK (1<<4)
#define m_SCANNING_MASK (1<<5)
#define m_HOR_STARTCLEAR (1<<6)
#define m_FRM_STARTCLEAR (1<<7)
#define m_SCANNING_CLEAR (1<<8)
#define m_SCAN_LINE_NUM (0x7ff<<9)
#define v_HOR_START(x) (((x)&1)<<0)
#define v_FRM_START(x) (((x)&1)<<1)
#define v_SCANNING_FLAG(x) (((x)&1)<<2)
#define v_HOR_STARTMASK(x) (((x)&1)<<3)
#define v_FRM_STARTMASK(x) (((x)&1)<<4)
#define v_SCANNING_MASK(x) (((x)&1)<<5)
#define v_HOR_STARTCLEAR(x) (((x)&1)<<6)
#define v_FRM_STARTCLEAR(x) (((x)&1)<<7)
#define v_SCANNING_CLEAR(x) (((x)&1)<<8)
#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9)
//AXI MS ID
#define m_W0_YRGB_CH_ID (0xF<<0)
#define m_W0_CBR_CH_ID (0xF<<4)
#define m_W1_YRGB_CH_ID (0xF<<8)
#define m_W2_CH_ID (0xF<<12)
#define m_HWC_CH_ID (0xF<<16)
#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
#define v_W2_CH_ID(x) (((x)&0xF)<<12)
#define v_HWC_CH_ID(x) (((x)&0xF)<<16)
/* Low Bits Mask */
#define m_WORDLO (0xffff<<0)
#define m_WORDHI (0xffff<<16)
#define v_WORDLO(x) (((x)&0xffff)<<0)
#define v_WORDHI(x) (((x)&0xffff)<<16)
#define m_BIT11LO (0x7ff<<0)
#define m_BIT11HI (0x7ff<<16)
#define v_BIT11LO(x) (((x)&0x7ff)<<0)
#define v_BIT11HI(x) (((x)&0x7ff)<<16)
#define m_VIRWIDTH (0xffff<<0)
#define m_VIRHEIGHT (0xffff<<16)
#define v_VIRWIDTH(x) (((x)&0xffff)<<0)
#define v_VIRHEIGHT(x) (((x)&0xffff)<<16)
#define m_ACTWIDTH (0xffff<<0)
#define m_ACTHEIGHT (0xffff<<16)
#define v_ACTWIDTH(x) (((x)&0xffff)<<0)
#define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
#define m_VIRST_X (0xffff<<0)
#define m_VIRST_Y (0xffff<<16)
#define v_VIRST_X(x) (((x)&0xffff)<<0)
#define v_VIRST_Y(x) (((x)&0xffff)<<16)
#define m_PANELST_X (0x3ff<<0)
#define m_PANELST_Y (0x3ff<<16)
#define v_PANELST_X(x) (((x)&0x3ff)<<0)
#define v_PANELST_Y(x) (((x)&0x3ff)<<16)
#define m_PANELWIDTH (0x3ff<<0)
#define m_PANELHEIGHT (0x3ff<<16)
#define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
#define m_HWC_B (0xff<<0)
#define m_HWC_G (0xff<<8)
#define m_HWC_R (0xff<<16)
#define m_W0_YRGB_HSP_OFFSET (0xff<<24)
#define m_W0_YRGB_HSD_OFFSET (0xff<<24)
#define v_HWC_B(x) (((x)&0xff)<<0)
#define v_HWC_G(x) (((x)&0xff)<<8)
#define v_HWC_R(x) (((x)&0xff)<<16)
#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
//Panel display scanning
#define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
#define m_PANEL_END (0x3ff<<0)
#define m_PANEL_START (0x3ff<<16)
#define v_PANEL_END(x) (((x)&0x3ff)<<0)
#define v_PANEL_START(x) (((x)&0x3ff)<<16)
#define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
//-----------
#define m_HSCALE_FACTOR (0xffff<<0)
#define m_VSCALE_FACTOR (0xffff<<16)
#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
#define m_W0_CBR_HSD_OFFSET (0xff<<0)
#define m_W0_CBR_HSP_OFFSET (0xff<<8)
#define m_W0_CBR_VSD_OFFSET (0xff<<16)
#define m_W0_CBR_VSP_OFFSET (0xff<<24)
#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
#define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
#define FB0_IOCTL_SET_PANEL 0x6002
#define FB1_IOCTL_GET_PANEL_SIZE 0x5001
#define FB1_IOCTL_SET_YUV_ADDR 0x5002
//#define FB1_TOCTL_SET_MCU_DIR 0x5003
#define FB1_IOCTL_SET_ROTATE 0x5003
#define FB1_IOCTL_SET_I2P_ODD_ADDR 0x5005
#define FB1_IOCTL_SET_I2P_EVEN_ADDR 0x5006
/********************************************************************
** 结构定义 *
********************************************************************/
/* LCDC的寄存器结构 */
typedef volatile struct tagLCDC_REG
{
/* offset 0x00~0xc0 */
unsigned int SYS_CONFIG; //0x00 SYSTEM configure register
unsigned int SWAP_CTRL; //0x04 Data SWAP control
unsigned int MCU_TIMING_CTRL; //0x08 MCU TIMING control register
unsigned int BLEND_CTRL; //0x0c Blending control register
unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register
unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register
unsigned int WIN2_VIR; //0x18 WIN2 virtual display width
unsigned int DSP_CTRL0; //0x1c Display control register0
unsigned int DSP_CTRL1; //0x20 Display control register1
unsigned int INT_STATUS; //0x24 Interrupt status register
unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height
unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address
unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address
unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height
unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel
unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel
unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height
unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address
unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel
unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel
unsigned int WIN2_MST; //0X50 Win2 memory start address
unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel
unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel
unsigned int HWC_MST; //0x5C HWC memory start address
unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel
unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2’b01 look up table 0
unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2’b10 look up table 1
unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2’b11 look up table 2
unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point
unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point
unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point
unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point
unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode
unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode
unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting
unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting
unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset
unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark
unsigned int AXI_MS_ID; //0x98 Axi master ID
unsigned int reserved0; //0x9c
unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH
unsigned int reserved1[(0x100-0xa4)/4];
unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
unsigned int reserved2[(0x200-0x104)/4];
unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
} LCDC_REG, *pLCDC_REG;
extern void __init rk29_add_device_lcdc(void);
extern int mcu_ioctl(unsigned int cmd, unsigned long arg);
#endif

2
fs/yaffs2/yaffs_fs.c
View File

@ -2189,7 +2189,7 @@ static struct super_block *yaffs_internal_read_super(int yaffsVersion,
dev->nReservedBlocks = 5;
dev->nShortOpCaches = (options.no_cache) ? 0 : 10;
dev->inbandTags = options.inband_tags;
#ifdef CONFIG_ARCH_RK2818
#if defined (CONFIG_ARCH_RK2818) || (CONFIG_ARCH_RK29)
dev->inbandTags = 1;
#endif