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iommu/amd: Add SNP page mode 0 support
Newer AMD IOMMUs supports DTE[Mode]=0 for SNP-enabled system. This is detected using new feature bit (EFR2[SNP_Page_Mode_0_Sup]). If this feature is enabled, then IOMMU supports: - Passthrough mode (i.e. iommu=pt) - amd_iommu=pgtbl_v2: Forcing Linux DMA-API to use IOMMU v2 page table - Setting up device for SVA mode in the host. Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: Amandeep Kaur Longia <AmandeepKaur.Longia@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -113,6 +113,7 @@
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#define FEATURE_SNPAVICSUP_GAM(x) \
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(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
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#define FEATURE_HT_RANGE_IGNORE BIT_ULL(11)
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#define FEATURE_SNP_PAGE_MODE0_SUP BIT_ULL(13)
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#define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8)
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#define FEATURE_NUM_INT_REMAP_SUP_2K(x) \
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@ -419,6 +420,9 @@ extern bool amd_iommu_dump;
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pr_info(format, ## arg); \
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} while(0);
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/* SNP page mode 0 support */
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extern bool amd_iommu_snp_mode0_sup;
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/* global flag if IOMMUs cache non-present entries */
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extern bool amd_iommu_np_cache;
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/* Only true if all IOMMUs support device IOTLBs */
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@ -180,6 +180,9 @@ bool amd_iommu_hatdis;
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bool amd_iommu_snp_en;
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EXPORT_SYMBOL(amd_iommu_snp_en);
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/* SNP page mode 0 support */
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bool amd_iommu_snp_mode0_sup;
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LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */
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LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */
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LIST_HEAD(amd_ivhd_dev_flags_list); /* list of all IVHD device entry settings */
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@ -3394,18 +3397,28 @@ static __init void iommu_snp_enable(void)
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#ifdef CONFIG_KVM_AMD_SEV
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if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP))
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return;
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/*
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* The SNP support requires that IOMMU must be enabled, and is
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* configured with V1 page table (DTE[Mode] = 0 is not supported).
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*/
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if (no_iommu || iommu_default_passthrough()) {
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pr_warn("SNP: IOMMU disabled or configured in passthrough mode, SNP cannot be supported.\n");
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/* SNP support required IOMMU to be ON */
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if (no_iommu) {
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pr_warn("SNP: IOMMU disabled, SNP cannot be supported.\n");
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goto disable_snp;
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}
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if (amd_iommu_pgtable != PD_MODE_V1) {
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pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n");
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goto disable_snp;
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amd_iommu_snp_mode0_sup = check_feature2(FEATURE_SNP_PAGE_MODE0_SUP);
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/*
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* If SNP page mode 0 is not enabled, then SNP support requires that IOMMU
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* must be configured with V1 page table (DTE[Mode] != 0).
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*/
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if (!amd_iommu_snp_mode0_sup) {
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if (iommu_default_passthrough()) {
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pr_warn("SNP: IOMMU configured in passthrough mode, SNP cannot be supported.\n");
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goto disable_snp;
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}
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if (amd_iommu_pgtable != PD_MODE_V1) {
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pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n");
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goto disable_snp;
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}
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}
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amd_iommu_snp_en = check_feature(FEATURE_SNP);
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@ -3940,12 +3953,15 @@ bool amd_iommu_pasid_supported(void)
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amd_iommu_gpt_level != PAGE_MODE_5_LEVEL)
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return false;
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if (!amd_iommu_gt_ppr_supported())
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return false;
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/*
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* Since DTE[Mode]=0 is prohibited on SNP-enabled system
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* (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without
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* setting up IOMMUv1 page table.
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* If SNP page mode 0 is not supported, then DTE[Mode]=0 is prohibited
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* on SNP-enabled system (i.e. EFR[SNPSup]=1). IOMMUv2 page table
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* cannot be used without setting up IOMMUv1 page table.
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*/
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return amd_iommu_gt_ppr_supported() && !amd_iommu_snp_en;
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return (!amd_iommu_snp_en) || (amd_iommu_snp_en && amd_iommu_snp_mode0_sup);
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}
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struct amd_iommu *get_amd_iommu(unsigned int idx)
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@ -2953,9 +2953,9 @@ static int amd_iommu_identity_attach(struct iommu_domain *dom, struct device *de
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{
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/*
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* Don't allow attaching a device to the identity domain if SNP is
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* enabled.
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* enabled and SNP Mode0 support is not present.
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*/
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if (amd_iommu_snp_en)
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if (amd_iommu_snp_en && !amd_iommu_snp_mode0_sup)
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return -EINVAL;
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return amd_iommu_attach_device(dom, dev, old);
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