This pull request contains Broadcom ARM-based SoC changes for 5.19,

please pull the following:
 
 - Julia fixes a couple of typographic errors in the Brahma-B15 read
   ahead cache driver and in the ARCH_BRCMSTB bare metal SMP bring-up code
 
 - William adds a Kconfig entry for ARCH_BCMBCA which will be used to
   upstream support for Broadcom's broadband SoCs
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Merge tag 'arm-soc/for-5.19/soc' of https://github.com/Broadcom/stblinux into arm/soc

This pull request contains Broadcom ARM-based SoC changes for 5.19,
please pull the following:

- Julia fixes a couple of typographic errors in the Brahma-B15 read
  ahead cache driver and in the ARCH_BRCMSTB bare metal SMP bring-up code

- William adds a Kconfig entry for ARCH_BCMBCA which will be used to
  upstream support for Broadcom's broadband SoCs

* tag 'arm-soc/for-5.19/soc' of https://github.com/Broadcom/stblinux:
  arm: bcmbca: add arch bcmbca machine entry
  ARM: brcmstb: fix typos in comments
  ARM: mm: fix typos in comments

Link: https://lore.kernel.org/r/20220504210942.1838248-6-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arch/arm/mach-bcm/Kconfig

@@ -218,4 +218,16 @@ config ARCH_BRCMSTB
 	  This enables support for Broadcom ARM-based set-top box chipsets,
 	  including the 7445 family of chips.
 
+config ARCH_BCMBCA
+	bool "Broadcom Broadband SoC"
+	depends on ARCH_MULTI_V7
+	select ARM_AMBA
+	select ARM_GIC
+	select HAVE_ARM_ARCH_TIMER
+	help
+	  Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
+	  BCA chipset.
+
+	  This enables support for Broadcom BCA ARM-based broadband chipsets,
+	  including the DSL, PON and Wireless family of chips.
 endif

arch/arm/mach-bcm/platsmp-brcmstb.c

@@ -59,7 +59,7 @@ static u32 hif_cont_reg;
 /*
  * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
  * one or more cache may be disabled, we must flush to ensure coherency. We
- * cannot use traditionl completion structures or spinlocks as they rely on
+ * cannot use traditional completion structures or spinlocks as they rely on
  * coherency.
  */
 static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);

arch/arm/mm/cache-b15-rac.c

@@ -74,7 +74,7 @@ static inline void __b15_rac_flush(void)
 	__raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset);
 	do {
 		/* This dmb() is required to force the Bus Interface Unit
-		 * to clean oustanding writes, and forces an idle cycle
+		 * to clean outstanding writes, and forces an idle cycle
 		 * to be inserted.
 		 */
 		dmb();