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drm/amdgpu: Check RRMT status for JPEG v4.0.3
RRMT could get dynamically enabled/disabled by PSP firmware. Read the status from register for reading RRMT status. For VFs, this is not accessible, hence assume that it's always disabled for now. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -92,6 +92,12 @@
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*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \
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} while (0)
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enum amdgpu_jpeg_caps {
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AMDGPU_JPEG_RRMT_ENABLED,
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};
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#define AMDGPU_JPEG_CAPS(caps) BIT(AMDGPU_JPEG_##caps)
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struct amdgpu_jpeg_reg{
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unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
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};
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@ -130,6 +136,7 @@ struct amdgpu_jpeg {
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uint8_t num_inst_per_aid;
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bool indirect_sram;
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uint32_t supported_reset;
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uint32_t caps;
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};
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int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
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@ -61,8 +61,7 @@ static int amdgpu_ih_srcid_jpeg[] = {
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static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
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{
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return amdgpu_sriov_vf(adev) ||
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(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4));
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return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0;
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}
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/**
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@ -331,6 +330,11 @@ static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)
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}
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}
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} else {
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/* This flag is not set for VF, assumed to be disabled always */
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if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &
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0x100)
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adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED);
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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jpeg_inst = GET_INST(JPEG, i);
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