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Merge tag 'drm-intel-gt-next-2025-07-02' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

Browse Source 
Driver Changes:

Fixes/improvements/new stuff:

- Avoid GuC scheduling stalls [guc] (Julia Filipchuk)
- Remove force_probe requirement for DG1 (Ville Syrjälä)
- Handle errors correctly to avoid losing GuC-2-Host messages [guc] (Jesus Narvaez)
- Avoid double wakeref put if GuC context deregister failed [guc] (Jesus Narvaez)
- Avoid timeline memory leak with signals and legacy platforms [ringbuf] (Janusz Krzysztofik)
- Fix MEI (discrete) interrupt handler on RT kernels [gsc] (Junxiao Chang)

Miscellaneous:

- Allow larger memory allocation [selftest] (Mikolaj Wasiak)
- Use provided dma_fence_is_chain (Tvrtko Ursulin)
- Fix build error with GCOV and AutoFDO enabled [pmu] (Tzung-Bi Shih)
- Fix build error some more (Arnd Bergmann)
- Reduce stack usage in igt_vma_pin1() (Arnd Bergmann)
- Move out engine related macros from i915_drv.h (Krzysztof Karas)
- Move GEM_QUIRK_PIN_SWIZZLED_PAGES to i915_gem.h (Krzysztof Karas)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tursulin@igalia.com>
Link: https://lore.kernel.org/r/aGTjUBeOQFw26bRT@linux
This commit is contained in:
Dave Airlie 2025-07-04 11:43:29 +10:00
commit ca39a37174
12 changed files with 71 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/i915/gem/i915_gem_wait.c
View File

@ -106,11 +106,6 @@ static void fence_set_priority(struct dma_fence *fence,
rcu_read_unlock();
}
static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
{
return fence->ops == &dma_fence_chain_ops;
}
void i915_gem_fence_wait_priority(struct dma_fence *fence,
const struct i915_sched_attr *attr)
{
@ -126,7 +121,7 @@ void i915_gem_fence_wait_priority(struct dma_fence *fence,
for (i = 0; i < array->num_fences; i++)
fence_set_priority(array->fences[i], attr);
} else if (__dma_fence_is_chain(fence)) {
} else if (dma_fence_is_chain(fence)) {
struct dma_fence *iter;
/* The chain is ordered; if we boost the last, we boost all */

31
drivers/gpu/drm/i915/gt/intel_engine.h
View File

@ -79,6 +79,29 @@ struct lock_class_key;
#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
unsigned int first__ = (first); \
unsigned int count__ = (count); \
((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
})
#define ENGINE_INSTANCES_MASK(gt, first, count) \
__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
#define RCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
#define BCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
#define VDBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
#define VEBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
#define CCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
#define GEN6_RING_FAULT_REG_READ(engine__) \
intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
@ -355,4 +378,12 @@ u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value);
u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);
u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);
#define rb_to_uabi_engine(rb) \
rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
#define for_each_uabi_engine(engine__, i915__) \
for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
(engine__); \
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
#endif /* _INTEL_RINGBUFFER_H_ */

2
drivers/gpu/drm/i915/gt/intel_gsc.c
View File

@ -284,7 +284,7 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
if (gt->gsc.intf[intf_id].irq < 0)
return;
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
ret = generic_handle_irq_safe(gt->gsc.intf[intf_id].irq);
if (ret)
gt_err_ratelimited(gt, "error handling GSC irq: %d\n", ret);
}

3
drivers/gpu/drm/i915/gt/intel_ring_submission.c
View File

@ -610,7 +610,6 @@ static int ring_context_alloc(struct intel_context *ce)
/* One ringbuffer to rule them all */
GEM_BUG_ON(!engine->legacy.ring);
ce->ring = engine->legacy.ring;
ce->timeline = intel_timeline_get(engine->legacy.timeline);
GEM_BUG_ON(ce->state);
if (engine->context_size) {
@ -623,6 +622,8 @@ static int ring_context_alloc(struct intel_context *ce)
ce->state = vma;
}
ce->timeline = intel_timeline_get(engine->legacy.timeline);
return 0;
}

7
drivers/gpu/drm/i915/gt/uc/intel_guc.c
View File

@ -313,8 +313,13 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
*
* The same WA bit is used for both and 22011391025 is applicable to
* all DG2.
*
* Platforms post DG2 prevent this issue in hardware by stalling
* submissions. With this flag GuC will schedule as to avoid such
* stalls.
*/
if (IS_DG2(gt->i915))
if (IS_DG2(gt->i915) ||
(CCS_MASK(gt) && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)))
flags |= GUC_WA_DUAL_QUEUE;
/* Wa_22011802037: graphics version 11/12 */

33
drivers/gpu/drm/i915/i915_drv.h
View File

@ -66,8 +66,6 @@ struct intel_display;
struct intel_pxp;
struct vlv_s0ix_state;
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
struct i915_dsm {
/*
@ -354,14 +352,6 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
return i915->gt[0];
}
#define rb_to_uabi_engine(rb) \
rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
#define for_each_uabi_engine(engine__, i915__) \
for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
(engine__); \
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
#define INTEL_INFO(i915) ((i915)->__info)
#define RUNTIME_INFO(i915) (&(i915)->__runtime)
#define DRIVER_CAPS(i915) (&(i915)->caps)
@ -570,29 +560,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915))
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
unsigned int first__ = (first); \
unsigned int count__ = (count); \
((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
})
#define ENGINE_INSTANCES_MASK(gt, first, count) \
__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
#define RCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
#define BCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
#define VDBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
#define VEBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
#define CCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
/*

2
drivers/gpu/drm/i915/i915_gem.h
View File

@ -134,4 +134,6 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
#define I915_GEM_IDLE_TIMEOUT (HZ / 5)
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
#endif /* __I915_GEM_H__ */

1
drivers/gpu/drm/i915/i915_pci.c
View File

@ -663,7 +663,6 @@ static const struct intel_device_info dg1_info = {
DGFX_FEATURES,
.__runtime.graphics.ip.rel = 10,
PLATFORM(INTEL_DG1),
.require_force_probe = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
BIT(VCS0) | BIT(VCS2),

6
drivers/gpu/drm/i915/i915_pmu.c
View File

@ -108,11 +108,11 @@ static unsigned int config_bit(const u64 config)
return other_bit(config);
}
static u32 config_mask(const u64 config)
static __always_inline u32 config_mask(const u64 config)
{
unsigned int bit = config_bit(config);
if (__builtin_constant_p(config))
if (__builtin_constant_p(bit))
BUILD_BUG_ON(bit >
BITS_PER_TYPE(typeof_member(struct i915_pmu,
enable)) - 1);
@ -121,7 +121,7 @@ static u32 config_mask(const u64 config)
BITS_PER_TYPE(typeof_member(struct i915_pmu,
enable)) - 1);
return BIT(config_bit(config));
return BIT(bit);
}
static bool is_engine_event(struct perf_event *event)

20
drivers/gpu/drm/i915/i915_vma.c
View File

@ -1607,6 +1607,26 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
return err;
}
int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
struct i915_gem_ww_ctx ww;
int err;
i915_gem_ww_ctx_init(&ww, true);
retry:
err = i915_gem_object_lock(vma->obj, &ww);
if (!err)
err = i915_vma_pin_ww(vma, &ww, size, alignment, flags);
if (err == -EDEADLK) {
err = i915_gem_ww_ctx_backoff(&ww);
if (!err)
goto retry;
}
i915_gem_ww_ctx_fini(&ww);
return err;
}
static void flush_idle_contexts(struct intel_gt *gt)
{
struct intel_engine_cs *engine;

22
drivers/gpu/drm/i915/i915_vma.h
View File

@ -289,26 +289,8 @@ int __must_check
i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
u64 size, u64 alignment, u64 flags);
static inline int __must_check
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
struct i915_gem_ww_ctx ww;
int err;
i915_gem_ww_ctx_init(&ww, true);
retry:
err = i915_gem_object_lock(vma->obj, &ww);
if (!err)
err = i915_vma_pin_ww(vma, &ww, size, alignment, flags);
if (err == -EDEADLK) {
err = i915_gem_ww_ctx_backoff(&ww);
if (!err)
goto retry;
}
i915_gem_ww_ctx_fini(&ww);
return err;
}
int __must_check
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags);
int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
u32 align, unsigned int flags);

14
drivers/gpu/drm/i915/selftests/intel_memory_region.c
View File

@ -413,15 +413,8 @@ static int igt_mock_splintered_region(void *arg)
close_objects(mem, &objects);
/*
* While we should be able allocate everything without any flag
* restrictions, if we consider I915_BO_ALLOC_CONTIGUOUS then we are
* actually limited to the largest power-of-two for the region size i.e
* max_order, due to the inner workings of the buddy allocator. So make
* sure that does indeed hold true.
*/
obj = igt_object_create(mem, &objects, size, I915_BO_ALLOC_CONTIGUOUS);
obj = igt_object_create(mem, &objects, roundup_pow_of_two(size),
I915_BO_ALLOC_CONTIGUOUS);
if (!IS_ERR(obj)) {
pr_err("%s too large contiguous allocation was not rejected\n",
__func__);
@ -429,8 +422,7 @@ static int igt_mock_splintered_region(void *arg)
goto out_close;
}
obj = igt_object_create(mem, &objects, rounddown_pow_of_two(size),
I915_BO_ALLOC_CONTIGUOUS);
obj = igt_object_create(mem, &objects, size, I915_BO_ALLOC_CONTIGUOUS);
if (IS_ERR(obj)) {
pr_err("%s largest possible contiguous allocation failed\n",
__func__);