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ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane}

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There is only one PCIe PHY in this SoC, so there is no need to add an
index to the suffix. This also matches the naming convention of the PCIe
controller.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308082424.140224-7-manivannan.sadhasivam@linaro.org
This commit is contained in:
Manivannan Sadhasivam 2023-03-08 13:54:17 +05:30 committed by Bjorn Andersson
parent 3b76b736cd
commit c9f30e3dd9
2 changed files with 4 additions and 4 deletions
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2
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
View File

@ -242,7 +242,7 @@ &ipa {
status = "okay";
};
&pcie0_phy {
&pcie_phy {
status = "okay";
vdda-phy-supply = <&vreg_l1e_bb_1p2>;

6
arch/arm/boot/dts/qcom-sdx55.dtsi
View File

@ -335,7 +335,7 @@ pcie_ep: pcie-ep@1c00000 {
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie0_lane>;
phys = <&pcie_lane>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
@ -343,7 +343,7 @@ pcie_ep: pcie-ep@1c00000 {
status = "disabled";
};
pcie0_phy: phy@1c07000 {
pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
reg = <0x01c07000 0x1c4>;
#address-cells = <1>;
@ -363,7 +363,7 @@ pcie0_phy: phy@1c07000 {
status = "disabled";
pcie0_lane: lanes@1c06000 {
pcie_lane: lanes@1c06000 {
reg = <0x01c06000 0x104>, /* tx0 */
<0x01c06200 0x328>, /* rx0 */
<0x01c07200 0x1e8>, /* pcs */