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clk: samsung: Use single CPU clock notifier callback for all chips

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Reduce the code duplication by making all chips use a single version of
exynos_cpuclk_notifier_cb() function. That will prevent the code bloat
when adding new chips support too.

Also don't pass base address to pre/post rate change functions, as it
can be easily derived from already passed cpuclk param.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-6-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Sam Protsenko 2024-02-24 14:20:43 -06:00 committed by Krzysztof Kozlowski
parent 84d42803e4
commit c9bc1f7786
1 changed files with 28 additions and 35 deletions
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63
drivers/clk/samsung/clk-cpu.c
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@ -66,6 +66,11 @@
#define DIV_MASK_ALL GENMASK(31, 0)
#define MUX_MASK GENMASK(2, 0)
struct exynos_cpuclk;
typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk);
/**
* struct exynos_cpuclk - information about clock supplied to a CPU core
* @hw: handle between CCF and CPU clock
@ -78,6 +83,8 @@
* @clk_nb: clock notifier registered for changes in clock speed of the
* primary parent clock
* @flags: configuration flags for the CPU clock
* @pre_rate_cb: callback to run before CPU clock rate change
* @post_rate_cb: callback to run after CPU clock rate change
*
* This structure holds information required for programming the CPU clock for
* various clock speeds.
@ -91,6 +98,9 @@ struct exynos_cpuclk {
const unsigned long num_cfgs;
struct notifier_block clk_nb;
unsigned long flags;
exynos_rate_change_fn_t pre_rate_cb;
exynos_rate_change_fn_t post_rate_cb;
};
/*
@ -178,9 +188,10 @@ static void exynos_set_safe_div(void __iomem *base, unsigned long div,
/* handler for pre-rate change notification from parent clock */
static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
void __iomem *base = cpuclk->ctrl_base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@ -255,9 +266,10 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* handler for post-rate change notification from parent clock */
static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
void __iomem *base = cpuclk->ctrl_base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
@ -306,9 +318,10 @@ static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
/* handler for pre-rate change notification from parent clock */
static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
void __iomem *base = cpuclk->ctrl_base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@ -366,8 +379,9 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* handler for post-rate change notification from parent clock */
static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
struct exynos_cpuclk *cpuclk)
{
void __iomem *base = cpuclk->ctrl_base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
@ -393,39 +407,14 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
{
struct clk_notifier_data *ndata = data;
struct exynos_cpuclk *cpuclk;
void __iomem *base;
int err = 0;
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
base = cpuclk->ctrl_base;
if (event == PRE_RATE_CHANGE)
err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
err = cpuclk->pre_rate_cb(ndata, cpuclk);
else if (event == POST_RATE_CHANGE)
err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
return notifier_from_errno(err);
}
/*
* This notifier function is called for the pre-rate and post-rate change
* notifications of the parent clock of cpuclk.
*/
static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct exynos_cpuclk *cpuclk;
void __iomem *base;
int err = 0;
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
base = cpuclk->ctrl_base;
if (event == PRE_RATE_CHANGE)
err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
else if (event == POST_RATE_CHANGE)
err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
err = cpuclk->post_rate_cb(ndata, cpuclk);
return notifier_from_errno(err);
}
@ -467,10 +456,14 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
cpuclk->ctrl_base = ctx->reg_base + clk_data->offset;
cpuclk->lock = &ctx->lock;
cpuclk->flags = clk_data->flags;
if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
else
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) {
cpuclk->pre_rate_cb = exynos5433_cpuclk_pre_rate_change;
cpuclk->post_rate_cb = exynos5433_cpuclk_post_rate_change;
} else {
cpuclk->pre_rate_cb = exynos_cpuclk_pre_rate_change;
cpuclk->post_rate_cb = exynos_cpuclk_post_rate_change;
}
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
if (ret) {