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staging: gpib: agilent_02350b: cleanup comments
Cleans up the comments in both the c and the h file. Standardises the comment type (/* */) and the indentation. Signed-off-by: Ruben Wauters <rubenru09@aol.com> Link: https://lore.kernel.org/r/20250415151246.30337-1-rubenru09@aol.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ruben Wauters
Greg Kroah-Hartman
parent
b0b23267b6
commit
c9bc151fb0
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@ -39,7 +39,7 @@ static int agilent_82350b_accel_read(struct gpib_board *board, u8 *buffer,
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int retval = 0;
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unsigned short event_status;
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int i, num_fifo_bytes;
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//hardware doesn't support checking for end-of-string character when using fifo
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/* hardware doesn't support checking for end-of-string character when using fifo */
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if (tms_priv->eos_flags & REOS)
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return tms9914_read(board, tms_priv, buffer, length, end, bytes_read);
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@ -50,9 +50,9 @@ static int agilent_82350b_accel_read(struct gpib_board *board, u8 *buffer,
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*bytes_read = 0;
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if (length == 0)
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return 0;
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//disable fifo for the moment
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/* disable fifo for the moment */
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writeb(DIRECTION_GPIB_TO_HOST, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
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// handle corner case of board not in holdoff and one byte might slip in early
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/* handle corner case of board not in holdoff and one byte might slip in early */
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if (tms_priv->holdoff_active == 0 && length > 1) {
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size_t num_bytes;
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@ -67,7 +67,8 @@ static int agilent_82350b_accel_read(struct gpib_board *board, u8 *buffer,
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tms9914_release_holdoff(tms_priv);
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i = 0;
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num_fifo_bytes = length - 1;
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write_byte(tms_priv, tms_priv->imr0_bits & ~HR_BIIE, IMR0); // disable BI interrupts
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/* disable BI interrupts */
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write_byte(tms_priv, tms_priv->imr0_bits & ~HR_BIIE, IMR0);
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while (i < num_fifo_bytes && *end == 0) {
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int block_size;
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int j;
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@ -111,17 +112,18 @@ static int agilent_82350b_accel_read(struct gpib_board *board, u8 *buffer,
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break;
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}
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}
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write_byte(tms_priv, tms_priv->imr0_bits, IMR0); // re-enable BI interrupts
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/* re-enable BI interrupts */
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write_byte(tms_priv, tms_priv->imr0_bits, IMR0);
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*bytes_read += i;
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buffer += i;
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length -= i;
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writeb(DIRECTION_GPIB_TO_HOST, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
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if (retval < 0)
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return retval;
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// read last bytes if we havn't received an END yet
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/* read last bytes if we havn't received an END yet */
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if (*end == 0) {
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size_t num_bytes;
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// try to make sure we holdoff after last byte read
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/* try to make sure we holdoff after last byte read */
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retval = tms9914_read(board, tms_priv, buffer, length, end, &num_bytes);
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*bytes_read += num_bytes;
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if (retval < 0)
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@ -169,7 +171,7 @@ static int agilent_82350b_accel_write(struct gpib_board *board, u8 *buffer,
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event_status = read_and_clear_event_status(board);
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#ifdef EXPERIMENTAL
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// wait for previous BO to complete if any
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/* wait for previous BO to complete if any */
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retval = wait_event_interruptible(board->wait,
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test_bit(DEV_CLEAR_BN, &tms_priv->state) ||
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test_bit(WRITE_READY_BN, &tms_priv->state) ||
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@ -192,7 +194,7 @@ static int agilent_82350b_accel_write(struct gpib_board *board, u8 *buffer,
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block_size = min(fifotransferlength - i, agilent_82350b_fifo_size);
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set_transfer_counter(a_priv, block_size);
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for (j = 0; j < block_size; ++j, ++i) {
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// load data into board's sram
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/* load data into board's sram */
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writeb(buffer[i], a_priv->sram_base + j);
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}
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writeb(ENABLE_TI_TO_SRAM, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
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@ -262,7 +264,7 @@ static irqreturn_t agilent_82350b_interrupt(int irq, void *arg)
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tms9914_interrupt_have_status(board, &a_priv->tms9914_priv, tms9914_status1,
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tms9914_status2);
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}
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//write-clear status bits
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/* write-clear status bits */
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if (event_status & (BUFFER_END_STATUS_BIT | TERM_COUNT_STATUS_BIT)) {
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writeb(event_status & (BUFFER_END_STATUS_BIT | TERM_COUNT_STATUS_BIT),
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a_priv->gpib_base + EVENT_STATUS_REG);
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@ -292,11 +294,11 @@ static void set_transfer_counter(struct agilent_82350b_priv *a_priv, int count)
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writeb(complement & 0xff, a_priv->gpib_base + XFER_COUNT_LO_REG);
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writeb((complement >> 8) & 0xff, a_priv->gpib_base + XFER_COUNT_MID_REG);
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//I don't think the hi count reg is even used, but oh well
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/* I don't think the hi count reg is even used, but oh well */
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writeb((complement >> 16) & 0xf, a_priv->gpib_base + XFER_COUNT_HI_REG);
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}
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// wrappers for interface functions
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/* wrappers for interface functions */
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static int agilent_82350b_read(struct gpib_board *board, u8 *buffer,
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size_t length, int *end, size_t *bytes_read)
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{
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@ -511,18 +513,18 @@ static int init_82350a_hardware(struct gpib_board *board,
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PLX9050_PCI_RETRY_DELAY_BITS(64) |
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PLX9050_DIRECT_SLAVE_LOCK_ENABLE_BIT;
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// load borg data
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/* load borg data */
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borg_status = readb(a_priv->borg_base);
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if ((borg_status & BORG_DONE_BIT))
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return 0;
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// need to programme borg
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/* need to programme borg */
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if (!config->init_data || config->init_data_length != firmware_length) {
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dev_err(board->gpib_dev, "the 82350A board requires firmware after powering on.\n");
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return -EIO;
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}
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dev_dbg(board->gpib_dev, "Loading firmware...\n");
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// tickle the borg
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/* tickle the borg */
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writel(plx_cntrl_static_bits | PLX9050_USER3_DATA_BIT,
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a_priv->plx_base + PLX9050_CNTRL_REG);
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usleep_range(1000, 2000);
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@ -563,7 +565,7 @@ static int test_sram(struct gpib_board *board)
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struct agilent_82350b_priv *a_priv = board->private_data;
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unsigned int i;
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const unsigned int sram_length = pci_resource_len(a_priv->pci_device, SRAM_82350A_REGION);
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// test SRAM
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/* test SRAM */
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const unsigned int byte_mask = 0xff;
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for (i = 0; i < sram_length; ++i) {
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@ -606,7 +608,7 @@ static int agilent_82350b_generic_attach(struct gpib_board *board,
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tms_priv->write_byte = tms9914_iomem_write_byte;
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tms_priv->offset = 1;
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// find board
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/* find board */
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a_priv->pci_device = gpib_pci_get_device(config, PCI_VENDOR_ID_AGILENT,
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PCI_DEVICE_ID_82350B, NULL);
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if (a_priv->pci_device) {
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@ -702,7 +704,7 @@ static int agilent_82350b_generic_attach(struct gpib_board *board,
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writeb(a_priv->card_mode_bits, a_priv->gpib_base + CARD_MODE_REG);
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if (a_priv->model == MODEL_82350A) {
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// enable PCI interrupts for 82350a
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/* enable PCI interrupts for 82350a */
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writel(PLX9050_LINTR1_EN_BIT | PLX9050_LINTR2_POLARITY_BIT |
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PLX9050_PCI_INTR_EN_BIT,
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a_priv->plx_base + PLX9050_INTCSR_REG);
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@ -713,7 +715,7 @@ static int agilent_82350b_generic_attach(struct gpib_board *board,
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a_priv->gpib_base + EVENT_ENABLE_REG);
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writeb(ENABLE_TERM_COUNT_INTERRUPT_BIT | ENABLE_BUFFER_END_INTERRUPT_BIT |
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ENABLE_TMS9914_INTERRUPTS_BIT, a_priv->gpib_base + INTERRUPT_ENABLE_REG);
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//write-clear event status bits
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/* write-clear event status bits */
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writeb(BUFFER_END_STATUS_BIT | TERM_COUNT_STATUS_BIT,
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a_priv->gpib_base + EVENT_STATUS_REG);
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} else {
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@ -747,7 +749,7 @@ static void agilent_82350b_detach(struct gpib_board *board)
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struct tms9914_priv *tms_priv;
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if (a_priv) {
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if (a_priv->plx_base) // disable interrupts
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if (a_priv->plx_base) /* disable interrupts */
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writel(0, a_priv->plx_base + PLX9050_INTCSR_REG);
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tms_priv = &a_priv->tms9914_priv;
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@ -790,7 +792,7 @@ static struct gpib_interface agilent_82350b_unaccel_interface = {
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.parallel_poll = agilent_82350b_parallel_poll,
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.parallel_poll_configure = agilent_82350b_parallel_poll_configure,
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.parallel_poll_response = agilent_82350b_parallel_poll_response,
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.local_parallel_poll_mode = NULL, // XXX
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.local_parallel_poll_mode = NULL, /* XXX */
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.line_status = agilent_82350b_line_status,
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.update_status = agilent_82350b_update_status,
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.primary_address = agilent_82350b_primary_address,
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@ -818,7 +820,7 @@ static struct gpib_interface agilent_82350b_interface = {
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.parallel_poll = agilent_82350b_parallel_poll,
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.parallel_poll_configure = agilent_82350b_parallel_poll_configure,
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.parallel_poll_response = agilent_82350b_parallel_poll_response,
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.local_parallel_poll_mode = NULL, // XXX
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.local_parallel_poll_mode = NULL, /* XXX */
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.line_status = agilent_82350b_line_status,
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.update_status = agilent_82350b_update_status,
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.primary_address = agilent_82350b_primary_address,
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@ -41,11 +41,11 @@ enum board_model {
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MODEL_82351A
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};
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// struct which defines private_data for board
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/* struct which defines private_data for board */
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struct agilent_82350b_priv {
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struct tms9914_priv tms9914_priv;
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struct pci_dev *pci_device;
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void __iomem *plx_base; //82350a only
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void __iomem *plx_base; /* 82350a only */
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void __iomem *gpib_base;
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void __iomem *sram_base;
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void __iomem *misc_base;
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@ -57,12 +57,12 @@ struct agilent_82350b_priv {
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bool using_fifos;
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};
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//registers
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/* registers */
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enum agilent_82350b_gpib_registers
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{
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CARD_MODE_REG = 0x1,
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CONFIG_DATA_REG = 0x2, // 82350A specific
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CONFIG_DATA_REG = 0x2, /* 82350A specific */
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INTERRUPT_ENABLE_REG = 0x3,
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EVENT_STATUS_REG = 0x4,
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EVENT_ENABLE_REG = 0x5,
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@ -76,8 +76,8 @@ enum agilent_82350b_gpib_registers
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XFER_COUNT_HI_REG = 0xe,
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TMS9914_BASE_REG = 0x10,
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INTERNAL_CONFIG_REG = 0x18,
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IMR0_READ_REG = 0x19, //read
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T1_DELAY_REG = 0x19, // write
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IMR0_READ_REG = 0x19, /* read */
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T1_DELAY_REG = 0x19, /* write */
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IMR1_READ_REG = 0x1a,
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ADR_READ_REG = 0x1b,
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SPMR_READ_REG = 0x1c,
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@ -89,7 +89,7 @@ enum agilent_82350b_gpib_registers
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enum card_mode_bits
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{
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ACTIVE_CONTROLLER_BIT = 0x2, // read-only
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ACTIVE_CONTROLLER_BIT = 0x2, /* read-only */
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CM_SYSTEM_CONTROLLER_BIT = 0x8,
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ENABLE_BUS_MONITOR_BIT = 0x10,
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ENABLE_PCI_IRQ_BIT = 0x20,
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@ -115,15 +115,15 @@ enum event_status_bits
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{
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TMS9914_IRQ_STATUS_BIT = 0x1,
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IRQ_STATUS_BIT = 0x2,
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BUFFER_END_STATUS_BIT = 0x10, // write-clear
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TERM_COUNT_STATUS_BIT = 0x20, // write-clear
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BUFFER_END_STATUS_BIT = 0x10, /* write-clear */
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TERM_COUNT_STATUS_BIT = 0x20, /* write-clear */
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};
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enum stream_status_bits
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{
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HALTED_STATUS_BIT = 0x1, //read
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RESTART_STREAM_BIT = 0x1, //write
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HALTED_STATUS_BIT = 0x1, /* read */
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RESTART_STREAM_BIT = 0x1, /* write */
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};
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enum internal_config_bits
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@ -135,9 +135,9 @@ enum internal_config_bits
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enum sram_access_control_bits
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{
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DIRECTION_GPIB_TO_HOST = 0x20, // transfer direction
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ENABLE_TI_TO_SRAM = 0x40, // enable fifo
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ENABLE_FAST_TALKER = 0x80 // added for 82350A (not used)
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DIRECTION_GPIB_TO_HOST = 0x20, /* transfer direction */
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ENABLE_TI_TO_SRAM = 0x40, /* enable fifo */
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ENABLE_FAST_TALKER = 0x80 /* added for 82350A (not used) */
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};
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enum borg_bits
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