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pwm: mediatek: Simplify representation of channel offsets

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The general register layout contains some per-chip registers starting at
offset 0 and then at a higher address there are n nearly identical and
equidistant blocks for the registers of the n channels.

This allows to represent the offsets of per-channel registers as $base +
i * $width instead of listing all (or too many) offsets explicitly in an
array. So for a small additional effort in pwm_mediatek_writel() the
three arrays with the channel offsets can be dropped.

The size changes according to bloat-o-meter are:

	add/remove: 0/3 grow/shrink: 1/0 up/down: 12/-96 (-84)
	Function                                     old     new   delta
	pwm_mediatek_apply                           696     708     +12
	mtk_pwm_reg_offset_v3                         32       -     -32
	mtk_pwm_reg_offset_v2                         32       -     -32
	mtk_pwm_reg_offset_v1                         32       -     -32
	Total: Before=5347, After=5263, chg -1.57%

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250725154506.2610172-11-u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
This commit is contained in:
Uwe Kleine-König 2025-07-25 17:45:05 +02:00 committed by Uwe Kleine-König
parent a2f77ae477
commit c95ab56a7a
1 changed files with 30 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
drivers/pwm/pwm-mediatek.c
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@ -38,7 +38,8 @@ struct pwm_mediatek_of_data {
unsigned int num_pwms;
bool pwm45_fixup;
u16 pwm_ck_26m_sel_reg;
const unsigned int *reg_offset;
unsigned int chanreg_base;
unsigned int chanreg_width;
};
/**
@ -57,19 +58,6 @@ struct pwm_mediatek_chip {
const struct pwm_mediatek_of_data *soc;
};
static const unsigned int mtk_pwm_reg_offset_v1[] = {
0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};
static const unsigned int mtk_pwm_reg_offset_v2[] = {
0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
};
/* PWM IP Version 3.0.2 */
static const unsigned int mtk_pwm_reg_offset_v3[] = {
0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700, 0x0800
};
static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip)
{
@ -118,7 +106,8 @@ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
unsigned int num, unsigned int offset,
u32 value)
{
writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
writel(value, chip->regs + chip->soc->chanreg_base +
num * chip->soc->chanreg_width + offset);
}
static void pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
@ -303,86 +292,99 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
static const struct pwm_mediatek_of_data mt2712_pwm_data = {
.num_pwms = 8,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt6795_pwm_data = {
.num_pwms = 7,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7622_pwm_data = {
.num_pwms = 6,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7623_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = true,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7628_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = true,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7629_pwm_data = {
.num_pwms = 1,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7981_pwm_data = {
.num_pwms = 3,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v2,
.chanreg_base = 0x80,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7986_pwm_data = {
.num_pwms = 2,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7988_pwm_data = {
.num_pwms = 8,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v2,
.chanreg_base = 0x80,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt8183_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt8365_pwm_data = {
.num_pwms = 3,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt8516_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt6991_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3,
.reg_offset = mtk_pwm_reg_offset_v3,
.chanreg_base = 0x100,
.chanreg_width = 0x100,
};
static const struct of_device_id pwm_mediatek_of_match[] = {