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Merge branch 'pci/controller/rzg3s-host'
- Add Renesas RZ/G3S host controller DT binding and driver (Claudiu Beznea) * pci/controller/rzg3s-host: PCI: Add Renesas RZ/G3S host controller driver dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding
This commit is contained in:
Bjorn Helgaas
commit
c934541253
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@ -0,0 +1,249 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G3S PCIe host controller
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maintainers:
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- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
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description:
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Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
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4.0 and supports up to 5 GT/s (Gen2).
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properties:
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compatible:
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const: renesas,r9a08g045-pcie # RZ/G3S
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: System error interrupt
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- description: System error on correctable error interrupt
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- description: System error on non-fatal error interrupt
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- description: System error on fatal error interrupt
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- description: AXI error interrupt
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- description: INTA interrupt
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- description: INTB interrupt
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- description: INTC interrupt
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- description: INTD interrupt
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- description: MSI interrupt
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- description: Link bandwidth interrupt
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- description: PME interrupt
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- description: DMA interrupt
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- description: PCIe event interrupt
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- description: Message interrupt
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- description: All interrupts
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interrupt-names:
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items:
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- description: serr
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- description: ser_cor
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- description: serr_nonfatal
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- description: serr_fatal
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- description: axi_err
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- description: inta
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- description: intb
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- description: intc
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- description: intd
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- description: msi
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- description: link_bandwidth
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- description: pm_pme
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- description: dma
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- description: pcie_evt
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- description: msg
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- description: all
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interrupt-controller: true
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clocks:
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items:
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- description: System clock
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- description: PM control clock
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clock-names:
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items:
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- description: aclk
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- description: pm
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resets:
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items:
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- description: AXI2PCIe Bridge reset
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- description: Data link layer/transaction layer reset
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- description: Transaction layer (ACLK domain) reset
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- description: Transaction layer (PCLK domain) reset
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- description: Physical layer reset
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- description: Configuration register reset
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- description: Configuration register reset
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reset-names:
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items:
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- description: aresetn
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- description: rst_b
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- description: rst_gp_b
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- description: rst_ps_b
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- description: rst_rsm_b
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- description: rst_cfg_b
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- description: rst_load_b
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power-domains:
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maxItems: 1
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dma-ranges:
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description:
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A single range for the inbound memory region.
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maxItems: 1
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renesas,sysc:
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description: |
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System controller registers control and monitor various PCIe
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functionalities.
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Control:
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- transition to L1 state
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- receiver termination settings
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- RST_RSM_B signal
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Monitor:
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- clkl1pm clock request state
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- power off information in L2 state
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- errors (fatal, non-fatal, correctable)
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$ref: /schemas/types.yaml#/definitions/phandle
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patternProperties:
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"^pcie@0,[0-0]$":
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type: object
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allOf:
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- $ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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vendor-id:
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const: 0x1912
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device-id:
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const: 0x0033
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clocks:
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items:
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- description: Reference clock
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clock-names:
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items:
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- const: ref
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required:
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- device_type
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- vendor-id
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- device-id
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- clocks
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- clock-names
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- interrupts
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- interrupt-names
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- interrupt-map
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- interrupt-map-mask
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- interrupt-controller
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- power-domains
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- "#address-cells"
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- "#size-cells"
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- "#interrupt-cells"
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- renesas,sysc
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a08g045-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@11e40000 {
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compatible = "renesas,r9a08g045-pcie";
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reg = <0 0x11e40000 0 0x10000>;
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ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
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/* Map all possible DRAM ranges (4 GB). */
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
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bus-range = <0x0 0xff>;
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interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "serr", "serr_cor", "serr_nonfatal",
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"serr_fatal", "axi_err", "inta",
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"intb", "intc", "intd", "msi",
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"link_bandwidth", "pm_pme", "dma",
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"pcie_evt", "msg", "all";
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
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<0 0 0 2 &pcie 0 0 0 1>, /* INTB */
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<0 0 0 3 &pcie 0 0 0 2>, /* INTC */
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<0 0 0 4 &pcie 0 0 0 3>; /* INTD */
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clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,
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<&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;
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clock-names = "aclk", "pm";
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resets = <&cpg R9A08G045_PCI_ARESETN>,
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<&cpg R9A08G045_PCI_RST_B>,
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<&cpg R9A08G045_PCI_RST_GP_B>,
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<&cpg R9A08G045_PCI_RST_PS_B>,
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<&cpg R9A08G045_PCI_RST_RSM_B>,
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<&cpg R9A08G045_PCI_RST_CFG_B>,
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<&cpg R9A08G045_PCI_RST_LOAD_B>;
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reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",
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"rst_rsm_b", "rst_cfg_b", "rst_load_b";
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power-domains = <&cpg>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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renesas,sysc = <&sysc>;
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pcie@0,0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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ranges;
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clocks = <&versa3 5>;
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clock-names = "ref";
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device_type = "pci";
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vendor-id = <0x1912>;
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device-id = <0x0033>;
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#address-cells = <3>;
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#size-cells = <2>;
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};
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};
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};
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...
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@ -20007,6 +20007,14 @@ S: Maintained
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F: drivers/pci/controller/dwc/pcie-qcom-common.c
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F: drivers/pci/controller/dwc/pcie-qcom.c
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PCIE DRIVER FOR RENESAS RZ/G3S SERIES
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M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
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L: linux-pci@vger.kernel.org
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L: linux-renesas-soc@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
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F: drivers/pci/controller/pcie-rzg3s-host.c
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PCIE DRIVER FOR ROCKCHIP
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M: Shawn Lin <shawn.lin@rock-chips.com>
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L: linux-pci@vger.kernel.org
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@ -265,6 +265,15 @@ config PCI_RCAR_GEN2
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Each internal PCI controller contains a single built-in EHCI/OHCI
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host controller.
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config PCIE_RENESAS_RZG3S_HOST
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bool "Renesas RZ/G3S PCIe host controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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select MFD_SYSCON
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select IRQ_MSI_LIB
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help
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Say Y here if you want PCIe host controller support on Renesas RZ/G3S
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SoC.
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config PCIE_ROCKCHIP
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bool
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depends on PCI
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@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
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obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
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obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
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obj-$(CONFIG_PCIE_RENESAS_RZG3S_HOST) += pcie-rzg3s-host.o
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obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
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obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
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obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
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1761
drivers/pci/controller/pcie-rzg3s-host.c
Normal file
1761
drivers/pci/controller/pcie-rzg3s-host.c
Normal file
File diff suppressed because it is too large
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