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drm/scdc-helper: Implement parsing and printing HDMI 2.1 fields
HDMI 2.1 redefines previously reserved fields in SCDC for various new uses. No version check needs to be performed, as an HDMI 2.0 sink's reserved SCDC fields are well-defined to be 0, and any zero-ness of these fields for an HDMI 2.0 sink is not a surprise for SCDC parsers for HDMI 2.1. Implement reading and outputting these fields over debugfs. Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Tested-by: Hans Verkuil <hverkuil+cisco@kernel.org> Link: https://patch.msgid.link/20260724-scdc-link-health-v9-3-bdda406d016d@collabora.com Signed-off-by: Daniel Stone <daniels@collabora.com>
This commit is contained in:
Nicolas Frattaroli
Daniel Stone
parent
6c5121962e
commit
c8faf89e97
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@ -21,6 +21,7 @@
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/bitfield.h>
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#include <linux/export.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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@ -57,6 +58,38 @@
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#define SCDC_I2C_SLAVE_ADDRESS 0x54
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static const char *drm_scdc_frl_rate_str(enum drm_scdc_frl_rate rate)
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{
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switch (rate) {
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case SCDC_FRL_RATE_OFF:
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return "Off";
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case SCDC_FRL_RATE_3X3:
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return "3 Gbit/s x 3 lanes";
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case SCDC_FRL_RATE_6X3:
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return "6 Gbit/s x 3 lanes";
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case SCDC_FRL_RATE_6X4:
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return "6 Gbit/s x 4 lanes";
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case SCDC_FRL_RATE_8X4:
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return "8 Gbit/s x 4 lanes";
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case SCDC_FRL_RATE_10X4:
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return "10 Gbit/s x 4 lanes";
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case SCDC_FRL_RATE_12X4:
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return "12 Gbit/s x 4 lanes";
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case SCDC_FRL_RATE_RESV_7:
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case SCDC_FRL_RATE_RESV_8:
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case SCDC_FRL_RATE_RESV_9:
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case SCDC_FRL_RATE_RESV_10:
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case SCDC_FRL_RATE_RESV_11:
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case SCDC_FRL_RATE_RESV_12:
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case SCDC_FRL_RATE_RESV_13:
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case SCDC_FRL_RATE_RESV_14:
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case SCDC_FRL_RATE_RESV_15:
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return "(Reserved)";
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default:
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return NULL;
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}
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}
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/**
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* drm_scdc_read - read a block of data from SCDC
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* @adapter: I2C controller
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@ -286,14 +319,41 @@ drm_scdc_parse_status0_flags(u8 val, struct drm_scdc_status_flags *flags)
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flags->ch0_locked = val & SCDC_CH0_LOCK;
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flags->ch1_locked = val & SCDC_CH1_LOCK;
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flags->ch2_locked = val & SCDC_CH2_LOCK;
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flags->ln3_locked = val & SCDC_LN3_LOCK;
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flags->flt_ready = val & SCDC_FLT_READY;
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flags->dsc_fail = val & SCDC_DSC_FAIL;
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}
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static int drm_scdc_parse_error_counters(const u8 scdc[256], u16 counter[3])
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static void
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drm_scdc_parse_status1_2_flags(u8 val_flag1, u8 val_flag2,
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struct drm_scdc_status_flags *flags)
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{
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flags->ln0_training_pattern = FIELD_GET(SCDC_LN_EVEN_TRAIN_PTRN, val_flag1);
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flags->ln1_training_pattern = FIELD_GET(SCDC_LN_ODD_TRAIN_PTRN, val_flag1);
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flags->ln2_training_pattern = FIELD_GET(SCDC_LN_EVEN_TRAIN_PTRN, val_flag2);
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flags->ln3_training_pattern = FIELD_GET(SCDC_LN_ODD_TRAIN_PTRN, val_flag2);
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}
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static int drm_scdc_parse_error_counters(const u8 scdc[256], u16 counter[4],
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unsigned int num_lanes)
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{
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u8 end_reg;
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u8 sum = 0;
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int i;
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for (i = SCDC_ERR_DET_0_L; i <= SCDC_ERR_DET_CHECKSUM ; i++)
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switch (num_lanes) {
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case 3:
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end_reg = SCDC_ERR_DET_CHECKSUM;
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break;
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case 4:
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end_reg = SCDC_ERR_DET_3_H;
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break;
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default:
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return -EINVAL;
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}
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for (i = SCDC_ERR_DET_0_L; i <= end_reg; i++)
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sum = wrapping_add(u8, sum, scdc[i]);
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if (sum)
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@ -308,6 +368,12 @@ static int drm_scdc_parse_error_counters(const u8 scdc[256], u16 counter[3])
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counter[i] = 0;
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}
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if (num_lanes == 4 && scdc[SCDC_ERR_DET_3_H] & SCDC_CHANNEL_VALID)
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counter[3] = (scdc[SCDC_ERR_DET_3_H] & ~SCDC_CHANNEL_VALID) << 8 |
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scdc[SCDC_ERR_DET_3_L];
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else
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counter[3] = 0;
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return 0;
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}
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@ -325,6 +391,7 @@ int drm_scdc_read_state(struct drm_connector *connector, struct drm_scdc_state *
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struct i2c_adapter *ddc;
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struct drm_scdc *scdc;
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u8 *buf = state->scdc;
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int num_lanes;
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int ret;
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if (!state || !connector)
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@ -350,11 +417,26 @@ int drm_scdc_read_state(struct drm_connector *connector, struct drm_scdc_state *
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state->scrambling_detected = buf[SCDC_SCRAMBLER_STATUS] & SCDC_SCRAMBLING_STATUS;
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state->rate = FIELD_GET(SCDC_FRL_RATE, buf[SCDC_CONFIG_1]);
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num_lanes = drm_scdc_num_frl_lanes(state->rate);
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if (num_lanes < 0)
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return num_lanes;
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if (!num_lanes)
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num_lanes = 3;
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state->ffe_levels = FIELD_GET(SCDC_FFE_LEVELS, buf[SCDC_CONFIG_1]);
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drm_scdc_parse_status0_flags(buf[SCDC_STATUS_FLAGS_0], &state->stf);
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ret = drm_scdc_parse_error_counters(buf, state->error_count);
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drm_scdc_parse_status1_2_flags(buf[SCDC_STATUS_FLAGS_1],
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buf[SCDC_STATUS_FLAGS_2], &state->stf);
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ret = drm_scdc_parse_error_counters(buf, state->error_count, num_lanes);
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if (ret)
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return ret;
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if (state->rate && (buf[SCDC_ERR_DET_RS_H] & SCDC_CHANNEL_VALID))
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state->rs_corrections = (buf[SCDC_ERR_DET_RS_H] & ~SCDC_CHANNEL_VALID) << 8 |
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buf[SCDC_ERR_DET_RS_L];
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return 0;
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}
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EXPORT_SYMBOL(drm_scdc_read_state);
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@ -371,7 +453,7 @@ static int scdc_status_show(struct seq_file *m, void *data)
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struct drm_connector *connector = m->private;
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struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
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struct drm_scdc_state *st;
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int i, ret;
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int i, ret, frl_lanes;
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drm_connector_get(connector);
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@ -414,8 +496,12 @@ static int scdc_status_show(struct seq_file *m, void *data)
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drm_connector_put(connector);
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frl_lanes = drm_scdc_num_frl_lanes(st->rate);
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scdc_print_flag(m, "Scrambling Enabled", st->scrambling_enabled);
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scdc_print_flag(m, "Scrambling Detected", st->scrambling_detected);
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scdc_print_str(m, "FRL Rate", drm_scdc_frl_rate_str(st->rate));
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scdc_print_dec(m, "FFE Levels", st->ffe_levels);
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if (st->tmds_bclk_x40)
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scdc_print_str(m, "TMDS Bit Clock Ratio", "1/40");
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@ -426,10 +512,19 @@ static int scdc_status_show(struct seq_file *m, void *data)
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scdc_print_flag(m, "Channel 0 Locked", st->stf.ch0_locked);
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scdc_print_flag(m, "Channel 1 Locked", st->stf.ch1_locked);
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scdc_print_flag(m, "Channel 2 Locked", st->stf.ch2_locked);
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if (frl_lanes == 4)
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scdc_print_flag(m, "Lane 3 Locked", st->stf.ln3_locked);
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scdc_print_flag(m, "Sink Ready For Link Training", st->stf.flt_ready);
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scdc_print_flag(m, "Sink Failed To Decode DSC", st->stf.dsc_fail);
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scdc_print_dec(m, "Channel 0 Errors", st->error_count[0]);
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scdc_print_dec(m, "Channel 1 Errors", st->error_count[1]);
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scdc_print_dec(m, "Channel 2 Errors", st->error_count[2]);
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if (frl_lanes == 4)
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scdc_print_dec(m, "Lane 3 Errors", st->error_count[3]);
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if (frl_lanes > 0)
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scdc_print_dec(m, "Reed-Solomon Corrections", st->rs_corrections);
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kfree(st);
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@ -29,6 +29,8 @@
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#define SCDC_SOURCE_VERSION 0x02
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#define SCDC_UPDATE_0 0x10
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#define SCDC_RSED_UPDATE (1 << 6)
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#define SCDC_FLT_UPDATE (1 << 5)
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#define SCDC_READ_REQUEST_TEST (1 << 2)
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#define SCDC_CED_UPDATE (1 << 1)
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#define SCDC_STATUS_UPDATE (1 << 0)
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@ -46,14 +48,25 @@
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#define SCDC_CONFIG_0 0x30
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#define SCDC_READ_REQUEST_ENABLE (1 << 0)
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#define SCDC_CONFIG_1 0x31
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#define SCDC_FRL_RATE 0x0f
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#define SCDC_FFE_LEVELS 0xf0
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#define SCDC_STATUS_FLAGS_0 0x40
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#define SCDC_DSC_FAIL (1 << 7)
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#define SCDC_FLT_READY (1 << 6)
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#define SCDC_LN3_LOCK (1 << 4)
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#define SCDC_CH2_LOCK (1 << 3)
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#define SCDC_CH1_LOCK (1 << 2)
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#define SCDC_CH0_LOCK (1 << 1)
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#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
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#define SCDC_CH_LOCK_MASK (SCDC_LN3_LOCK | SCDC_CH2_LOCK | SCDC_CH1_LOCK | \
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SCDC_CH0_LOCK)
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#define SCDC_CLOCK_DETECT (1 << 0)
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#define SCDC_STATUS_FLAGS_1 0x41
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#define SCDC_LN_EVEN_TRAIN_PTRN 0x0f
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#define SCDC_LN_ODD_TRAIN_PTRN 0xf0
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#define SCDC_STATUS_FLAGS_2 0x42
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#define SCDC_ERR_DET_0_L 0x50
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#define SCDC_ERR_DET_0_H 0x51
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@ -65,6 +78,12 @@
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#define SCDC_ERR_DET_CHECKSUM 0x56
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#define SCDC_ERR_DET_3_L 0x57
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#define SCDC_ERR_DET_3_H 0x58
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#define SCDC_ERR_DET_RS_L 0x59
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#define SCDC_ERR_DET_RS_H 0x5a
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#define SCDC_TEST_CONFIG_0 0xc0
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#define SCDC_TEST_READ_REQUEST (1 << 7)
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#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
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@ -24,6 +24,7 @@
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#ifndef DRM_SCDC_HELPER_H
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#define DRM_SCDC_HELPER_H
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <drm/display/drm_scdc.h>
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@ -38,8 +39,65 @@ struct drm_scdc_status_flags {
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bool ch0_locked;
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bool ch1_locked;
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bool ch2_locked;
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bool ln3_locked;
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bool flt_ready;
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bool dsc_fail;
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/* Status Register 1 */
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u8 ln0_training_pattern : 4;
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u8 ln1_training_pattern : 4;
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/* Status Register 2 */
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u8 ln2_training_pattern : 4;
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u8 ln3_training_pattern : 4;
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};
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enum drm_scdc_frl_rate {
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SCDC_FRL_RATE_OFF = 0,
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SCDC_FRL_RATE_3X3 = 1,
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SCDC_FRL_RATE_6X3 = 2,
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SCDC_FRL_RATE_6X4 = 3,
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SCDC_FRL_RATE_8X4 = 4,
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SCDC_FRL_RATE_10X4 = 5,
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SCDC_FRL_RATE_12X4 = 6,
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SCDC_FRL_RATE_RESV_7 = 7,
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SCDC_FRL_RATE_RESV_8 = 8,
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SCDC_FRL_RATE_RESV_9 = 9,
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SCDC_FRL_RATE_RESV_10 = 10,
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SCDC_FRL_RATE_RESV_11 = 11,
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SCDC_FRL_RATE_RESV_12 = 12,
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SCDC_FRL_RATE_RESV_13 = 13,
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SCDC_FRL_RATE_RESV_14 = 14,
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SCDC_FRL_RATE_RESV_15 = 15
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};
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/**
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* drm_scdc_num_frl_lanes - get number of lanes for a given FRL rate
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* @rate: one of &enum drm_scdc_frl_rate
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*
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* For a given @rate, return the number of lanes it uses.
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*
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* Returns: %-EINVAL if @rate is not a valid FRL rate, or the number of lanes
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* for a given &enum drm_scdc_frl_rate on success (including %0 for "off")
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*/
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static inline __pure int drm_scdc_num_frl_lanes(enum drm_scdc_frl_rate rate)
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{
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switch (rate) {
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case SCDC_FRL_RATE_OFF:
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return 0;
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case SCDC_FRL_RATE_3X3:
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case SCDC_FRL_RATE_6X3:
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return 3;
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case SCDC_FRL_RATE_6X4:
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case SCDC_FRL_RATE_8X4:
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case SCDC_FRL_RATE_10X4:
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case SCDC_FRL_RATE_12X4:
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return 4;
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default:
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return -EINVAL;
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}
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}
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struct drm_scdc_state {
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/** @stf: contents of the status flag registers */
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struct drm_scdc_status_flags stf;
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@ -52,9 +110,14 @@ struct drm_scdc_state {
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* clock period, false if it's 1/10th of the clock period.
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*/
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bool tmds_bclk_x40;
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/** @error_count: character error counts for each channel */
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u16 error_count[3];
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/** @rate: FRL rate set by the source */
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enum drm_scdc_frl_rate rate : 4;
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/** @ffe_levels: The FFE levels for @rate set by the source */
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u8 ffe_levels : 4;
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/** @error_count: character error counts for each channel/link */
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u16 error_count[4];
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/** @rs_corrections: number of Reed-Solomon Corrections */
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u16 rs_corrections;
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/** @scdc: raw SCDC data buffer */
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u8 scdc[256];
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};
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