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perf arm_spe: Rename SPE_OP_PKT_IS_OTHER_SVE_OP macro

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Rename the macro to SPE_OP_PKT_OTHER_SUBCLASS_SVE to unify naming.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Leo Yan 2025-11-12 18:24:30 +00:00 committed by Namhyung Kim
parent b4eaece3d9
commit c8bf2a05df
3 changed files with 3 additions and 3 deletions
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2
tools/perf/util/arm-spe-decoder/arm-spe-decoder.c
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@ -205,7 +205,7 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder)
break; break;
case SPE_OP_PKT_HDR_CLASS_OTHER: case SPE_OP_PKT_HDR_CLASS_OTHER:
decoder->record.op |= ARM_SPE_OP_OTHER; decoder->record.op |= ARM_SPE_OP_OTHER;
if (SPE_OP_PKT_IS_OTHER_SVE_OP(payload)) if (SPE_OP_PKT_OTHER_SUBCLASS_SVE(payload))
decoder->record.op |= ARM_SPE_OP_SVE_OTHER; decoder->record.op |= ARM_SPE_OP_SVE_OTHER;
break; break;
case SPE_OP_PKT_HDR_CLASS_BR_ERET: case SPE_OP_PKT_HDR_CLASS_BR_ERET:

2
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
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@ -340,7 +340,7 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet,
switch (packet->index) { switch (packet->index) {
case SPE_OP_PKT_HDR_CLASS_OTHER: case SPE_OP_PKT_HDR_CLASS_OTHER:
if (SPE_OP_PKT_IS_OTHER_SVE_OP(payload)) { if (SPE_OP_PKT_OTHER_SUBCLASS_SVE(payload)) {
arm_spe_pkt_out_string(&err, &buf, &buf_len, "SVE-OTHER"); arm_spe_pkt_out_string(&err, &buf, &buf_len, "SVE-OTHER");
/* SVE effective vector length */ /* SVE effective vector length */

2
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
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@ -123,7 +123,7 @@ enum arm_spe_events {
#define SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC 0x1 #define SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC 0x1
#define SPE_OP_PKT_HDR_CLASS_BR_ERET 0x2 #define SPE_OP_PKT_HDR_CLASS_BR_ERET 0x2
#define SPE_OP_PKT_IS_OTHER_SVE_OP(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8) #define SPE_OP_PKT_OTHER_SUBCLASS_SVE(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8)
#define SPE_OP_PKT_LDST_SUBCLASS_GP_REG(v) (((v) & GENMASK_ULL(7, 1)) == 0x0) #define SPE_OP_PKT_LDST_SUBCLASS_GP_REG(v) (((v) & GENMASK_ULL(7, 1)) == 0x0)
#define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP(v) (((v) & GENMASK_ULL(7, 1)) == 0x4) #define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP(v) (((v) & GENMASK_ULL(7, 1)) == 0x4)