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ARM: dts: r8a73a4: Add L2 cache-controller nodes

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Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2016-02-15 21:38:29 +01:00 committed by Simon Horman
parent 57f9156bc6
commit c86a4b6219
1 changed files with 17 additions and 0 deletions
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17
arch/arm/boot/dts/r8a73a4.dtsi
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@ -29,6 +29,7 @@ cpu0: cpu@0 {
reg = <0>;
clock-frequency = <1500000000>;
power-domains = <&pd_a2sl>;
next-level-cache = <&L2_CA15>;
};
};
@ -45,6 +46,22 @@ timer {
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
L2_CA15: cache-controller@0 {
compatible = "cache";
clocks = <&cpg_clocks R8A73A4_CLK_Z>;
power-domains = <&pd_a3sm>;
cache-unified;
cache-level = <2>;
};
L2_CA7: cache-controller@1 {
compatible = "cache";
clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
power-domains = <&pd_a3km>;
cache-unified;
cache-level = <2>;
};
dbsc1: memory-controller@e6790000 {
compatible = "renesas,dbsc-r8a73a4";
reg = <0 0xe6790000 0 0x10000>;