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rk3368: clk: add codes to make npll only used by dclk_vop

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Signed-off-by: dkl <dkl@rock-chips.com>
This commit is contained in:
dkl 2014-11-12 15:15:59 +08:00 committed by Huang, Tao
parent 566db1b206
commit c83fb066be
3 changed files with 86 additions and 12 deletions
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30
arch/arm64/boot/dts/rk3368-clocks.dtsi
View File

@ -13,6 +13,8 @@
*/
#include <dt-bindings/clock/rockchip,rk3368.h>
/{
clocks {
compatible = "rockchip,rk-clocks";
@ -233,7 +235,7 @@ clk_npll: pll-clk@0050 {
status-reg = <0x0480 5>;
clocks = <&xin24m>;
clock-output-names = "clk_npll";
rockchip,pll-type = <CLK_PLL_3188PLUS>;
rockchip,pll-type = <CLK_PLL_3188PLUS_AUTO>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
@ -439,7 +441,7 @@ aclk_cci_div: aclk_cci_div {
clock-output-names = "aclk_cci";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
/* 5 reserved */
@ -490,6 +492,7 @@ hclk_bus: hclk_bus_div {
clock-output-names = "hclk_bus";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* 11:10 reserved */
@ -501,6 +504,7 @@ pclk_bus: pclk_bus_div {
clock-output-names = "pclk_bus";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
@ -598,6 +602,7 @@ clk_crypto: clk_crypto_div {
clock-output-names = "clk_crypto";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
@ -706,7 +711,7 @@ clk_gpu_core_div: clk_gpu_core_div {
clock-output-names = "clk_gpu_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
@ -755,7 +760,7 @@ aclk_vepu_div: aclk_vepu_div {
clock-output-names = "aclk_vepu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
/* 5 reserved */
@ -776,7 +781,7 @@ aclk_vdpu_div: aclk_vdpu_div {
clock-output-names = "aclk_vdpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
/* 13 reserved */
@ -820,7 +825,7 @@ clk_hevc_cabac_div: clk_hevc_cabac_div {
clock-output-names = "clk_hevc_cabac";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
/* 5 reserved */
@ -841,7 +846,7 @@ clk_hevc_core_div: clk_hevc_core_div {
clock-output-names = "clk_hevc_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
/* 13 reserved */
@ -947,6 +952,7 @@ dclk_vop0_div: dclk_vop0_div {
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
dclk_vop0: dclk_vop0_mux {
@ -1030,7 +1036,7 @@ clk_isp_div: clk_isp_div {
clock-output-names = "clk_isp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
clk_isp: clk_isp_mux {
@ -1056,7 +1062,7 @@ clk_edp_div: clk_edp_div {
clock-output-names = "clk_edp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
clk_edp: clk_edp_mux {
@ -1519,7 +1525,7 @@ clk_mac_pll_div: clk_mac_pll_div {
clock-output-names = "clk_mac_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
/* 5 reserved */
@ -1613,7 +1619,7 @@ clk_tsp_div: clk_tsp_div {
clock-output-names = "clk_tsp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
/* 5 reserved */
@ -1866,7 +1872,7 @@ clk_hdcp_div: clk_hdcp_div {
clock-output-names = "clk_hdcp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
};
clk_hdcp: clk_hdcp_mux {

67
drivers/clk/rockchip/clk-ops.c
View File

@ -714,6 +714,72 @@ const struct clk_ops clkops_rate_3288_dclk_lcdc1 = {
.recalc_rate = clk_divider_recalc_rate,
};
#define CONFIG_RK3368_MUX_NO_USE_NPLL
static long clk_3368_mux_div_determine_rate(struct clk_hw *div_hw,
unsigned long rate,
unsigned long *best_parent_rate,
struct clk **best_parent_p)
{
struct clk *clk = div_hw->clk, *parent = NULL, *best_parent = NULL;
int i, num_parents;
unsigned long parent_rate = 0, best_prate = 0, best = 0, now = 0;
parent = __clk_get_parent(clk);
if (!parent) {
best = __clk_get_rate(clk);
goto out;
}
/* if NO_REPARENT flag set, pass through to current parent */
if (clk->flags & CLK_SET_RATE_NO_REPARENT) {
best_prate = __clk_get_rate(parent);
best = clk_divider_ops.round_rate(div_hw, rate, &best_prate);
goto out;
}
/* find the parent that can provide the fastest rate <= rate */
num_parents = clk->num_parents;
for (i = 0; i < num_parents; i++) {
parent = clk_get_parent_by_index(clk, i);
if (!parent)
continue;
#ifdef CONFIG_RK3368_MUX_NO_USE_NPLL
if (!strcmp(__clk_get_name(parent), "clk_npll"))
continue;
#endif
parent_rate = __clk_get_rate(parent);
now = clk_divider_ops.round_rate(div_hw, rate, &parent_rate);
if (now <= rate && now > best) {
best_parent = parent;
best_prate = parent_rate;
best = now;
}
}
out:
if (best_prate)
*best_parent_rate = best_prate;
if (best_parent)
*best_parent_p = best_parent;
clk_debug("clk name = %s, determine rate = %lu, best = %lu\n"
"\tbest_parent name = %s, best_prate = %lu\n",
clk->name, rate, best,
__clk_get_name(*best_parent_p), *best_parent_rate);
return best;
}
const struct clk_ops clkops_rate_3368_auto_parent = {
.recalc_rate = clk_divider_recalc_rate,
.round_rate = clk_divider_round_rate,
.set_rate = clk_divider_set_rate,
.determine_rate = clk_3368_mux_div_determine_rate,
};
struct clk_ops_table rk_clkops_rate_table[] = {
{.index = CLKOPS_RATE_MUX_DIV, .clk_ops = &clkops_rate_auto_parent},
@ -730,6 +796,7 @@ struct clk_ops_table rk_clkops_rate_table[] = {
{.index = CLKOPS_RATE_RK3288_DCLK_LCDC1,.clk_ops = &clkops_rate_3288_dclk_lcdc1},
{.index = CLKOPS_RATE_DDR_DIV2, .clk_ops = &clkops_rate_ddr_div2},
{.index = CLKOPS_RATE_DDR_DIV4, .clk_ops = &clkops_rate_ddr_div4},
{.index = CLKOPS_RATE_RK3368_MUX_DIV_NPLL, .clk_ops = &clkops_rate_3368_auto_parent},
{.index = CLKOPS_RATE_I2S, .clk_ops = NULL},
{.index = CLKOPS_RATE_CIFOUT, .clk_ops = NULL},
{.index = CLKOPS_RATE_UART, .clk_ops = NULL},

1
include/dt-bindings/clock/rockchip.h
View File

@ -67,6 +67,7 @@
#define CLKOPS_RATE_RK3288_DCLK_LCDC1 17
#define CLKOPS_RATE_DDR_DIV2 18
#define CLKOPS_RATE_DDR_DIV4 19
#define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20
#define CLKOPS_TABLE_END (~0)
/* pd id */