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arm64: dts: rockchip: Fix gmac0 reset pin for NanoPi R5S

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According to the NanoPi R5S 2204 schematic on page 6, GPIO0_C4 is for
GMAC0_INT/PMEB_GPIO0_C4, while GPIO0_C5 is for GMAC0_RSTn_GPIO0_C5.
While the 'reset-gpios' property was set correctly, the corresponding
pinctrl didn't match that.

Next to fixing the pinctrl definition, also change the node name and
phandle to match what is used in the schematic.

Fixes: c6629b9a67 ("arm64: dts: rockchip: Add FriendlyElec Nanopi R5S")
Signed-off-by: Diederik de Haas <diederik@cknow-tech.com>
Link: https://patch.msgid.link/20260401131551.734456-2-diederik@cknow-tech.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Diederik de Haas 2026-04-01 15:11:38 +02:00 committed by Heiko Stuebner
parent ae653cb854
commit c83c4a09d4
1 changed files with 3 additions and 3 deletions
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6
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
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@ -98,7 +98,7 @@ &mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-0 = <&gmac0_rstn_gpio0_c5_pin>;
pinctrl-names = "default";
};
};
@ -132,8 +132,8 @@ &pcie3x2 {
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
gmac0_rstn_gpio0_c5_pin: gmac0-rstn-gpio0-c5-pin {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};