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arm64: dts: renesas: r9a08g045: Add USB support
Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20251023135810.1688415-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -727,6 +727,124 @@ eth1: ethernet@11c40000 {
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status = "disabled";
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};
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phyrst: usbphy-ctrl@11e00000 {
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compatible = "renesas,r9a08g045-usbphy-ctrl";
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reg = <0 0x11e00000 0 0x10000>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>;
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resets = <&cpg R9A08G045_USB_PRESETN>;
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power-domains = <&cpg>;
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#reset-cells = <1>;
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renesas,sysc-pwrrdy = <&sysc 0xd70 0x1>;
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status = "disabled";
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usb0_vbus_otg: regulator-vbus {
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regulator-name = "vbus";
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};
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};
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ohci0: usb@11e10000 {
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compatible = "generic-ohci";
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reg = <0 0x11e10000 0 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
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<&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
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resets = <&phyrst 0>,
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<&cpg R9A08G045_USB_U2H0_HRESETN>;
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phys = <&usb2_phy0 1>;
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phy-names = "usb";
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power-domains = <&cpg>;
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status = "disabled";
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};
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ohci1: usb@11e30000 {
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compatible = "generic-ohci";
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reg = <0 0x11e30000 0 0x100>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
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<&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
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resets = <&phyrst 1>,
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<&cpg R9A08G045_USB_U2H1_HRESETN>;
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phys = <&usb2_phy1 1>;
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phy-names = "usb";
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power-domains = <&cpg>;
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status = "disabled";
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};
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ehci0: usb@11e10100 {
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compatible = "generic-ehci";
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reg = <0 0x11e10100 0 0x100>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
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<&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
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resets = <&phyrst 0>,
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<&cpg R9A08G045_USB_U2H0_HRESETN>;
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phys = <&usb2_phy0 2>;
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phy-names = "usb";
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companion = <&ohci0>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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ehci1: usb@11e30100 {
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compatible = "generic-ehci";
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reg = <0 0x11e30100 0 0x100>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
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<&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
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resets = <&phyrst 1>,
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<&cpg R9A08G045_USB_U2H1_HRESETN>;
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phys = <&usb2_phy1 2>;
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phy-names = "usb";
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companion = <&ohci1>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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usb2_phy0: usb-phy@11e10200 {
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compatible = "renesas,usb2-phy-r9a08g045";
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reg = <0 0x11e10200 0 0x700>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
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<&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>;
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resets = <&phyrst 0>,
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<&cpg R9A08G045_USB_U2H0_HRESETN>;
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#phy-cells = <1>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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usb2_phy1: usb-phy@11e30200 {
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compatible = "renesas,usb2-phy-r9a08g045";
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reg = <0 0x11e30200 0 0x700>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
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<&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>;
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resets = <&phyrst 1>,
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<&cpg R9A08G045_USB_U2H1_HRESETN>;
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#phy-cells = <1>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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hsusb: usb@11e20000 {
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compatible = "renesas,usbhs-r9a08g045",
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"renesas,rzg2l-usbhs";
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reg = <0 0x11e20000 0 0x10000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>,
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<&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>;
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resets = <&phyrst 0>,
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<&cpg R9A08G045_USB_U2P_EXL_SYSRST>;
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renesas,buswait = <7>;
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phys = <&usb2_phy0 3>;
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phy-names = "usb";
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power-domains = <&cpg>;
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status = "disabled";
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};
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gic: interrupt-controller@12400000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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