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arm64: dts: layerscape: add msi-cell = <1> for gic its

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Add msi-cell = <1> for GIC ITS. msi-parent have to be kept because it is
checked by U-Boot due to historical reasons to fix up msi-map.

Fix below CHECK_DTBS warning:
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb: interrupt-controller@6000000: msi-controller@6020000: '#msi-cells' is a required property
        from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li 2024-07-29 14:59:28 -04:00 committed by Shawn Guo
parent 8b35a4acea
commit c7ad422f0e
4 changed files with 23 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -143,6 +143,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
};
};
@ -661,7 +662,7 @@ pcie1: pcie@3400000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
@ -700,7 +701,7 @@ pcie2: pcie@3500000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
@ -1079,7 +1080,7 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
reg = <0x01 0xf0000000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&its>;
msi-parent = <&its 0>;
device_type = "pci";
bus-range = <0x0 0x0>;
dma-coherent;

9
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -126,6 +126,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x6020000 0 0x20000>;
};
};
@ -575,7 +576,7 @@ pcie1: pcie@3400000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
@ -614,7 +615,7 @@ pcie2: pcie@3500000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
@ -652,7 +653,7 @@ pcie3: pcie@3600000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
@ -964,7 +965,7 @@ fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
msi-parent = <&its 0>;
iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
dma-coherent;
#address-cells = <3>;

11
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -63,6 +63,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x6020000 0 0x20000>;
};
};
@ -758,7 +759,7 @@ fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
msi-parent = <&its 0>;
iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
dma-coherent;
#address-cells = <3>;
@ -1085,7 +1086,7 @@ pcie1: pcie@3400000 {
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
@ -1107,7 +1108,7 @@ pcie2: pcie@3500000 {
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
@ -1129,7 +1130,7 @@ pcie3: pcie@3600000 {
dma-coherent;
num-viewport = <256>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
@ -1151,7 +1152,7 @@ pcie4: pcie@3700000 {
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,

15
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -398,6 +398,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x6020000 0 0x20000>;
};
};
@ -1181,7 +1182,7 @@ pcie1: pcie@3400000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
@ -1209,7 +1210,7 @@ pcie2: pcie@3500000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
@ -1237,7 +1238,7 @@ pcie3: pcie@3600000 {
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
@ -1265,7 +1266,7 @@ pcie4: pcie@3700000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
@ -1293,7 +1294,7 @@ pcie5: pcie@3800000 {
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
@ -1321,7 +1322,7 @@ pcie6: pcie@3900000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@ -1777,7 +1778,7 @@ fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
<0x00000000 0x08340000 0 0x40000>;
msi-parent = <&its>;
msi-parent = <&its 0>;
/* iommu-map property is fixed up by u-boot */
iommu-map = <0 &smmu 0 0>;
dma-coherent;