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RISC-V SpacemiT Reset for 6.17

Browse Source 
- Add reset driver support for K1 SoC
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Merge tag 'spacemit-reset-for-6.17-1' of https://github.com/spacemit-com/linux

RISC-V SpacemiT Reset for 6.17

- Add reset driver support for K1 SoC

* tag 'spacemit-reset-for-6.17-1':
  reset: spacemit: add support for SpacemiT CCU resets
  clk: spacemit: define three reset-only CCUs
  clk: spacemit: set up reset auxiliary devices
  soc: spacemit: create a header for clock/reset registers
  dt-bindings: soc: spacemit: define spacemit,k1-ccu resets

Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Yixun Lan 2025-07-07 22:07:15 +08:00
commit c79550f69f
8 changed files with 757 additions and 127 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
View File

@ -19,6 +19,9 @@ properties:
- spacemit,k1-syscon-apbc
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
- spacemit,k1-syscon-rcpu
- spacemit,k1-syscon-rcpu2
- spacemit,k1-syscon-apbc2
reg:
maxItems: 1
@ -47,9 +50,6 @@ properties:
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
- "#reset-cells"
allOf:
@ -57,13 +57,28 @@ allOf:
properties:
compatible:
contains:
const: spacemit,k1-syscon-apbc
enum:
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
then:
properties:
"#power-domain-cells": false
else:
required:
- "#power-domain-cells"
else:
properties:
"#power-domain-cells": false
- if:
properties:
compatible:
contains:
enum:
- spacemit,k1-syscon-apbc
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
then:
required:
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false

1
drivers/clk/spacemit/Kconfig
View File

@ -3,6 +3,7 @@
config SPACEMIT_CCU
tristate "Clock support for SpacemiT SoCs"
depends on ARCH_SPACEMIT || COMPILE_TEST
select AUXILIARY_BUS
select MFD_SYSCON
help
Say Y to enable clock controller unit support for SpacemiT SoCs.

239
drivers/clk/spacemit/ccu-k1.c
View File

@ -5,12 +5,16 @@
*/
#include <linux/array_size.h>
#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/idr.h>
#include <linux/mfd/syscon.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <soc/spacemit/k1-syscon.h>
#include "ccu_common.h"
#include "ccu_pll.h"
@ -19,121 +23,14 @@
#include <dt-bindings/clock/spacemit,k1-syscon.h>
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
#define APBS_PLL1_SWCR2 0x104
#define APBS_PLL1_SWCR3 0x108
#define APBS_PLL2_SWCR1 0x118
#define APBS_PLL2_SWCR2 0x11c
#define APBS_PLL2_SWCR3 0x120
#define APBS_PLL3_SWCR1 0x124
#define APBS_PLL3_SWCR2 0x128
#define APBS_PLL3_SWCR3 0x12c
/* MPMU register offset */
#define MPMU_POSR 0x0010
#define POSR_PLL1_LOCK BIT(27)
#define POSR_PLL2_LOCK BIT(28)
#define POSR_PLL3_LOCK BIT(29)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024
#define MPMU_APBCSCR 0x1050
#define MPMU_SUCCR_1 0x10b0
/* APBC register offset */
#define APBC_UART1_CLK_RST 0x00
#define APBC_UART2_CLK_RST 0x04
#define APBC_GPIO_CLK_RST 0x08
#define APBC_PWM0_CLK_RST 0x0c
#define APBC_PWM1_CLK_RST 0x10
#define APBC_PWM2_CLK_RST 0x14
#define APBC_PWM3_CLK_RST 0x18
#define APBC_TWSI8_CLK_RST 0x20
#define APBC_UART3_CLK_RST 0x24
#define APBC_RTC_CLK_RST 0x28
#define APBC_TWSI0_CLK_RST 0x2c
#define APBC_TWSI1_CLK_RST 0x30
#define APBC_TIMERS1_CLK_RST 0x34
#define APBC_TWSI2_CLK_RST 0x38
#define APBC_AIB_CLK_RST 0x3c
#define APBC_TWSI4_CLK_RST 0x40
#define APBC_TIMERS2_CLK_RST 0x44
#define APBC_ONEWIRE_CLK_RST 0x48
#define APBC_TWSI5_CLK_RST 0x4c
#define APBC_DRO_CLK_RST 0x58
#define APBC_IR_CLK_RST 0x5c
#define APBC_TWSI6_CLK_RST 0x60
#define APBC_COUNTER_CLK_SEL 0x64
#define APBC_TWSI7_CLK_RST 0x68
#define APBC_TSEN_CLK_RST 0x6c
#define APBC_UART4_CLK_RST 0x70
#define APBC_UART5_CLK_RST 0x74
#define APBC_UART6_CLK_RST 0x78
#define APBC_SSP3_CLK_RST 0x7c
#define APBC_SSPA0_CLK_RST 0x80
#define APBC_SSPA1_CLK_RST 0x84
#define APBC_IPC_AP2AUD_CLK_RST 0x90
#define APBC_UART7_CLK_RST 0x94
#define APBC_UART8_CLK_RST 0x98
#define APBC_UART9_CLK_RST 0x9c
#define APBC_CAN0_CLK_RST 0xa0
#define APBC_PWM4_CLK_RST 0xa8
#define APBC_PWM5_CLK_RST 0xac
#define APBC_PWM6_CLK_RST 0xb0
#define APBC_PWM7_CLK_RST 0xb4
#define APBC_PWM8_CLK_RST 0xb8
#define APBC_PWM9_CLK_RST 0xbc
#define APBC_PWM10_CLK_RST 0xc0
#define APBC_PWM11_CLK_RST 0xc4
#define APBC_PWM12_CLK_RST 0xc8
#define APBC_PWM13_CLK_RST 0xcc
#define APBC_PWM14_CLK_RST 0xd0
#define APBC_PWM15_CLK_RST 0xd4
#define APBC_PWM16_CLK_RST 0xd8
#define APBC_PWM17_CLK_RST 0xdc
#define APBC_PWM18_CLK_RST 0xe0
#define APBC_PWM19_CLK_RST 0xe4
/* APMU register offset */
#define APMU_JPG_CLK_RES_CTRL 0x020
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
#define APMU_ISP_CLK_RES_CTRL 0x038
#define APMU_LCD_CLK_RES_CTRL1 0x044
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
#define APMU_LCD_CLK_RES_CTRL2 0x04c
#define APMU_CCIC_CLK_RES_CTRL 0x050
#define APMU_SDH0_CLK_RES_CTRL 0x054
#define APMU_SDH1_CLK_RES_CTRL 0x058
#define APMU_USB_CLK_RES_CTRL 0x05c
#define APMU_QSPI_CLK_RES_CTRL 0x060
#define APMU_DMA_CLK_RES_CTRL 0x064
#define APMU_AES_CLK_RES_CTRL 0x068
#define APMU_VPU_CLK_RES_CTRL 0x0a4
#define APMU_GPU_CLK_RES_CTRL 0x0cc
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
#define APMU_PMUA_MC_CTRL 0x0e8
#define APMU_PMU_CC2_AP 0x100
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
#define APMU_CCI550_CLK_CTRL 0x300
#define APMU_ACLK_CLK_CTRL 0x388
#define APMU_CPU_C0_CLK_CTRL 0x38C
#define APMU_CPU_C1_CLK_CTRL 0x390
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
struct spacemit_ccu_data {
const char *reset_name;
struct clk_hw **hws;
size_t num;
};
static DEFINE_IDA(auxiliary_ids);
/* APBS clocks start, APBS region contains and only contains all PLL clocks */
/*
@ -820,8 +717,9 @@ static struct clk_hw *k1_ccu_pll_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_pll_data = {
.hws = k1_ccu_pll_hws,
.num = ARRAY_SIZE(k1_ccu_pll_hws),
/* The PLL CCU implements no resets */
.hws = k1_ccu_pll_hws,
.num = ARRAY_SIZE(k1_ccu_pll_hws),
};
static struct clk_hw *k1_ccu_mpmu_hws[] = {
@ -861,8 +759,9 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
.hws = k1_ccu_mpmu_hws,
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
.reset_name = "mpmu-reset",
.hws = k1_ccu_mpmu_hws,
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
};
static struct clk_hw *k1_ccu_apbc_hws[] = {
@ -969,8 +868,9 @@ static struct clk_hw *k1_ccu_apbc_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apbc_data = {
.hws = k1_ccu_apbc_hws,
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
.reset_name = "apbc-reset",
.hws = k1_ccu_apbc_hws,
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
};
static struct clk_hw *k1_ccu_apmu_hws[] = {
@ -1039,8 +939,21 @@ static struct clk_hw *k1_ccu_apmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apmu_data = {
.hws = k1_ccu_apmu_hws,
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
.reset_name = "apmu-reset",
.hws = k1_ccu_apmu_hws,
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
};
static const struct spacemit_ccu_data k1_ccu_rcpu_data = {
.reset_name = "rcpu-reset",
};
static const struct spacemit_ccu_data k1_ccu_rcpu2_data = {
.reset_name = "rcpu2-reset",
};
static const struct spacemit_ccu_data k1_ccu_apbc2_data = {
.reset_name = "apbc2-reset",
};
static int spacemit_ccu_register(struct device *dev,
@ -1051,6 +964,10 @@ static int spacemit_ccu_register(struct device *dev,
struct clk_hw_onecell_data *clk_data;
int i, ret;
/* Nothing to do if the CCU does not implement any clocks */
if (!data->hws)
return 0;
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
GFP_KERNEL);
if (!clk_data)
@ -1091,9 +1008,74 @@ static int spacemit_ccu_register(struct device *dev,
return ret;
}
static void spacemit_cadev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
ida_free(&auxiliary_ids, adev->id);
kfree(to_spacemit_ccu_adev(adev));
}
static void spacemit_adev_unregister(void *data)
{
struct auxiliary_device *adev = data;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
static int spacemit_ccu_reset_register(struct device *dev,
struct regmap *regmap,
const char *reset_name)
{
struct spacemit_ccu_adev *cadev;
struct auxiliary_device *adev;
int ret;
/* Nothing to do if the CCU does not implement a reset controller */
if (!reset_name)
return 0;
cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
if (!cadev)
return -ENOMEM;
cadev->regmap = regmap;
adev = &cadev->adev;
adev->name = reset_name;
adev->dev.parent = dev;
adev->dev.release = spacemit_cadev_release;
adev->dev.of_node = dev->of_node;
ret = ida_alloc(&auxiliary_ids, GFP_KERNEL);
if (ret < 0)
goto err_free_cadev;
adev->id = ret;
ret = auxiliary_device_init(adev);
if (ret)
goto err_free_aux_id;
ret = auxiliary_device_add(adev);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);
err_free_aux_id:
ida_free(&auxiliary_ids, adev->id);
err_free_cadev:
kfree(cadev);
return ret;
}
static int k1_ccu_probe(struct platform_device *pdev)
{
struct regmap *base_regmap, *lock_regmap = NULL;
const struct spacemit_ccu_data *data;
struct device *dev = &pdev->dev;
int ret;
@ -1122,11 +1104,16 @@ static int k1_ccu_probe(struct platform_device *pdev)
"failed to get lock regmap\n");
}
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap,
of_device_get_match_data(dev));
data = of_device_get_match_data(dev);
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data);
if (ret)
return dev_err_probe(dev, ret, "failed to register clocks\n");
ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name);
if (ret)
return dev_err_probe(dev, ret, "failed to register resets\n");
return 0;
}
@ -1147,6 +1134,18 @@ static const struct of_device_id of_k1_ccu_match[] = {
.compatible = "spacemit,k1-syscon-apmu",
.data = &k1_ccu_apmu_data,
},
{
.compatible = "spacemit,k1-syscon-rcpu",
.data = &k1_ccu_rcpu_data,
},
{
.compatible = "spacemit,k1-syscon-rcpu2",
.data = &k1_ccu_rcpu2_data,
},
{
.compatible = "spacemit,k1-syscon-apbc2",
.data = &k1_ccu_apbc2_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, of_k1_ccu_match);

9
drivers/reset/Kconfig
View File

@ -270,6 +270,15 @@ config RESET_SOCFPGA
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
config RESET_SPACEMIT
tristate "SpacemiT reset driver"
depends on ARCH_SPACEMIT || COMPILE_TEST
select AUXILIARY_BUS
default ARCH_SPACEMIT
help
This enables the reset controller driver for SpacemiT SoCs,
including the K1.
config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
default ARCH_SUNPLUS

1
drivers/reset/Makefile
View File

@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TH1520) += reset-th1520.o

304
drivers/reset/reset-spacemit.c Normal file
View File

@ -0,0 +1,304 @@
// SPDX-License-Identifier: GPL-2.0-only
/* SpacemiT reset controller driver */
#include <linux/auxiliary_bus.h>
#include <linux/container_of.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/types.h>
#include <soc/spacemit/k1-syscon.h>
#include <dt-bindings/clock/spacemit,k1-syscon.h>
struct ccu_reset_data {
u32 offset;
u32 assert_mask;
u32 deassert_mask;
};
struct ccu_reset_controller_data {
const struct ccu_reset_data *reset_data; /* array */
size_t count;
};
struct ccu_reset_controller {
struct reset_controller_dev rcdev;
const struct ccu_reset_controller_data *data;
struct regmap *regmap;
};
#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \
{ \
.offset = (_offset), \
.assert_mask = (_assert_mask), \
.deassert_mask = (_deassert_mask), \
}
static const struct ccu_reset_data k1_mpmu_resets[] = {
[RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
};
static const struct ccu_reset_controller_data k1_mpmu_reset_data = {
.reset_data = k1_mpmu_resets,
.count = ARRAY_SIZE(k1_mpmu_resets),
};
static const struct ccu_reset_data k1_apbc_resets[] = {
[RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
[RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
[RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
[RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)),
[RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
[RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
[RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
[RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
[RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
[RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
[RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
[RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
[RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
[RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
[RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
[RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0),
[RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
[RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
[RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
[RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
[RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
[RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
[RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0),
[RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
[RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
[RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
[RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
[RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
[RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
[RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
[RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
[RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
};
static const struct ccu_reset_controller_data k1_apbc_reset_data = {
.reset_data = k1_apbc_resets,
.count = ARRAY_SIZE(k1_apbc_resets),
};
static const struct ccu_reset_data k1_apmu_resets[] = {
[RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
[RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
[RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
[RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
[RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)),
[RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
[RESET_USB30_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
[RESET_USB30_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
[RESET_USB30_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
[RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
[RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
[RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
[RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
[RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
[RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
[RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)),
[RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)),
[RESET_AUDIO_SYS] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(0)),
[RESET_AUDIO_MCU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(2)),
[RESET_AUDIO_APMU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(3)),
[RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)),
[RESET_PCIE0_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(3)),
[RESET_PCIE0_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(4)),
[RESET_PCIE0_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(5)),
[RESET_PCIE0_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0),
[RESET_PCIE1_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(3)),
[RESET_PCIE1_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(4)),
[RESET_PCIE1_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(5)),
[RESET_PCIE1_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), 0),
[RESET_PCIE2_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(3)),
[RESET_PCIE2_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(4)),
[RESET_PCIE2_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(5)),
[RESET_PCIE2_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), 0),
[RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)),
[RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
[RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
[RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
[RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)),
[RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)),
[RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)),
[RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
[RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
[RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
[RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
[RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)),
[RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)),
[RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
[RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)),
[RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
};
static const struct ccu_reset_controller_data k1_apmu_reset_data = {
.reset_data = k1_apmu_resets,
.count = ARRAY_SIZE(k1_apmu_resets),
};
static const struct ccu_reset_data k1_rcpu_resets[] = {
[RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)),
[RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)),
[RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)),
[RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)),
[RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)),
[RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)),
[RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)),
};
static const struct ccu_reset_controller_data k1_rcpu_reset_data = {
.reset_data = k1_rcpu_resets,
.count = ARRAY_SIZE(k1_rcpu_resets),
};
static const struct ccu_reset_data k1_rcpu2_resets[] = {
[RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
};
static const struct ccu_reset_controller_data k1_rcpu2_reset_data = {
.reset_data = k1_rcpu2_resets,
.count = ARRAY_SIZE(k1_rcpu2_resets),
};
static const struct ccu_reset_data k1_apbc2_resets[] = {
[RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0),
[RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0),
[RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0),
[RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0),
[RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0),
[RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0),
[RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0),
};
static const struct ccu_reset_controller_data k1_apbc2_reset_data = {
.reset_data = k1_apbc2_resets,
.count = ARRAY_SIZE(k1_apbc2_resets),
};
static int spacemit_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct ccu_reset_controller *controller;
const struct ccu_reset_data *data;
u32 mask;
u32 val;
controller = container_of(rcdev, struct ccu_reset_controller, rcdev);
data = &controller->data->reset_data[id];
mask = data->assert_mask | data->deassert_mask;
val = assert ? data->assert_mask : data->deassert_mask;
return regmap_update_bits(controller->regmap, data->offset, mask, val);
}
static int spacemit_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return spacemit_reset_update(rcdev, id, true);
}
static int spacemit_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return spacemit_reset_update(rcdev, id, false);
}
static const struct reset_control_ops spacemit_reset_control_ops = {
.assert = spacemit_reset_assert,
.deassert = spacemit_reset_deassert,
};
static int spacemit_reset_controller_register(struct device *dev,
struct ccu_reset_controller *controller)
{
struct reset_controller_dev *rcdev = &controller->rcdev;
rcdev->ops = &spacemit_reset_control_ops;
rcdev->owner = THIS_MODULE;
rcdev->of_node = dev->of_node;
rcdev->nr_resets = controller->data->count;
return devm_reset_controller_register(dev, &controller->rcdev);
}
static int spacemit_reset_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev);
struct ccu_reset_controller *controller;
struct device *dev = &adev->dev;
controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
if (!controller)
return -ENOMEM;
controller->data = (const struct ccu_reset_controller_data *)id->driver_data;
controller->regmap = rdev->regmap;
return spacemit_reset_controller_register(dev, controller);
}
#define K1_AUX_DEV_ID(_unit) \
{ \
.name = "spacemit_ccu_k1." #_unit "-reset", \
.driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
}
static const struct auxiliary_device_id spacemit_reset_ids[] = {
K1_AUX_DEV_ID(mpmu),
K1_AUX_DEV_ID(apbc),
K1_AUX_DEV_ID(apmu),
K1_AUX_DEV_ID(rcpu),
K1_AUX_DEV_ID(rcpu2),
K1_AUX_DEV_ID(apbc2),
{ },
};
MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids);
static struct auxiliary_driver spacemit_k1_reset_driver = {
.probe = spacemit_reset_probe,
.id_table = spacemit_reset_ids,
};
module_auxiliary_driver(spacemit_k1_reset_driver);
MODULE_AUTHOR("Alex Elder <elder@kernel.org>");
MODULE_DESCRIPTION("SpacemiT reset controller driver");
MODULE_LICENSE("GPL");

141
include/dt-bindings/clock/spacemit,k1-syscon.h
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@ -78,6 +78,9 @@
#define CLK_APB 31
#define CLK_WDT_BUS 32
/* MPMU resets */
#define RESET_WDT 0
/* APBC clocks */
#define CLK_UART0 0
#define CLK_UART2 1
@ -180,6 +183,59 @@
#define CLK_TSEN_BUS 98
#define CLK_IPC_AP2AUD_BUS 99
/* APBC resets */
#define RESET_UART0 0
#define RESET_UART2 1
#define RESET_UART3 2
#define RESET_UART4 3
#define RESET_UART5 4
#define RESET_UART6 5
#define RESET_UART7 6
#define RESET_UART8 7
#define RESET_UART9 8
#define RESET_GPIO 9
#define RESET_PWM0 10
#define RESET_PWM1 11
#define RESET_PWM2 12
#define RESET_PWM3 13
#define RESET_PWM4 14
#define RESET_PWM5 15
#define RESET_PWM6 16
#define RESET_PWM7 17
#define RESET_PWM8 18
#define RESET_PWM9 19
#define RESET_PWM10 20
#define RESET_PWM11 21
#define RESET_PWM12 22
#define RESET_PWM13 23
#define RESET_PWM14 24
#define RESET_PWM15 25
#define RESET_PWM16 26
#define RESET_PWM17 27
#define RESET_PWM18 28
#define RESET_PWM19 29
#define RESET_SSP3 30
#define RESET_RTC 31
#define RESET_TWSI0 32
#define RESET_TWSI1 33
#define RESET_TWSI2 34
#define RESET_TWSI4 35
#define RESET_TWSI5 36
#define RESET_TWSI6 37
#define RESET_TWSI7 38
#define RESET_TWSI8 39
#define RESET_TIMERS1 40
#define RESET_TIMERS2 41
#define RESET_AIB 42
#define RESET_ONEWIRE 43
#define RESET_SSPA0 44
#define RESET_SSPA1 45
#define RESET_DRO 46
#define RESET_IR 47
#define RESET_TSEN 48
#define RESET_IPC_AP2AUD 49
#define RESET_CAN0 50
/* APMU clocks */
#define CLK_CCI550 0
#define CLK_CPU_C0_HI 1
@ -244,4 +300,89 @@
#define CLK_V2D 60
#define CLK_EMMC_BUS 61
/* APMU resets */
#define RESET_CCIC_4X 0
#define RESET_CCIC1_PHY 1
#define RESET_SDH_AXI 2
#define RESET_SDH0 3
#define RESET_SDH1 4
#define RESET_SDH2 5
#define RESET_USBP1_AXI 6
#define RESET_USB_AXI 7
#define RESET_USB30_AHB 8
#define RESET_USB30_VCC 9
#define RESET_USB30_PHY 10
#define RESET_QSPI 11
#define RESET_QSPI_BUS 12
#define RESET_DMA 13
#define RESET_AES 14
#define RESET_VPU 15
#define RESET_GPU 16
#define RESET_EMMC 17
#define RESET_EMMC_X 18
#define RESET_AUDIO_SYS 19
#define RESET_AUDIO_MCU 20
#define RESET_AUDIO_APMU 21
#define RESET_HDMI 22
#define RESET_PCIE0_MASTER 23
#define RESET_PCIE0_SLAVE 24
#define RESET_PCIE0_DBI 25
#define RESET_PCIE0_GLOBAL 26
#define RESET_PCIE1_MASTER 27
#define RESET_PCIE1_SLAVE 28
#define RESET_PCIE1_DBI 29
#define RESET_PCIE1_GLOBAL 30
#define RESET_PCIE2_MASTER 31
#define RESET_PCIE2_SLAVE 32
#define RESET_PCIE2_DBI 33
#define RESET_PCIE2_GLOBAL 34
#define RESET_EMAC0 35
#define RESET_EMAC1 36
#define RESET_JPG 37
#define RESET_CCIC2PHY 38
#define RESET_CCIC3PHY 39
#define RESET_CSI 40
#define RESET_ISP_CPP 41
#define RESET_ISP_BUS 42
#define RESET_ISP 43
#define RESET_ISP_CI 44
#define RESET_DPU_MCLK 45
#define RESET_DPU_ESC 46
#define RESET_DPU_HCLK 47
#define RESET_DPU_SPIBUS 48
#define RESET_DPU_SPI_HBUS 49
#define RESET_V2D 50
#define RESET_MIPI 51
#define RESET_MC 52
/* RCPU resets */
#define RESET_RCPU_SSP0 0
#define RESET_RCPU_I2C0 1
#define RESET_RCPU_UART1 2
#define RESET_RCPU_IR 3
#define RESET_RCPU_CAN 4
#define RESET_RCPU_UART0 5
#define RESET_RCPU_HDMI_AUDIO 6
/* RCPU2 resets */
#define RESET_RCPU2_PWM0 0
#define RESET_RCPU2_PWM1 1
#define RESET_RCPU2_PWM2 2
#define RESET_RCPU2_PWM3 3
#define RESET_RCPU2_PWM4 4
#define RESET_RCPU2_PWM5 5
#define RESET_RCPU2_PWM6 6
#define RESET_RCPU2_PWM7 7
#define RESET_RCPU2_PWM8 8
#define RESET_RCPU2_PWM9 9
/* APBC2 resets */
#define RESET_APBC2_UART1 0
#define RESET_APBC2_SSP2 1
#define RESET_APBC2_TWSI3 2
#define RESET_APBC2_RTC 3
#define RESET_APBC2_TIMERS0 4
#define RESET_APBC2_KPC 5
#define RESET_APBC2_GPIO 6
#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */

160
include/soc/spacemit/k1-syscon.h Normal file
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@ -0,0 +1,160 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* SpacemiT clock and reset driver definitions for the K1 SoC */
#ifndef __SOC_K1_SYSCON_H__
#define __SOC_K1_SYSCON_H__
/* Auxiliary device used to represent a CCU reset controller */
struct spacemit_ccu_adev {
struct auxiliary_device adev;
struct regmap *regmap;
};
static inline struct spacemit_ccu_adev *
to_spacemit_ccu_adev(struct auxiliary_device *adev)
{
return container_of(adev, struct spacemit_ccu_adev, adev);
}
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
#define APBS_PLL1_SWCR2 0x104
#define APBS_PLL1_SWCR3 0x108
#define APBS_PLL2_SWCR1 0x118
#define APBS_PLL2_SWCR2 0x11c
#define APBS_PLL2_SWCR3 0x120
#define APBS_PLL3_SWCR1 0x124
#define APBS_PLL3_SWCR2 0x128
#define APBS_PLL3_SWCR3 0x12c
/* MPMU register offset */
#define MPMU_POSR 0x0010
#define POSR_PLL1_LOCK BIT(27)
#define POSR_PLL2_LOCK BIT(28)
#define POSR_PLL3_LOCK BIT(29)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024
#define MPMU_APBCSCR 0x1050
#define MPMU_SUCCR_1 0x10b0
/* APBC register offset */
#define APBC_UART1_CLK_RST 0x00
#define APBC_UART2_CLK_RST 0x04
#define APBC_GPIO_CLK_RST 0x08
#define APBC_PWM0_CLK_RST 0x0c
#define APBC_PWM1_CLK_RST 0x10
#define APBC_PWM2_CLK_RST 0x14
#define APBC_PWM3_CLK_RST 0x18
#define APBC_TWSI8_CLK_RST 0x20
#define APBC_UART3_CLK_RST 0x24
#define APBC_RTC_CLK_RST 0x28
#define APBC_TWSI0_CLK_RST 0x2c
#define APBC_TWSI1_CLK_RST 0x30
#define APBC_TIMERS1_CLK_RST 0x34
#define APBC_TWSI2_CLK_RST 0x38
#define APBC_AIB_CLK_RST 0x3c
#define APBC_TWSI4_CLK_RST 0x40
#define APBC_TIMERS2_CLK_RST 0x44
#define APBC_ONEWIRE_CLK_RST 0x48
#define APBC_TWSI5_CLK_RST 0x4c
#define APBC_DRO_CLK_RST 0x58
#define APBC_IR_CLK_RST 0x5c
#define APBC_TWSI6_CLK_RST 0x60
#define APBC_COUNTER_CLK_SEL 0x64
#define APBC_TWSI7_CLK_RST 0x68
#define APBC_TSEN_CLK_RST 0x6c
#define APBC_UART4_CLK_RST 0x70
#define APBC_UART5_CLK_RST 0x74
#define APBC_UART6_CLK_RST 0x78
#define APBC_SSP3_CLK_RST 0x7c
#define APBC_SSPA0_CLK_RST 0x80
#define APBC_SSPA1_CLK_RST 0x84
#define APBC_IPC_AP2AUD_CLK_RST 0x90
#define APBC_UART7_CLK_RST 0x94
#define APBC_UART8_CLK_RST 0x98
#define APBC_UART9_CLK_RST 0x9c
#define APBC_CAN0_CLK_RST 0xa0
#define APBC_PWM4_CLK_RST 0xa8
#define APBC_PWM5_CLK_RST 0xac
#define APBC_PWM6_CLK_RST 0xb0
#define APBC_PWM7_CLK_RST 0xb4
#define APBC_PWM8_CLK_RST 0xb8
#define APBC_PWM9_CLK_RST 0xbc
#define APBC_PWM10_CLK_RST 0xc0
#define APBC_PWM11_CLK_RST 0xc4
#define APBC_PWM12_CLK_RST 0xc8
#define APBC_PWM13_CLK_RST 0xcc
#define APBC_PWM14_CLK_RST 0xd0
#define APBC_PWM15_CLK_RST 0xd4
#define APBC_PWM16_CLK_RST 0xd8
#define APBC_PWM17_CLK_RST 0xdc
#define APBC_PWM18_CLK_RST 0xe0
#define APBC_PWM19_CLK_RST 0xe4
/* APMU register offset */
#define APMU_JPG_CLK_RES_CTRL 0x020
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
#define APMU_ISP_CLK_RES_CTRL 0x038
#define APMU_LCD_CLK_RES_CTRL1 0x044
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
#define APMU_LCD_CLK_RES_CTRL2 0x04c
#define APMU_CCIC_CLK_RES_CTRL 0x050
#define APMU_SDH0_CLK_RES_CTRL 0x054
#define APMU_SDH1_CLK_RES_CTRL 0x058
#define APMU_USB_CLK_RES_CTRL 0x05c
#define APMU_QSPI_CLK_RES_CTRL 0x060
#define APMU_DMA_CLK_RES_CTRL 0x064
#define APMU_AES_CLK_RES_CTRL 0x068
#define APMU_VPU_CLK_RES_CTRL 0x0a4
#define APMU_GPU_CLK_RES_CTRL 0x0cc
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
#define APMU_PMUA_MC_CTRL 0x0e8
#define APMU_PMU_CC2_AP 0x100
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
#define APMU_CCI550_CLK_CTRL 0x300
#define APMU_ACLK_CLK_CTRL 0x388
#define APMU_CPU_C0_CLK_CTRL 0x38C
#define APMU_CPU_C1_CLK_CTRL 0x390
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
/* RCPU register offsets */
#define RCPU_SSP0_CLK_RST 0x0028
#define RCPU_I2C0_CLK_RST 0x0030
#define RCPU_UART1_CLK_RST 0x003c
#define RCPU_CAN_CLK_RST 0x0048
#define RCPU_IR_CLK_RST 0x004c
#define RCPU_UART0_CLK_RST 0x00d8
#define AUDIO_HDMI_CLK_CTRL 0x2044
/* RCPU2 register offsets */
#define RCPU2_PWM0_CLK_RST 0x0000
#define RCPU2_PWM1_CLK_RST 0x0004
#define RCPU2_PWM2_CLK_RST 0x0008
#define RCPU2_PWM3_CLK_RST 0x000c
#define RCPU2_PWM4_CLK_RST 0x0010
#define RCPU2_PWM5_CLK_RST 0x0014
#define RCPU2_PWM6_CLK_RST 0x0018
#define RCPU2_PWM7_CLK_RST 0x001c
#define RCPU2_PWM8_CLK_RST 0x0020
#define RCPU2_PWM9_CLK_RST 0x0024
/* APBC2 register offsets */
#define APBC2_UART1_CLK_RST 0x0000
#define APBC2_SSP2_CLK_RST 0x0004
#define APBC2_TWSI3_CLK_RST 0x0008
#define APBC2_RTC_CLK_RST 0x000c
#define APBC2_TIMERS0_CLK_RST 0x0010
#define APBC2_KPC_CLK_RST 0x0014
#define APBC2_GPIO_CLK_RST 0x001c
#endif /* __SOC_K1_SYSCON_H__ */