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watchdog: s3c2410_wdt: exynosautov920: Enable QUIRK_HAS_32BIT_CNT

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Enable QUIRK_HAS_32BIT_CNT to ExynosAutov920 SoC which has 32-bit WTCNT.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Sangwook Shin 2025-08-18 11:18:25 +09:00 committed by Wim Van Sebroeck
parent a36c90ab4d
commit c76c029ce5
1 changed files with 2 additions and 2 deletions
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4
drivers/watchdog/s3c2410_wdt.c
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@ -357,7 +357,7 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
.cnt_en_bit = 8,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
QUIRK_HAS_DBGACK_BIT,
QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT,
};
static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
@ -370,7 +370,7 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
.cnt_en_bit = 8,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
QUIRK_HAS_DBGACK_BIT,
QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT,
};
static const struct of_device_id s3c2410_wdt_match[] = {