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perf vendor events arm64: Drop hip08 PublicDescription if same as BriefDescription
If BriefDescription and PublicDescription are the same, only BriefDescription is needed. It will be used for both long and short format outputs. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Junhao He <hejunhao3@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@linaro.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20250418070812.3771441-3-hejunhao3@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -3,56 +3,48 @@
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"ConfigCode": "0x00",
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"EventName": "flux_wr",
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"BriefDescription": "DDRC total write operations",
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"PublicDescription": "DDRC total write operations",
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"Unit": "hisi_sccl,ddrc"
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},
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{
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"ConfigCode": "0x01",
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"EventName": "flux_rd",
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"BriefDescription": "DDRC total read operations",
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"PublicDescription": "DDRC total read operations",
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"Unit": "hisi_sccl,ddrc"
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},
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{
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"ConfigCode": "0x02",
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"EventName": "flux_wcmd",
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"BriefDescription": "DDRC write commands",
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"PublicDescription": "DDRC write commands",
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"Unit": "hisi_sccl,ddrc"
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},
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{
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"ConfigCode": "0x03",
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"EventName": "flux_rcmd",
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"BriefDescription": "DDRC read commands",
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"PublicDescription": "DDRC read commands",
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"Unit": "hisi_sccl,ddrc"
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},
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{
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"ConfigCode": "0x04",
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"EventName": "pre_cmd",
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"BriefDescription": "DDRC precharge commands",
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"PublicDescription": "DDRC precharge commands",
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"Unit": "hisi_sccl,ddrc"
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},
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{
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"ConfigCode": "0x05",
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"EventName": "act_cmd",
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"BriefDescription": "DDRC active commands",
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"PublicDescription": "DDRC active commands",
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"Unit": "hisi_sccl,ddrc"
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},
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{
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"ConfigCode": "0x06",
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"EventName": "rnk_chg",
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"BriefDescription": "DDRC rank commands",
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"PublicDescription": "DDRC rank commands",
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"Unit": "hisi_sccl,ddrc"
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},
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{
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"ConfigCode": "0x07",
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"EventName": "rw_chg",
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"BriefDescription": "DDRC read and write changes",
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"PublicDescription": "DDRC read and write changes",
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"Unit": "hisi_sccl,ddrc"
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}
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]
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@ -3,28 +3,24 @@
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"ConfigCode": "0x00",
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"EventName": "rx_ops_num",
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"BriefDescription": "The number of all operations received by the HHA",
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"PublicDescription": "The number of all operations received by the HHA",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x01",
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"EventName": "rx_outer",
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"BriefDescription": "The number of all operations received by the HHA from another socket",
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"PublicDescription": "The number of all operations received by the HHA from another socket",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x02",
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"EventName": "rx_sccl",
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"BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket",
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"PublicDescription": "The number of all operations received by the HHA from another SCCL in this socket",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x03",
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"EventName": "rx_ccix",
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"BriefDescription": "Count of the number of operations that HHA has received from CCIX",
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"PublicDescription": "Count of the number of operations that HHA has received from CCIX",
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"Unit": "hisi_sccl,hha"
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},
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{
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@ -49,42 +45,36 @@
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"ConfigCode": "0x1c",
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"EventName": "rd_ddr_64b",
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"BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
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"PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x1d",
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"EventName": "wr_ddr_64b",
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"BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
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"PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x1e",
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"EventName": "rd_ddr_128b",
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"BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
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"PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x1f",
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"EventName": "wr_ddr_128b",
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"BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
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"PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x20",
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"EventName": "spill_num",
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"BriefDescription": "Count of the number of spill operations that the HHA has sent",
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"PublicDescription": "Count of the number of spill operations that the HHA has sent",
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"Unit": "hisi_sccl,hha"
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},
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{
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"ConfigCode": "0x21",
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"EventName": "spill_success",
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"BriefDescription": "Count of the number of successful spill operations that the HHA has sent",
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"PublicDescription": "Count of the number of successful spill operations that the HHA has sent",
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"Unit": "hisi_sccl,hha"
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},
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{
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@ -3,91 +3,78 @@
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"ConfigCode": "0x00",
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"EventName": "rd_cpipe",
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"BriefDescription": "Total read accesses",
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"PublicDescription": "Total read accesses",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x01",
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"EventName": "wr_cpipe",
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"BriefDescription": "Total write accesses",
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"PublicDescription": "Total write accesses",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x02",
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"EventName": "rd_hit_cpipe",
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"BriefDescription": "Total read hits",
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"PublicDescription": "Total read hits",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x03",
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"EventName": "wr_hit_cpipe",
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"BriefDescription": "Total write hits",
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"PublicDescription": "Total write hits",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x04",
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"EventName": "victim_num",
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"BriefDescription": "l3c precharge commands",
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"PublicDescription": "l3c precharge commands",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x20",
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"EventName": "rd_spipe",
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"BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
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"PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x21",
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"EventName": "wr_spipe",
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"BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
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"PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x22",
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"EventName": "rd_hit_spipe",
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"BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
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"PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x23",
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"EventName": "wr_hit_spipe",
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"BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
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"PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x29",
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"EventName": "back_invalid",
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"BriefDescription": "Count of the number of L3C back invalid operations",
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"PublicDescription": "Count of the number of L3C back invalid operations",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x40",
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"EventName": "retry_cpu",
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"BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",
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"PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x41",
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"EventName": "retry_ring",
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"BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",
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"PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",
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"Unit": "hisi_sccl,l3c"
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},
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{
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"ConfigCode": "0x42",
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"EventName": "prefetch_drop",
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"BriefDescription": "Count of the number of prefetch drops from this L3C",
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"PublicDescription": "Count of the number of prefetch drops from this L3C",
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"Unit": "hisi_sccl,l3c"
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}
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]
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