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wifi: iwlwifi: fix the access to CNVR TOP registers
For Dr and Sc, we need to wait until the TOP is ready to gets its registers read by the host. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Reviewed-by: Daniel Gabay <daniel.gabay@intel.com> Link: https://patch.msgid.link/20260511203428.09778340db51.I28d678ad404bbf8068f139666d38e29be5aa063b@changeid Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
This commit is contained in:
parent
605f563c58
commit
c73869c1df
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2003-2014, 2018-2022, 2024-2025 Intel Corporation
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* Copyright (C) 2003-2014, 2018-2022, 2024-2026 Intel Corporation
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* Copyright (C) 2015-2016 Intel Deutschland GmbH
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*/
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#include <linux/device.h>
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@ -168,6 +168,22 @@ int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
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return -ETIMEDOUT;
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}
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int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout)
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{
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int t = 0;
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do {
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if ((iwl_read_umac_prph_no_grab(trans, addr) & mask) ==
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(bits & mask))
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return 0;
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udelay(IWL_POLL_INTERVAL);
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t += IWL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2018-2021, 2025 Intel Corporation
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* Copyright (C) 2018-2021, 2025-2026 Intel Corporation
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*/
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#ifndef __iwl_io_h__
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#define __iwl_io_h__
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@ -51,6 +51,8 @@ static inline void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
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int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout);
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int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout);
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void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
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void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
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u32 bits, u32 mask);
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2005-2014, 2018-2025 Intel Corporation
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* Copyright (C) 2005-2014, 2018-2026 Intel Corporation
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* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016 Intel Deutschland GmbH
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*/
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@ -411,6 +411,11 @@ enum {
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#define HPM_SECONDARY_DEVICE_STATE 0xa03404
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#define WFPM_MAC_OTP_CFG7_ADDR 0xa03338
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#define WFPM_MAC_OTP_CFG7_DATA 0xa0333c
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#define WFPM_RSRCS_4PHS_REQ_STTS 0xa033f8
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#define WFPM_RSRCS_4PHS_ACK_STTS 0xa033fc
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#define RSRC_REQ_CNVR_TOP BIT(6)
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#define RSRC_ACK_CNVR_TOP BIT(6)
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/* For UMAG_GEN_HW_STATUS reg check */
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2007-2015, 2018-2024 Intel Corporation
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* Copyright (C) 2007-2015, 2018-2024, 2026 Intel Corporation
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* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016-2017 Intel Deutschland GmbH
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*/
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@ -4000,6 +4000,30 @@ static void get_crf_id(struct iwl_trans *iwl_trans,
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else
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sd_reg_ver_addr = SD_REG_VER;
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/* wait until the device is ready to access the prph registers */
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if (iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_DR ||
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iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_SC) {
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u32 req = iwl_read_umac_prph_no_grab(iwl_trans,
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WFPM_RSRCS_4PHS_REQ_STTS);
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int ret;
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if (!(req & RSRC_REQ_CNVR_TOP)) {
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IWL_ERR(iwl_trans,
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"WFPM_RSRCS_4PHS_REQ_STTS bit 6 is clear 0x%x\n",
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req);
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return;
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}
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ret = iwl_poll_umac_prph_bits_no_grab(iwl_trans,
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WFPM_RSRCS_4PHS_ACK_STTS,
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RSRC_ACK_CNVR_TOP,
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RSRC_ACK_CNVR_TOP,
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50 * 1000);
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if (ret < 0)
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IWL_ERR(iwl_trans,
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"WFPM_RSRCS_4PHS_ACK_STTS bit 6 is clear\n");
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}
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/* Enable access to peripheral registers */
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val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);
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val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;
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