wifi: iwlwifi: fix the access to CNVR TOP registers

For Dr and Sc, we need to wait until the TOP is ready to gets its
registers read by the host.

Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Reviewed-by: Daniel Gabay <daniel.gabay@intel.com>
Link: https://patch.msgid.link/20260511203428.09778340db51.I28d678ad404bbf8068f139666d38e29be5aa063b@changeid
Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
This commit is contained in:
Emmanuel Grumbach 2026-05-11 20:36:19 +03:00 committed by Miri Korenblit
parent 605f563c58
commit c73869c1df
4 changed files with 51 additions and 4 deletions

View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2003-2014, 2018-2022, 2024-2025 Intel Corporation
* Copyright (C) 2003-2014, 2018-2022, 2024-2026 Intel Corporation
* Copyright (C) 2015-2016 Intel Deutschland GmbH
*/
#include <linux/device.h>
@ -168,6 +168,22 @@ int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
return -ETIMEDOUT;
}
int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
u32 bits, u32 mask, int timeout)
{
int t = 0;
do {
if ((iwl_read_umac_prph_no_grab(trans, addr) & mask) ==
(bits & mask))
return 0;
udelay(IWL_POLL_INTERVAL);
t += IWL_POLL_INTERVAL;
} while (t < timeout);
return -ETIMEDOUT;
}
void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
{
if (iwl_trans_grab_nic_access(trans)) {

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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2018-2021, 2025 Intel Corporation
* Copyright (C) 2018-2021, 2025-2026 Intel Corporation
*/
#ifndef __iwl_io_h__
#define __iwl_io_h__
@ -51,6 +51,8 @@ static inline void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
u32 bits, u32 mask, int timeout);
int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
u32 bits, u32 mask, int timeout);
void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
u32 bits, u32 mask);

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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2005-2014, 2018-2025 Intel Corporation
* Copyright (C) 2005-2014, 2018-2026 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Intel Deutschland GmbH
*/
@ -411,6 +411,11 @@ enum {
#define HPM_SECONDARY_DEVICE_STATE 0xa03404
#define WFPM_MAC_OTP_CFG7_ADDR 0xa03338
#define WFPM_MAC_OTP_CFG7_DATA 0xa0333c
#define WFPM_RSRCS_4PHS_REQ_STTS 0xa033f8
#define WFPM_RSRCS_4PHS_ACK_STTS 0xa033fc
#define RSRC_REQ_CNVR_TOP BIT(6)
#define RSRC_ACK_CNVR_TOP BIT(6)
/* For UMAG_GEN_HW_STATUS reg check */

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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2007-2015, 2018-2024 Intel Corporation
* Copyright (C) 2007-2015, 2018-2024, 2026 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@ -4000,6 +4000,30 @@ static void get_crf_id(struct iwl_trans *iwl_trans,
else
sd_reg_ver_addr = SD_REG_VER;
/* wait until the device is ready to access the prph registers */
if (iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_DR ||
iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_SC) {
u32 req = iwl_read_umac_prph_no_grab(iwl_trans,
WFPM_RSRCS_4PHS_REQ_STTS);
int ret;
if (!(req & RSRC_REQ_CNVR_TOP)) {
IWL_ERR(iwl_trans,
"WFPM_RSRCS_4PHS_REQ_STTS bit 6 is clear 0x%x\n",
req);
return;
}
ret = iwl_poll_umac_prph_bits_no_grab(iwl_trans,
WFPM_RSRCS_4PHS_ACK_STTS,
RSRC_ACK_CNVR_TOP,
RSRC_ACK_CNVR_TOP,
50 * 1000);
if (ret < 0)
IWL_ERR(iwl_trans,
"WFPM_RSRCS_4PHS_ACK_STTS bit 6 is clear\n");
}
/* Enable access to peripheral registers */
val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);
val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;