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dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl
Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their requirement status are: - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sscounterenw: Mandatory in RVA22S64, RVA23S64 - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu <guodong@riscstar.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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@ -161,12 +161,26 @@ properties:
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behavioural changes to interrupts as frozen at commit ccbddab
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("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
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- const: ssccptr
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description: |
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The standard Ssccptr extension for main memory (cacheability and
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coherence) hardware page-table reads, as ratified in RISC-V
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Profiles Version 1.0, with commit b1d806605f87 ("Updated to
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ratified state.")
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- const: sscofpmf
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description: |
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The standard Sscofpmf supervisor-level extension for count overflow
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and mode-based filtering as ratified at commit 01d1df0 ("Add ability
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to manually trigger workflow. (#2)") of riscv-count-overflow.
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- const: sscounterenw
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description: |
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The standard Sscounterenw extension for support writable enables
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in scounteren for any supported counter, as ratified in RISC-V
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Profiles Version 1.0, with commit b1d806605f87 ("Updated to
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ratified state.")
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- const: ssnpm
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description: |
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The standard Ssnpm extension for next-mode pointer masking as
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@ -179,6 +193,24 @@ properties:
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ratified at commit 3f9ed34 ("Add ability to manually trigger
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workflow. (#2)") of riscv-time-compare.
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- const: sstvala
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description: |
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The standard Sstvala extension for stval provides all needed values
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as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
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("Updated to ratified state.")
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- const: sstvecd
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description: |
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The standard Sstvecd extension for stvec supports Direct mode as
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ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
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("Updated to ratified state.")
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- const: ssu64xl
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description: |
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The standard Ssu64xl extension for UXLEN=64 must be supported, as
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ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
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("Updated to ratified state.")
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- const: svade
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description: |
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The standard Svade supervisor-level extension for SW-managed PTE A/D
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