dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl

Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala,
Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles
Version 1.0 (commit b1d806605f87 "Updated to ratified state.").

They are introduced as new extension names for existing features and
regulate implementation details for RISC-V Profile compliance. According
to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their
requirement status are:

 - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64
 - Sscounterenw: Mandatory in RVA22S64, RVA23S64
 - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64
 - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64
 - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64

Signed-off-by: Guodong Xu <guodong@riscstar.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Guodong Xu 2026-01-10 13:18:20 +08:00 committed by Conor Dooley
parent b321256a4f
commit c712413333

View File

@ -161,12 +161,26 @@ properties:
behavioural changes to interrupts as frozen at commit ccbddab
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
- const: ssccptr
description: |
The standard Ssccptr extension for main memory (cacheability and
coherence) hardware page-table reads, as ratified in RISC-V
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: sscofpmf
description: |
The standard Sscofpmf supervisor-level extension for count overflow
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
to manually trigger workflow. (#2)") of riscv-count-overflow.
- const: sscounterenw
description: |
The standard Sscounterenw extension for support writable enables
in scounteren for any supported counter, as ratified in RISC-V
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as
@ -179,6 +193,24 @@ properties:
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
- const: sstvala
description: |
The standard Sstvala extension for stval provides all needed values
as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
- const: sstvecd
description: |
The standard Sstvecd extension for stvec supports Direct mode as
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
- const: ssu64xl
description: |
The standard Ssu64xl extension for UXLEN=64 must be supported, as
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
- const: svade
description: |
The standard Svade supervisor-level extension for SW-managed PTE A/D