x86/mce: Define BSP-only SMCA init

Currently, on AMD systems, MCA interrupt handler functions are set during CPU
init. However, the functions only need to be set once for the whole system.

Assign the handlers only during BSP init. Do so only for SMCA systems to
maintain the old behavior for legacy systems.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
Link: https://lore.kernel.org/20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com
This commit is contained in:
Yazen Ghannam 2025-09-08 15:40:32 +00:00 committed by Borislav Petkov (AMD)
parent 669ce4984b
commit c6e465b8d4
3 changed files with 11 additions and 0 deletions

View File

@ -684,6 +684,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
deferred_error_interrupt_enable(c);
}
void smca_bsp_init(void)
{
mce_threshold_vector = amd_threshold_interrupt;
deferred_error_int_vector = amd_deferred_error_interrupt;
}
/*
* DRAM ECC errors are reported in the Northbridge (bank 4) with
* Extended Error Code 8.

View File

@ -2244,6 +2244,9 @@ void mca_bsp_init(struct cpuinfo_x86 *c)
mce_flags.succor = cpu_feature_enabled(X86_FEATURE_SUCCOR);
mce_flags.smca = cpu_feature_enabled(X86_FEATURE_SMCA);
if (mce_flags.smca)
smca_bsp_init();
rdmsrq(MSR_IA32_MCG_CAP, cap);
/* Use accurate RIP reporting if available. */

View File

@ -294,12 +294,14 @@ static __always_inline void smca_extract_err_addr(struct mce *m)
m->addr &= GENMASK_ULL(55, lsb);
}
void smca_bsp_init(void);
#else
static inline void mce_threshold_create_device(unsigned int cpu) { }
static inline void mce_threshold_remove_device(unsigned int cpu) { }
static inline bool amd_filter_mce(struct mce *m) { return false; }
static inline bool amd_mce_usable_address(struct mce *m) { return false; }
static inline void smca_extract_err_addr(struct mce *m) { }
static inline void smca_bsp_init(void) { }
#endif
#ifdef CONFIG_X86_ANCIENT_MCE