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dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family

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RZ/V2H, RZ/V2N, and RZ/G3E support two optional external audio clock
inputs (AUDIO_CLKB and AUDIO_CLKC) that can be used by the Audio Clock
Generator (ADG) to derive internal audio clocks.  The third ADG input
(AUDIO_CLKA) is fed internally by the AUDIO_EXTAL pin and does not need
a separate binding entry.

Update the bindings to allow these optional clocks for all RZ/V2H family
SoCs.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260525110603.4018170-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
John Madieu 2026-05-25 11:05:56 +00:00 committed by Geert Uytterhoeven
parent dc59e4fea9
commit c67b3c631a
1 changed files with 6 additions and 0 deletions
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6
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
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@ -26,16 +26,22 @@ properties:
maxItems: 1
clocks:
minItems: 3
items:
- description: AUDIO_EXTAL clock input
- description: RTXIN clock input
- description: QEXTAL clock input
- description: AUDIO_CLKB clock input
- description: AUDIO_CLKC clock input
clock-names:
minItems: 3
items:
- const: audio_extal
- const: rtxin
- const: qextal
- const: audio_clkb
- const: audio_clkc
'#clock-cells':
description: |