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ARM: dts: microchip: sam9x7: Add qspi controller

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Add support for QSPI controller.

Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Link: https://lore.kernel.org/r/20250915-sam9x7-qspi-dtsi-v1-1-1cc9adba7573@microchip.com
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
This commit is contained in:
Dharma Balasubiramani 2025-09-15 14:43:57 +05:30 committed by Nicolas Ferre
parent 82ab67d762
commit c656932c3e
1 changed files with 21 additions and 0 deletions
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21
arch/arm/boot/dts/microchip/sam9x7.dtsi
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@ -271,6 +271,27 @@ AT91_XDMAC_DT_PERID(38))>,
status = "disabled";
};
qspi: spi@f0014000 {
compatible = "microchip,sam9x7-ospi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0014000 0x100>, <0x60000000 0x20000000>;
reg-names = "qspi_base", "qspi_mmap";
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(26))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(27))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>;
clock-names = "pclk", "gclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 35>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_PLLADIV2>;
status = "disabled";
};
i2s: i2s@f001c000 {
compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc";
reg = <0xf001c000 0x100>;