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drm/rockchip: vop: support rk3328 linux drm cvbs

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Change-Id: Ie412fb30794b0addb2a4a0844af65e8356ab98c0
Signed-off-by: algea.cao <algea.cao@rock-chips.com>
This commit is contained in:
algea.cao 2017-06-14 18:11:36 +08:00 committed by Huang, Tao
parent ce0eedfcb2
commit c64bc3bdfa
3 changed files with 28 additions and 1 deletions
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14
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@ -1695,6 +1695,20 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, dp_pin_pol, val);
VOP_CTRL_SET(vop, dp_en, 1);
break;
case DRM_MODE_CONNECTOR_TV:
if (vdisplay == CVBS_PAL_VDISPLAY)
VOP_CTRL_SET(vop, tve_sw_mode, 1);
else
VOP_CTRL_SET(vop, tve_sw_mode, 0);
VOP_CTRL_SET(vop, tve_dclk_pol, 1);
VOP_CTRL_SET(vop, tve_dclk_en, 1);
/* use the same pol reg with hdmi */
VOP_CTRL_SET(vop, hdmi_pin_pol, val);
VOP_CTRL_SET(vop, sw_genlock, 1);
VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
VOP_CTRL_SET(vop, dither_up, 1);
break;
default:
DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
}

9
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@ -105,10 +105,15 @@ struct vop_ctrl {
struct vop_reg edp_pin_pol;
struct vop_reg mipi_pin_pol;
struct vop_reg dp_pin_pol;
struct vop_reg dither_up;
struct vop_reg dither_down;
struct vop_reg sw_dac_sel;
struct vop_reg tve_sw_mode;
struct vop_reg tve_dclk_pol;
struct vop_reg tve_dclk_en;
struct vop_reg sw_genlock;
struct vop_reg sw_uv_offset_en;
struct vop_reg dsp_out_yuv;
struct vop_reg dsp_data_swap;
struct vop_reg dsp_ccir656_avg;
@ -277,6 +282,8 @@ struct vop_data {
u64 feature;
};
#define CVBS_PAL_VDISPLAY 288
/* interrupt define */
#define DSP_HOLD_VALID_INTR (1 << 0)
#define FS_INTR (1 << 1)

6
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@ -583,6 +583,12 @@ static const struct vop_ctrl rk3328_ctrl_data = {
.hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
.tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24),
.tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25),
.tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26),
.sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27),
.sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28),
.sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29),
.rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16),
.hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20),
.edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24),