github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-08-02 13:22:02 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: mba8xx: Add PCIe support

Browse Source 
Add PCIe support for TQMa8Xx on MBa8Xx board.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Alexander Stein 2025-01-07 15:01:10 +01:00 committed by Shawn Guo
parent c58128a8a8
commit c63a0bfd11
1 changed files with 27 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
arch/arm64/boot/dts/freescale/mba8xx.dtsi
View File

@ -36,6 +36,13 @@ chosen {
stdout-path = &lpuart1;
};
/* Non-controllable PCIe reference clock generator */
pcie_refclk: clock-pcie-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -208,6 +215,12 @@ &flexcan2 {
status = "okay";
};
&hsio_phy {
fsl,hsio-cfg = "pciea-x2-pcieb";
fsl,refclk-pad-mode = "input";
status = "okay";
};
&i2c1 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
@ -309,7 +322,16 @@ &lsio_gpio3 {
"", "", "", "";
};
/* TODO: Mini-PCIe */
&pcieb {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
disable-gpio = <&expander 7 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie_1v5>;
status = "okay";
};
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
@ -467,10 +489,10 @@ pinctrl_pca9538: pca9538grp {
fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>;
};
pinctrl_pcieb: pcieagrp {
fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
<IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
<IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
pinctrl_pcieb: pciebgrp {
fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
<IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000041>,
<IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
};
pinctrl_reg_pcie_1v5: regpcie1v5grp {