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Amlogic drivers changes for v6.15:

Browse Source 
- GPIO interrupt controller support for Amlogic A4 and A5 SoCs
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmfX/FAACgkQd9zb2sjI
 SdFTDw/+Ldaw2C5sMAkij6b/O/XC0L8Az32kySHfJgUlN/CtsST2V6bU660IzQOo
 9BhnZW59WZb4cakoVGtYgTjXWv1jyUxp6NvH2dc6TtdJ/TRV12mw4unOoVc2NVHX
 so4QbguTXyfJr1Yt2aiySzeivfuWALY4+wOhDLTOovPJJ2CiCR4a3hJywFfy9/2D
 VuVFHlX8UjGZEQvsr9OD39lnN4wTYddTKgvf9iu/I5ZrlGEsZuOrl5K8vvxZxtTm
 zLyJYj+cAhhbiPL0or1KKcqC6J+2hP39HpT7eYDXNHfyCBsDqmZp0HGPbhrMGPY7
 fofgbKDGsP8sMz8aNrS8lym7gyFSCVm+FUYYi/YeIykUXll//b+of38ITwUvxWyn
 J7Ipvt5U5GKhjDZ1uQ+S3Q5x+JlWVm/gflJs4V5Ycrw1UxTtCLPdu07G2cyk4AqD
 Yyn7td7l+ta00x+itD0yMQkn8Sq6ucqi4CqwW2D6xZS6olK32oyAbSCE6iT0Papu
 AJoSXLtogPTLdQvDzBk2kIdwulu5/VDNcuIBsLPmhx1mp88JxLeeQxNxWS9O3z3C
 3BCAh93CT0WwzXgAQY8zHuEVrvgJSynlHXm+RDbzezFEsPA7ucNdRovPsbQ7xIVh
 AmcDxZsMKepIlPB7Ldei7vA6NKXJlYbJxLLLFbmatjMFxqgSa4k=
 =wTrP
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfbPO4ACgkQYKtH/8kJ
 UicNYxAAvVW+/PLWjT2xp/WPclXpQxmf1xIfbx1LPG9ilY0aso1tMiseQsgF+eCo
 I11mhrHLljM6y56DGL/OmeWFGh8XoB9y61PLIaE0L4AyTNsaW5mvlsgK068RixMt
 3+RZg+rQglFqcXGRRUV6JTqFFIvYNh3msIEAmv+v7mRsNiVNfvsLfo5vCb1uRs6Y
 H0hKspeMxa862FrPEDacUuHEbYT38my6hGrSiUQdoaV2A5qLt7VQ76mYIFPt3FSr
 M7alenuHrr37I4kZ+BAcz/Yd26PTUX9Xm5RqOfPxrh42hePZhw6I/HM1shqxcjAv
 FSfNcYKAKl43dNHuDKktPNpZDt/tLCSTCkDqD3nKyhoO62CPnQ8z/Q5cyQY3+v2J
 zROD2E20ValyFvoX3rod2Fp4lUGYXVwUy+Nun7MUZ1FxGliGuTHOlQBSKvgHWJD/
 fYDID3L5LBLVLiA/Q4fAehjo4UPmGZIuDrYOqoXL9OMDNykBrKcRksE/PJHAhh38
 fBJZZmjCF77Vi7YaiLgTeqOn88d5PhrMtW9uCluLZY3u/iV913xjLsn4ixAW1TSs
 yCqfI0HQp2grlHPY9PBPArAfhn8Dt01OqyuWbRfE5PToDtdrBpTiSU8xCPCwnMai
 Na0zsYs4I8E/Jrr9YPmKLgs4IxHp0J0WxkK/JRnlbBfApdXN0ro=
 =RshC
 -----END PGP SIGNATURE-----

Merge tag 'amlogic-drivers-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers

Amlogic drivers changes for v6.15:
- GPIO interrupt controller support for Amlogic A4 and A5 SoCs

* tag 'amlogic-drivers-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  irqchip: Add support for Amlogic A4 and A5 SoCs
  dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs

Link: https://lore.kernel.org/r/eeaa8d3b-4fc3-4dae-92b8-0fc590e1a070@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-03-19 22:53:50 +01:00
commit c6325a2e26
2 changed files with 55 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
View File

@ -35,6 +35,9 @@ properties:
- amlogic,meson-sm1-gpio-intc
- amlogic,meson-a1-gpio-intc
- amlogic,meson-s4-gpio-intc
- amlogic,a4-gpio-intc
- amlogic,a4-gpio-ao-intc
- amlogic,a5-gpio-intc
- amlogic,c3-gpio-intc
- amlogic,t7-gpio-intc
- const: amlogic,meson-gpio-intc
@ -49,7 +52,7 @@ properties:
amlogic,channel-interrupts:
description: Array with the upstream hwirq numbers
minItems: 8
minItems: 2
maxItems: 12
$ref: /schemas/types.yaml#/definitions/uint32-array
@ -60,6 +63,20 @@ required:
- "#interrupt-cells"
- amlogic,channel-interrupts
if:
properties:
compatible:
contains:
const: amlogic,a4-gpio-ao-intc
then:
properties:
amlogic,channel-interrupts:
maxItems: 2
else:
properties:
amlogic,channel-interrupts:
minItems: 8
additionalProperties: false
examples:

48
drivers/irqchip/irq-meson-gpio.c
View File

@ -26,8 +26,6 @@
/* use for A1 like chips */
#define REG_PIN_A1_SEL 0x04
/* Used for s4 chips */
#define REG_EDGE_POL_S4 0x1c
/*
* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
@ -72,6 +70,7 @@ struct meson_gpio_irq_params {
bool support_edge_both;
unsigned int edge_both_offset;
unsigned int edge_single_offset;
unsigned int edge_pol_reg;
unsigned int pol_low_offset;
unsigned int pin_sel_mask;
struct irq_ctl_ops ops;
@ -105,6 +104,18 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
meson_a1_gpio_irq_sel_pin, \
meson_s4_gpio_irq_set_type) \
.support_edge_both = true, \
.edge_both_offset = 0, \
.edge_single_offset = 12, \
.edge_pol_reg = 0x8, \
.pol_low_offset = 0, \
.pin_sel_mask = 0xff, \
.nr_channels = 2, \
#define INIT_MESON_S4_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
meson_a1_gpio_irq_sel_pin, \
@ -112,6 +123,7 @@ struct meson_gpio_irq_params {
.support_edge_both = true, \
.edge_both_offset = 0, \
.edge_single_offset = 12, \
.edge_pol_reg = 0x1c, \
.pol_low_offset = 0, \
.pin_sel_mask = 0xff, \
.nr_channels = 12, \
@ -146,6 +158,18 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
static const struct meson_gpio_irq_params a4_params = {
INIT_MESON_S4_COMMON_DATA(81)
};
static const struct meson_gpio_irq_params a4_ao_params = {
INIT_MESON_A4_AO_COMMON_DATA(8)
};
static const struct meson_gpio_irq_params a5_params = {
INIT_MESON_S4_COMMON_DATA(99)
};
static const struct meson_gpio_irq_params s4_params = {
INIT_MESON_S4_COMMON_DATA(82)
};
@ -168,6 +192,9 @@ static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
{ .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
{ .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
{ .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
{ }
@ -299,11 +326,10 @@ meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq)
{
u32 val = 0;
const struct meson_gpio_irq_params *params = ctl->params;
unsigned int idx;
const struct meson_gpio_irq_params *params;
u32 val = 0;
params = ctl->params;
idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
/*
@ -356,19 +382,19 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq)
{
u32 val = 0;
const struct meson_gpio_irq_params *params = ctl->params;
unsigned int idx;
u32 val = 0;
idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
type &= IRQ_TYPE_SENSE_MASK;
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0);
meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0);
if (type == IRQ_TYPE_EDGE_BOTH) {
val |= BIT(ctl->params->edge_both_offset + idx);
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
BIT(ctl->params->edge_both_offset + idx), val);
val = BIT(ctl->params->edge_both_offset + idx);
meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, val, val);
return 0;
}
@ -378,7 +404,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
val |= BIT(ctl->params->edge_single_offset + idx);
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,
BIT(idx) | BIT(12 + idx), val);
return 0;
};