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drm/i915/lt_phy: Add xe3plpd .get_hw_state hook

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Add .get_hw_state hook to xe3plpd platform for dpll framework
and update intel_lt_phy_pll_readout_hw_state() function
accordingly to support dpll framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-14-mika.kahola@intel.com
This commit is contained in:
Mika Kahola 2026-03-12 08:06:46 +00:00
parent 37115f773c
commit c62ba60b10
4 changed files with 21 additions and 8 deletions
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2
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -4248,7 +4248,7 @@ static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
{
struct intel_display *display = to_intel_display(encoder);
intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
intel_lt_phy_pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.ltpll);
if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);

13
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
View File

@ -4571,7 +4571,20 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
.compare_hw_state = mtl_compare_hw_state,
};
static bool xe3plpd_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_encoder *encoder = get_intel_encoder(display, pll);
if (!encoder)
return false;
return intel_lt_phy_pll_readout_hw_state(encoder, &dpll_hw_state->ltpll);
}
static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
.get_hw_state = xe3plpd_pll_get_hw_state,
};
static const struct dpll_info xe3plpd_plls[] = {

11
drivers/gpu/drm/i915/display/intel_lt_phy.c
View File

@ -2213,8 +2213,7 @@ static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
XELPDP_LANE_PCLK_PLL_ACK(0);
}
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_lt_phy_pll_state *pll_state)
{
u8 owned_lane_mask;
@ -2223,11 +2222,11 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
int i, j, k;
if (!intel_lt_phy_pll_is_enabled(encoder))
return;
return false;
pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
if (pll_state->tbt_mode)
return;
return false;
owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
@ -2245,6 +2244,8 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
}
intel_lt_phy_transaction_end(encoder, wakeref);
return true;
}
void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
@ -2270,7 +2271,7 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
return;
encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
intel_lt_phy_pll_readout_hw_state(encoder, &pll_hw_state);
dig_port = enc_to_dig_port(encoder);
if (intel_tc_port_in_tbt_alt_mode(dig_port))

3
drivers/gpu/drm/i915/display/intel_lt_phy.h
View File

@ -32,8 +32,7 @@ void intel_lt_phy_dump_hw_state(struct drm_printer *p,
bool
intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
const struct intel_lt_phy_pll_state *b);
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_lt_phy_pll_state *pll_state);
void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);