From c5b29baad42b2b02389cc6a716697a8a63209930 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 27 Aug 2026 18:57:36 +0800 Subject: [PATCH] pwm: mtk-disp: Fix period readback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The period value stored in the register is the number of clock cycles - 1. Account for the offset when calculating the period in nanoseconds. This fixes the discrepancy reported by the pwm core when CONFIG_PWM_DEBUG=1: mediatek-disp-pwm 1100e000.pwm: .apply is not idempotent (ena=1 pol=0 281500/499875) -> (ena=1 pol=0 281500/499750) Calculation discrepancy in the driver was found by AI run by a colleague while debugging another PWM related issue. Check against SoC datasheet and fix done by the author. Fixes: 3f2b16734914 ("pwm: mtk-disp: Implement atomic API .get_state()") Cc: Jitao Shi Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://patch.msgid.link/20260827105738.8570-1-wenst@chromium.org [ukleinek: Adapt comment accordingly] Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-mtk-disp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index b5409e15dac8..56d10cde5b46 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -210,9 +210,9 @@ static int mtk_disp_pwm_get_state(struct pwm_chip *chip, period = FIELD_GET(PWM_PERIOD_MASK, con1); /* * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30, - * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow. + * so (period + 1) * (clk_div + 1) * NSEC_PER_SEC doesn't overflow. */ - state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); + state->period = DIV64_U64_ROUND_UP((period + 1) * (clk_div + 1) * NSEC_PER_SEC, rate); high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1); state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC, rate);