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pinctrl: renesas: rzg2l: Add support for clone channel control
The RZ/G3L SoC has some IP such as I2C ch{2,3},SCIF ch{3,4,5},
RSPI ch{1,2} and RSCI ch{1,2,3} need to control the clone channel for
proper operation. As per the RZ/G3L hardware manual, the clone channel
setting is to be done before the mux setting.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
Geert Uytterhoeven
parent
b2aff3c99f
commit
c590b377dc
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@ -11,12 +11,14 @@
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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@ -152,6 +154,18 @@
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FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
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FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
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#define RZG3L_CLONE_CHANNEL_PIN_MASK GENMASK(31, 24)
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#define RZG3L_CLONE_CHANNEL_PORT_MASK GENMASK(23, 19)
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#define RZG3L_CLONE_CHANNEL_BIT_MASK GENMASK(12, 9)
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#define RZG3L_CLONE_CHANNEL_VAL_MASK BIT(8)
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#define RZG3L_CLONE_CHANNEL_PFC_MASK GENMASK(7, 0)
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#define RZG3L_CLONE_CHANNEL_DATA(port, pins, bit, val, pfc) \
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(FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PIN_MASK, (pins)) | \
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FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PORT_MASK, (port)) | \
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FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_BIT_MASK, (bit)) | \
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FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_VAL_MASK, (val)) | \
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FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PFC_MASK, (pfc)))
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#define P(off) (0x0000 + (off))
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#define PM(off) (0x0100 + (off) * 2)
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#define PMC(off) (0x0200 + (off))
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@ -313,6 +327,8 @@ struct rzg2l_pinctrl_data {
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const struct rzg2l_dedicated_configs *dedicated_pins;
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unsigned int n_port_pins;
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unsigned int n_dedicated_pins;
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const u32 *clone_channel_data;
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unsigned int n_clone_channel_data;
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const struct rzg2l_hwcfg *hwcfg;
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const u64 *variable_pin_cfg;
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unsigned int n_variable_pin_cfg;
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@ -350,6 +366,7 @@ struct rzg2l_pinctrl_pin_settings {
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* @smt: SMT registers cache
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* @sr: SR registers cache
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* @nod: NOD registers cache
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* @clone: Clone register cache
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* @sd_ch: SD_CH registers cache
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* @eth_poc: ET_POC registers cache
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* @other_poc: OTHER_POC register cache
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@ -367,6 +384,7 @@ struct rzg2l_pinctrl_reg_cache {
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u32 *smt[2];
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u32 *sr[2];
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u32 *nod[2];
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u32 clone;
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u8 sd_ch[2];
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u8 eth_poc[2];
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u8 oen;
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@ -385,6 +403,8 @@ struct rzg2l_pinctrl {
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struct clk *clk;
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struct regmap *syscon;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
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@ -398,6 +418,7 @@ struct rzg2l_pinctrl {
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struct rzg2l_pinctrl_reg_cache *cache;
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struct rzg2l_pinctrl_reg_cache *dedicated_cache;
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atomic_t wakeup_path;
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u32 clone_offset;
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};
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static const u16 available_ps[] = { 1800, 2500, 3300 };
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@ -623,6 +644,45 @@ static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl,
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return 0;
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}
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static int rzg2l_pinctrl_set_clone_mode(struct rzg2l_pinctrl *pctrl,
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u8 port, u8 pin, u8 func)
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{
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unsigned int i;
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if (!pctrl->data->clone_channel_data)
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return 0;
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switch (func) {
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case 2:
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case 4 ... 7:
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break;
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default:
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return 0;
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}
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for (i = 0; i < pctrl->data->n_clone_channel_data; i++) {
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u32 pin_data = pctrl->data->clone_channel_data[i];
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unsigned int pin_func_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PFC_MASK, pin_data);
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unsigned int pin_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PIN_MASK, pin_data);
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u32 bit, val;
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if (!(pin_func_mask & BIT(func)) ||
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FIELD_GET(RZG3L_CLONE_CHANNEL_PORT_MASK, pin_data) != port)
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continue;
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if (!(pin_mask & BIT(pin)))
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continue;
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bit = FIELD_GET(RZG3L_CLONE_CHANNEL_BIT_MASK, pin_data);
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val = FIELD_GET(RZG3L_CLONE_CHANNEL_VAL_MASK, pin_data);
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return regmap_update_bits(pctrl->syscon, pctrl->clone_offset,
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BIT(bit), val << bit);
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}
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return 0;
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}
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static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
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u8 pin, u8 off, u8 func)
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{
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@ -698,6 +758,10 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
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func = psel_val[i] - hwcfg->func_base;
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dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", port, pin, off, func);
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ret = rzg2l_pinctrl_set_clone_mode(pctrl, port, pin, func);
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if (ret)
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return ret;
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rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func);
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}
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@ -2636,6 +2700,97 @@ static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = {
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(PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
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};
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static const u32 r9a08g046_clone_channel_data[] = {
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/* I2C ch2 Bit:0 Value:0 PFC:4 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(7, 6), 0, 0, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 2), 0, 0, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(1, 0), 0, 0, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 0, 0, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)),
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/* I2C ch2 Bit:0 Value:1 PFC:4 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(2, 1), 0, 1, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)),
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/* I2C ch3 Bit:1 Value:0 PFC:4 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 1, 0, BIT(4)),
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/* I2C ch3 Bit:1 Value:1 PFC:4 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P2, GENMASK(1, 0), 1, 1, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6) | GENMASK(3, 2), 1, 1, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 3) | BIT(0), 1, 1, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6), 1, 1, BIT(4)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(3, 2), 1, 1, BIT(4)),
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/* SCIF ch3 Bit:4 Value:0 PFC:{6,7} */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(6, 4), 4, 0, BIT(6)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 3), 4, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(4, 2), 4, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 3), 4, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(2, 0), 4, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 1), 4, 0, BIT(7)),
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/* SCIF ch3 Bit:4 Value:1 PFC:7 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(2, 0), 4, 1, BIT(7)),
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/* SCIF ch4 Bit:5 Value:0 PFC:7 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(2, 0), 5, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 5), 5, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 5, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, BIT(0), 5, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(5, 3), 5, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(6, 4), 5, 0, BIT(7)),
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/* SCIF ch4 Bit:5 Value:1 PFC:7 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 3), 5, 1, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 2), 5, 1, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 5), 5, 1, BIT(7)),
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/* SCIF ch5 Bit:6 Value:0 PFC:7 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, BIT(7), 6, 0, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 6, 0, BIT(7)),
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/* SCIF ch5 Bit:6 Value:1 PFC:7 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6), 6, 1, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(1, 0), 6, 1, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(4, 2) | BIT(0), 6, 1, BIT(7)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(2, 0), 6, 1, BIT(7)),
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/* RSPI ch1 Bit:8 Value:0 PFC:2 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 0), 8, 0, BIT(2)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 5), 8, 0, BIT(2)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 8, 0, BIT(2)),
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/* RSPI ch1 Bit:8 Value:1 PFC:2 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 0), 8, 1, BIT(2)),
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/* RSPI ch2 Bit:9 Value:0 PFC:2 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 4), 9, 0, BIT(2)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(2, 0), 9, 0, BIT(2)),
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/* RSPI ch2 Bit:9 Value:1 PFC:2 */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 0), 9, 1, BIT(2)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, BIT(7), 9, 1, BIT(2)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 0), 9, 1, BIT(2)),
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/* RSCI ch1 Bit:12 Value:0 PFC:{5,6} shared pins based on RSCI mode */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(3, 0), 12, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(3, 0), 12, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 12, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 12, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 4), 12, 0, GENMASK(6, 5)),
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/* RSCI ch1 Bit:12 Value:1 PFC:{5,6} shared pins based on RSCI mode */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(3, 0), 12, 1, GENMASK(6, 5)),
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/* RSCI ch2 Bit:13 Value:0 PFC:{5,6} shared pins based on RSCI mode */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 4), 13, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
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/* RSCI ch2 Bit:13 Value:1 PFC:{5,6} shared pins based on RSCI mode */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 4), 13, 1, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | BIT(0), 13, 1, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6) | GENMASK(1, 0), 13, 1, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(1, 0), 13, 1, GENMASK(6, 5)),
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/* RSCI ch3 Bit:14 Value:0 PFC:{5,6} shared pins based on RSCI mode */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6), 14, 0, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 14, 0, GENMASK(6, 5)),
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/* RSCI ch3 Bit:14 Value:1 PFC:{5,6} shared pins based on RSCI mode */
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 1), 14, 1, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(5, 2), 14, 1, GENMASK(6, 5)),
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RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 2), 14, 1, GENMASK(6, 5)),
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};
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static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
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{
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const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
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@ -3222,6 +3377,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
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"failed to enable GPIO clk\n");
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}
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if (pctrl->data->clone_channel_data) {
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struct device_node *np = pctrl->dev->of_node;
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pctrl->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,clonech",
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1, &pctrl->clone_offset);
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if (IS_ERR(pctrl->syscon))
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return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->syscon),
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"Failed to parse renesas,clonech\n");
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}
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raw_spin_lock_init(&pctrl->lock);
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spin_lock_init(&pctrl->bitmap_lock);
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mutex_init(&pctrl->mutex);
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@ -3511,6 +3676,14 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
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if (regs->other_poc)
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cache->other_poc = readb(pctrl->base + regs->other_poc);
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if (pctrl->syscon) {
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int ret;
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ret = regmap_read(pctrl->syscon, pctrl->clone_offset, &cache->clone);
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if (ret)
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return ret;
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}
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if (!atomic_read(&pctrl->wakeup_path))
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clk_disable_unprepare(pctrl->clk);
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else
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@ -3528,6 +3701,12 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
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unsigned long flags;
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int ret;
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if (pctrl->syscon) {
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ret = regmap_write(pctrl->syscon, pctrl->clone_offset, cache->clone);
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if (ret)
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return ret;
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}
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if (!atomic_read(&pctrl->wakeup_path)) {
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ret = clk_prepare_enable(pctrl->clk);
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if (ret)
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@ -3742,6 +3921,8 @@ static struct rzg2l_pinctrl_data r9a08g046_data = {
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.dedicated_pins = rzg3l_dedicated_pins,
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.n_port_pins = ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT,
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.n_dedicated_pins = ARRAY_SIZE(rzg3l_dedicated_pins),
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.clone_channel_data = r9a08g046_clone_channel_data,
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.n_clone_channel_data = ARRAY_SIZE(r9a08g046_clone_channel_data),
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.hwcfg = &rzg3l_hwcfg,
|
||||
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
|
||||
.pmc_writeb = &rzg2l_pmc_writeb,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user