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drm/i915/display: fix typos in i915/display files

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Fix all typos in files under drm/i915/display reported by codespell tool.

v2:
  - Include british and american spelling, as those are
    not typos.
  - Fix commenting style. <Jani>

v3: Fix "In case" wrongly capitalized and
    also fix comment style. <Krzysztof Niemiec>

Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
Reviewed-by: Krzysztof Niemiec <krzysztof.niemiec@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120081517.3237326-8-nitin.r.gote@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Nitin Gote 2025-01-20 13:45:16 +05:30 committed by Rodrigo Vivi
parent 5b056be1f2
commit c55af00652
No known key found for this signature in database
GPG Key ID: FA625F640EEB13CA
47 changed files with 112 additions and 103 deletions
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2
drivers/gpu/drm/i915/display/dvo_ns2501.c
View File

@ -517,7 +517,7 @@ static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo)
* Even if not, the detection bit of the 2501 is unreliable as
* it only works for some display types.
* It is even more unreliable as the PLL must be active for
* allowing reading from the chiop.
* allowing reading from the chip.
*/
return connector_status_connected;
}

6
drivers/gpu/drm/i915/display/i9xx_wm.c
View File

@ -446,7 +446,7 @@ static const struct intel_watermark_params i845_wm_info = {
* @latency: Memory wakeup latency in 0.1us units
*
* Compute the watermark using the method 1 or "small buffer"
* formula. The caller may additonally add extra cachelines
* formula. The caller may additionally add extra cachelines
* to account for TLB misses and clock crossings.
*
* This method is concerned with the short term drain rate
@ -493,7 +493,7 @@ static unsigned int intel_wm_method1(unsigned int pixel_rate,
* @latency: Memory wakeup latency in 0.1us units
*
* Compute the watermark using the method 2 or "large buffer"
* formula. The caller may additonally add extra cachelines
* formula. The caller may additionally add extra cachelines
* to account for TLB misses and clock crossings.
*
* This method is concerned with the long term drain rate
@ -1562,7 +1562,7 @@ static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
/*
* When enabling sprite0 after sprite1 has already been enabled
* we tend to get an underrun unless sprite0 already has some
* FIFO space allcoated. Hence we always allocate at least one
* FIFO space allocated. Hence we always allocate at least one
* cacheline for sprite0 whenever sprite1 is enabled.
*
* All other plane enable sequences appear immune to this problem.

4
drivers/gpu/drm/i915/display/icl_dsi.c
View File

@ -243,7 +243,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
for_each_dsi_phy(phy, intel_dsi->phys) {
/*
* Program voltage swing and pre-emphasis level values as per
* table in BSPEC under DDI buffer programing
* table in BSPEC under DDI buffer programming.
*/
mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
@ -961,7 +961,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
/*
* FIXME: Programing this by assuming progressive mode, since
* FIXME: Programming this by assuming progressive mode, since
* non-interlaced info from VBT is not saved inside
* struct drm_display_mode.
* For interlace mode: program required pixel minus 2

4
drivers/gpu/drm/i915/display/intel_audio.c
View File

@ -567,7 +567,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
AUDIO_ELD_VALID(cpu_transcoder), 0);
/*
* The audio componenent is used to convey the ELD
* The audio component is used to convey the ELD
* instead using of the hardware ELD buffer.
*/
@ -665,7 +665,7 @@ static void ibx_audio_codec_enable(struct intel_encoder *encoder,
IBX_ELD_VALID(port), 0);
/*
* The audio componenent is used to convey the ELD
* The audio component is used to convey the ELD
* instead using of the hardware ELD buffer.
*/

2
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@ -2250,7 +2250,7 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
/*
* Let's ignore the pipe field, since BIOS could have configured the
* dividers both synching to an active pipe, or asynchronously
* dividers both syncing to an active pipe, or asynchronously
* (PIPE_NONE).
*/
cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);

2
drivers/gpu/drm/i915/display/intel_color.c
View File

@ -998,7 +998,7 @@ static void skl_color_commit_noarm(struct intel_dsb *dsb,
* output all black (until CSC_MODE is rearmed and properly latched).
* Once PSR exit (and proper register latching) has occurred the
* danger is over. Thus when PSR is enabled the CSC coeff/offset
* register programming will be peformed from skl_color_commit_arm()
* register programming will be performed from skl_color_commit_arm()
* which is called after PSR exit.
*/
if (!crtc_state->has_psr)

6
drivers/gpu/drm/i915/display/intel_crt.c
View File

@ -745,8 +745,10 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
transconf | TRANSCONF_FORCE_BORDER);
intel_de_posting_read(display,
TRANSCONF(display, cpu_transcoder));
/* Wait for next Vblank to substitue
* border color for Color info */
/*
* Wait for next Vblank to substitute
* border color for Color info.
*/
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
st00 = intel_de_read8(display, _VGA_MSR_WRITE);
status = ((st00 & (1 << 4)) != 0) ?

2
drivers/gpu/drm/i915/display/intel_crtc.c
View File

@ -96,7 +96,7 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
/*
* From Gen 11, In case of dsi cmd mode, frame counter wouldnt
* From Gen 11, in case of dsi cmd mode, frame counter wouldn't
* have updated at the beginning of TE, if we want to use
* the hw counter, then we would find it updated in only
* the next TE, hence switching to sw counter.

2
drivers/gpu/drm/i915/display/intel_cursor.c
View File

@ -680,7 +680,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb,
* CURPOS.
*
* On other platforms CURPOS always requires the
* CURBASE write to arm the update. Additonally
* CURBASE write to arm the update. Additionally
* a write to any of the cursor register will cancel
* an already armed cursor update. Thus leaving out
* the CURBASE write after CURPOS could lead to a

4
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -2984,7 +2984,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
* - crtc_state will be the state of the first stream to be activated on this
* port, and it may not be the same stream that will be deactivated last, but
* each stream should have a state that is identical when it comes to the DP
* link parameteres
* link parameters.
*/
static void intel_ddi_pre_enable(struct intel_atomic_state *state,
struct intel_encoder *encoder,
@ -3284,7 +3284,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
* be deactivated on this port, and it may not be the same
* stream that was activated last, but each stream
* should have a state that is identical when it comes to
* the DP link parameteres
* the DP link parameters
*/
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))

8
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -1013,7 +1013,7 @@ static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
{
if (DISPLAY_VER(i915) == 9) {
/*
* "Plane N strech max must be programmed to 11b (x1)
* "Plane N stretch max must be programmed to 11b (x1)
* when Async flips are enabled on that plane."
*/
intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
@ -3592,7 +3592,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
/*
* We currently do not free assignements of panel fitters on
* We currently do not free assignments of panel fitters on
* ivb/hsw (since we don't use the higher upscaling modes which
* differentiates them) so just WARN about this case for now.
*/
@ -4292,7 +4292,7 @@ int intel_dotclock_calculate(int link_freq,
/*
* The calculation for the data clock -> pixel clock is:
* pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
* But we want to avoid losing precison if possible, so:
* But we want to avoid losing precision if possible, so:
* pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
*
* and for link freq (10kbs units) -> pixel clock it is:
@ -6433,7 +6433,7 @@ static void kill_joiner_secondaries(struct intel_atomic_state *state,
* the intel_crtc_enable_flip_done() function.
*
* As soon as the surface address register is written, flip done interrupt is
* generated and the requested events are sent to the usersapce in the interrupt
* generated and the requested events are sent to the userspace in the interrupt
* handler itself. The timestamp and sequence sent during the flip done event
* correspond to the last vblank and have no relation to the actual time when
* the flip done event was sent.

2
drivers/gpu/drm/i915/display/intel_display_debugfs.c
View File

@ -940,7 +940,7 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
/*
* Actually TGL can drive LPSP on port till DDI_C
* but there is no physical connected DDI_C on TGL sku's,
* even driver is not initilizing DDI_C port for gen12.
* even driver is not initializing DDI_C port for gen12.
*/
lpsp_capable = encoder->port <= PORT_B;
else if (DISPLAY_VER(i915) == 11)

4
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -842,7 +842,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
* block right away if this is the last reference.
*
* This function is only for the power domain code's internal use to suppress wakeref
* tracking when the correspondig debug kconfig option is disabled, should not
* tracking when the corresponding debug kconfig option is disabled, should not
* be used otherwise.
*/
void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
@ -1733,7 +1733,7 @@ static void icl_display_core_uninit(struct intel_display *display)
gen9_disable_dc_states(display);
intel_dmc_disable_program(display);
/* 1. Disable all display engine functions -> aready done */
/* 1. Disable all display engine functions -> already done */
/* 2. Disable DBUF */
gen9_dbuf_disable(display);

4
drivers/gpu/drm/i915/display/intel_display_power_well.h
View File

@ -60,7 +60,7 @@ struct i915_power_well_instance {
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
* Arbitraty data associated with this power well. Platform and power
* Arbitrary data associated with this power well. Platform and power
* well specific.
*/
union {
@ -77,7 +77,7 @@ struct i915_power_well_instance {
struct {
/*
* request/status flag index in the power well
* constrol/status registers.
* control/status registers.
*/
u8 idx;
} hsw;

4
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -732,7 +732,7 @@ struct intel_crtc_scaler_state {
*
* intel_atomic_setup_scalers will setup available scalers to users
* requesting scalers. It will gracefully fail if request exceeds
* avilability.
* availability.
*/
#define SKL_CRTC_INDEX 31
unsigned scaler_users;
@ -1113,7 +1113,7 @@ struct intel_crtc_state {
u16 su_y_granularity;
/*
* Frequence the dpll for the port should run at. Differs from the
* Frequency the dpll for the port should run at. Differs from the
* adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
* already multiplied by pixel_multiplier.
*/

2
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -1075,7 +1075,7 @@ static bool source_can_output(struct intel_dp *intel_dp,
/*
* No YCbCr output support on gmch platforms.
* Also, ILK doesn't seem capable of DP YCbCr output.
* The displayed image is severly corrupted. SNB+ is fine.
* The displayed image is severely corrupted. SNB+ is fine.
*/
return !HAS_GMCH(display) && !display->platform.ironlake;

4
drivers/gpu/drm/i915/display/intel_dp_link_training.c
View File

@ -783,7 +783,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
/*
* WaEdpLinkRateDataReload
*
* Parade PS8461E MUX (used on varius TGL+ laptops) needs
* Parade PS8461E MUX (used on various TGL+ laptops) needs
* to snoop the link rates reported by the sink when we
* use LINK_RATE_SET in order to operate in jitter cleaning
* mode (as opposed to redriver mode). Unfortunately it
@ -1629,7 +1629,7 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
/*
* Ignore the link failure in CI
*
* In fixed enviroments like CI, sometimes unexpected long HPDs are
* In fixed environments like CI, sometimes unexpected long HPDs are
* generated by the displays. If ignore_long_hpd flag is set, such long
* HPDs are ignored. And probably as a consequence of these ignored
* long HPDs, subsequent link trainings are failed resulting into CI

4
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -837,7 +837,7 @@ static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
* @state must be recomputed with the updated @limits.
*
* Returns:
* - 0 if the confugration is valid
* - 0 if the configuration is valid
* - %-EAGAIN, if the configuration is invalid and @limits got updated
* with fallback values with which the configuration of all CRTCs in
* @state must be recomputed
@ -2052,7 +2052,7 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
* @intel_dp: DP port object
*
* Prepare an MST link for topology probing, programming the target
* link parameters to DPCD. This step is a requirement of the enumaration
* link parameters to DPCD. This step is a requirement of the enumeration
* of path resources during probing.
*/
void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)

4
drivers/gpu/drm/i915/display/intel_dp_test.c
View File

@ -257,7 +257,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
/*
* FIXME: Ideally pattern should come from DPCD 0x250. As
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
* now for compliance test.
*/
drm_dbg_kms(display->drm,
"Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
@ -275,7 +275,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
/*
* FIXME: Ideally pattern should come from DPCD 0x24A. As
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
* now for compliance test.
*/
drm_dbg_kms(display->drm,
"Set HBR2 compliance Phy Test Pattern\n");

2
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
View File

@ -647,7 +647,7 @@ void intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state,
* @state must be recomputed with the updated @limits.
*
* Returns:
* - 0 if the confugration is valid
* - 0 if the configuration is valid
* - %-EAGAIN, if the configuration is invalid and @limits got updated
* with fallback values with which the configuration of all CRTCs in
* @state must be recomputed

2
drivers/gpu/drm/i915/display/intel_dpio_phy.c
View File

@ -40,7 +40,7 @@
* VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
* ports. DPIO is the name given to such a display PHY. These PHYs
* don't follow the standard programming model using direct MMIO
* registers, and instead their registers must be accessed trough IOSF
* registers, and instead their registers must be accessed through IOSF
* sideband. VLV has one such PHY for driving ports B and C, and CHV
* adds another PHY for driving port D. Each PHY responds to specific
* IOSF-SB port.

2
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
View File

@ -4372,7 +4372,7 @@ void intel_shared_dpll_init(struct drm_i915_private *i915)
* calling intel_shared_dpll_swap_state().
*
* Returns:
* 0 on success, negative error code on falure.
* 0 on success, negative error code on failure.
*/
int intel_compute_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,

2
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
View File

@ -318,7 +318,7 @@ struct dpll_info {
const struct intel_shared_dpll_funcs *funcs;
/**
* @id: unique indentifier for this DPLL
* @id: unique identifier for this DPLL
*/
enum intel_dpll_id id;

2
drivers/gpu/drm/i915/display/intel_dsb.c
View File

@ -821,7 +821,7 @@ void intel_dsb_irq_handler(struct intel_display *display,
if (crtc->dsb_event) {
/*
* Update vblank counter/timestmap in case it
* Update vblank counter/timestamp in case it
* hasn't been done yet for this frame.
*/
drm_crtc_accurate_vblank_count(&crtc->base);

2
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
View File

@ -582,7 +582,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
/*
* MIPI Sequence from VBT #53 parsing logic
* We have already separated each seqence during bios parsing
* We have already separated each sequence during bios parsing
* Following is generic execution function for any sequence
*/

2
drivers/gpu/drm/i915/display/intel_dvo_dev.h
View File

@ -57,7 +57,7 @@ struct intel_dvo_dev_ops {
* Turn on/off output.
*
* Because none of our dvo drivers support an intermediate power levels,
* we don't expose this in the interfac.
* we don't expose this in the interface.
*/
void (*dpms)(struct intel_dvo_device *dvo, bool enable);

2
drivers/gpu/drm/i915/display/intel_fdi.c
View File

@ -390,7 +390,7 @@ static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
* @state must be recomputed with the updated @limits.
*
* Returns:
* - 0 if the confugration is valid
* - 0 if the configuration is valid
* - %-EAGAIN, if the configuration is invalid and @limits got updated
* with fallback values with which the configuration of all CRTCs
* in @state must be recomputed

2
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
View File

@ -290,7 +290,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
}
/**
* intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
* intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrun reporting state
* @dev_priv: i915 device instance
* @pipe: (CPU) pipe to set state for
* @enable: whether underruns should be reported or not

2
drivers/gpu/drm/i915/display/intel_frontbuffer.c
View File

@ -227,7 +227,7 @@ static void intel_frontbuffer_flush_work(struct work_struct *work)
* @front: GEM object to flush
*
* This function is targeted for our dirty callback for queueing flush when
* dma fence is signales
* dma fence is signals
*/
void intel_frontbuffer_queue_flush(struct intel_frontbuffer *front)
{

8
drivers/gpu/drm/i915/display/intel_hdcp.c
View File

@ -353,7 +353,7 @@ static bool hdcp_key_loadable(struct intel_display *display)
/*
* Another req for hdcp key loadability is enabled state of pll for
* cdclk. Without active crtc we wont land here. So we are assuming that
* cdclk. Without active crtc we won't land here. So we are assuming that
* cdclk is already on.
*/
@ -1550,9 +1550,9 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector)
* with a 50ms delay if not hdcp2 capable for DP/DPMST encoders
* (dock decides to stop advertising hdcp2 capability for some reason).
* The reason being that during suspend resume dock usually keeps the
* HDCP2 registers inaccesible causing AUX error. This wouldn't be a
* HDCP2 registers inaccessible causing AUX error. This wouldn't be a
* big problem if the userspace just kept retrying with some delay while
* it continues to play low value content but most userpace applications
* it continues to play low value content but most userspace applications
* end up throwing an error when it receives one from KMD. This makes
* sure we give the dock and the sink devices to complete its power cycle
* and then try HDCP authentication. The values of 10 and delay of 50ms
@ -2573,7 +2573,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
/*
* During the HDCP encryption session if Type change is requested,
* disable the HDCP and reenable it with new TYPE value.
* disable the HDCP and re-enable it with new TYPE value.
*/
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||

6
drivers/gpu/drm/i915/display/intel_hotplug.c
View File

@ -806,7 +806,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
* of the powerwells.
*
* Since this function can get called in contexts where we're already holding
* dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
* dev->mode_config.mutex, we do the actual hotplug enabling in a separate
* worker.
*
* Also see: intel_hpd_init() and intel_hpd_poll_disable().
@ -823,7 +823,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
/*
* We might already be holding dev->mode_config.mutex, so do this in a
* seperate worker
* separate worker
* As well, there's no issue if we race here since we always reschedule
* this worker anyway
*/
@ -844,7 +844,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
* of the powerwells.
*
* Since this function can get called in contexts where we're already holding
* dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
* dev->mode_config.mutex, we do the actual hotplug enabling in a separate
* worker.
*
* Also used during driver init to initialize connector->polled

2
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
View File

@ -197,7 +197,7 @@ void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
* @bits: bits to enable
* NOTE: the HPD enable bits are modified both inside and outside
* of an interrupt context. To avoid that read-modify-write cycles
* interfer, these bits are protected by a spinlock. Since this
* interfere, these bits are protected by a spinlock. Since this
* function is usually not called from a context where the lock is
* held already, this function acquires the lock itself. A non-locking
* version is also available.

2
drivers/gpu/drm/i915/display/intel_link_bw.c
View File

@ -221,7 +221,7 @@ assert_link_limit_change_valid(struct intel_display *display,
* limits in @new_limits if there is a BW limitation.
*
* Returns:
* - 0 if the confugration is valid
* - 0 if the configuration is valid
* - %-EAGAIN, if the configuration is invalid and @new_limits got updated
* with fallback values with which the configuration of all CRTCs
* in @state must be recomputed

20
drivers/gpu/drm/i915/display/intel_overlay.c
View File

@ -46,7 +46,8 @@
/* Limits for overlay size. According to intel doc, the real limits are:
* Y width: 4095, UV width (planar): 2047, Y height: 2047,
* UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
* the mininum of both. */
* the minimum of both.
*/
#define IMAGE_MAX_WIDTH 2048
#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
/* on 830 and 845 these large limits result in the card hanging */
@ -408,10 +409,12 @@ static int intel_overlay_off(struct intel_overlay *overlay)
drm_WARN_ON(display->drm, !overlay->active);
/* According to intel docs the overlay hw may hang (when switching
/*
* According to intel docs the overlay hw may hang (when switching
* off) without loading the filter coeffs. It is however unclear whether
* this applies to the disabling of the overlay or to the switching off
* of the hw. Do it in both cases */
* of the hw. Do it in both cases.
*/
flip_addr |= OFC_UPDATE;
rq = alloc_request(overlay, intel_overlay_off_tail);
@ -442,16 +445,19 @@ static int intel_overlay_off(struct intel_overlay *overlay)
return i915_active_wait(&overlay->last_flip);
}
/* recover from an interruption due to a signal
* We have to be careful not to repeat work forever an make forward progess. */
/*
* Recover from an interruption due to a signal.
* We have to be careful not to repeat work forever an make forward progress.
*/
static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
{
return i915_active_wait(&overlay->last_flip);
}
/* Wait for pending overlay flip and release old frame.
/*
* Wait for pending overlay flip and release old frame.
* Needs to be called before the overlay register are changed
* via intel_overlay_(un)map_regs
* via intel_overlay_(un)map_regs.
*/
static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
{

2
drivers/gpu/drm/i915/display/intel_pmdemand.c
View File

@ -609,7 +609,7 @@ intel_pmdemand_program_params(struct intel_display *display,
goto unlock;
drm_dbg_kms(display->drm,
"initate pmdemand request values: (0x%x 0x%x)\n",
"initiate pmdemand request values: (0x%x 0x%x)\n",
mod_reg1, mod_reg2);
intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,

5
drivers/gpu/drm/i915/display/intel_pps.c
View File

@ -1501,8 +1501,9 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp,
if (!pps_delays_valid(vbt))
return;
/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
* of 500ms appears to be too short. Ocassionally the panel
/*
* On Toshiba Satellite P50-C-18C system the VBT T12 delay
* of 500ms appears to be too short. Occasionally the panel
* just fails to power back on. Increasing the delay to 800ms
* seems sufficient to avoid this problem.
*/

8
drivers/gpu/drm/i915/display/intel_psr.c
View File

@ -154,7 +154,7 @@
*
* Unfortunately CHICKEN_TRANS itself seems to be double buffered
* and thus won't latch until the first vblank. So with DC states
* enabled the register effctively uses the reset value during DC5
* enabled the register effectively uses the reset value during DC5
* exit+PSR exit sequence, and thus the bit does nothing until
* latched by the vblank that it was trying to prevent from being
* generated in the first place. So we should probably call this
@ -171,7 +171,7 @@
* CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw):
*
* On BDW without this bit is no vblanks whatsoever are
* generated after PSR exit. On HSW this has no apparant effect.
* generated after PSR exit. On HSW this has no apparent effect.
* WaPsrDPRSUnmaskVBlankInSRD says to set this.
*
* The rest of the bits are more self-explanatory and/or
@ -185,7 +185,7 @@
* has_psr + has_panel_replay: Panel Replay
* has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update
*
* Description of some intel_psr varibles. enabled, panel_replay_enabled,
* Description of some intel_psr variables. enabled, panel_replay_enabled,
* sel_update_enabled
*
* enabled (alone): PSR1
@ -1050,7 +1050,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
};
/*
* Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
* comments bellow for more information
* comments below for more information
*/
int tmp;

4
drivers/gpu/drm/i915/display/intel_sdvo.c
View File

@ -1741,8 +1741,8 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
* the sdvo port register, on all other platforms it is part of the dpll
* state. Since the general pipe state readout happens before the
* encoder->get_config we so already have a valid pixel multplier on all
* other platfroms.
* encoder->get_config we so already have a valid pixel multiplier on all
* other platforms.
*/
if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
pipe_config->pixel_multiplier =

2
drivers/gpu/drm/i915/display/intel_sdvo_regs.h
View File

@ -244,7 +244,7 @@ struct intel_sdvo_set_target_input_args {
* Takes a struct intel_sdvo_output_flags of which outputs are targeted by
* future output commands.
*
* Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
* Affected commands include SET_OUTPUT_TIMINGS_PART[12],
* GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
*/
#define SDVO_CMD_SET_TARGET_OUTPUT 0x11

2
drivers/gpu/drm/i915/display/intel_snps_phy.c
View File

@ -522,7 +522,7 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = {
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
};
/* values in the below table are calculted using the algo */
/* values in the below table are calculated using the algo */
static const struct intel_mpllb_state dg2_hdmi_25200 = {
.clock = 25200,
.ref_control =

2
drivers/gpu/drm/i915/display/intel_vblank.c
View File

@ -369,7 +369,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
/*
* Already exiting vblank? If so, shift our position
* so it looks like we're already apporaching the full
* so it looks like we're already approaching the full
* vblank end. This should make the generated timestamp
* more or less match when the active portion will start.
*/

2
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -106,7 +106,7 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
* According to DSC 1.2 spec in Section 4.1 if native_420 is set:
* -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
* height < 8.
* -second_line_offset_adj is 512 as shown by emperical values to yield best chroma
* -second_line_offset_adj is 512 as shown by empirical values to yield best chroma
* preservation in second line.
* -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
* up to 16 fractional bits, we left shift second line offset by 11 to preserve 11

48
drivers/gpu/drm/i915/display/skl_scaler.c
View File

@ -585,31 +585,31 @@ static u16 glk_nearest_filter_coef(int t)
* The letter represents the filter tap (D is the center tap) and the number
* represents the coefficient set for a phase (0-16).
*
* +------------+------------------------+------------------------+
* |Index value | Data value coeffient 1 | Data value coeffient 2 |
* +------------+------------------------+------------------------+
* | 00h | B0 | A0 |
* +------------+------------------------+------------------------+
* | 01h | D0 | C0 |
* +------------+------------------------+------------------------+
* | 02h | F0 | E0 |
* +------------+------------------------+------------------------+
* | 03h | A1 | G0 |
* +------------+------------------------+------------------------+
* | 04h | C1 | B1 |
* +------------+------------------------+------------------------+
* | ... | ... | ... |
* +------------+------------------------+------------------------+
* | 38h | B16 | A16 |
* +------------+------------------------+------------------------+
* | 39h | D16 | C16 |
* +------------+------------------------+------------------------+
* | 3Ah | F16 | C16 |
* +------------+------------------------+------------------------+
* | 3Bh | Reserved | G16 |
* +------------+------------------------+------------------------+
* +------------+--------------------------+--------------------------+
* |Index value | Data value coefficient 1 | Data value coefficient 2 |
* +------------+--------------------------+--------------------------+
* | 00h | B0 | A0 |
* +------------+--------------------------+--------------------------+
* | 01h | D0 | C0 |
* +------------+--------------------------+--------------------------+
* | 02h | F0 | E0 |
* +------------+--------------------------+--------------------------+
* | 03h | A1 | G0 |
* +------------+--------------------------+--------------------------+
* | 04h | C1 | B1 |
* +------------+--------------------------+--------------------------+
* | ... | ... | ... |
* +------------+--------------------------+--------------------------+
* | 38h | B16 | A16 |
* +------------+--------------------------+--------------------------+
* | 39h | D16 | C16 |
* +------------+--------------------------+--------------------------+
* | 3Ah | F16 | C16 |
* +------------+--------------------------+--------------------------+
* | 3Bh | Reserved | G16 |
* +------------+--------------------------+--------------------------+
*
* To enable nearest-neighbor scaling: program scaler coefficents with
* To enable nearest-neighbor scaling: program scaler coefficients with
* the center tap (Dxx) values set to 1 and all other values set to 0 as per
* SCALER_COEFFICIENT_FORMAT
*

4
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@ -1099,7 +1099,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate)
break;
/*
* DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
* while i915 HW rotation is clockwise, thats why this swapping.
* while i915 HW rotation is clockwise, that's why this swapping.
*/
case DRM_MODE_ROTATE_90:
return PLANE_CTL_ROTATE_270;
@ -2997,7 +2997,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
/*
* DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
* while i915 HW rotation is clockwise, thats why this swapping.
* while i915 HW rotation is clockwise, that's why this swapping.
*/
switch (val & PLANE_CTL_ROTATE_MASK) {
case PLANE_CTL_ROTATE_0:

4
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -584,7 +584,7 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
/*
* Per plane DDB entry can in a really worst case be on multiple slices
* but single entry is anyway contigious.
* but single entry is anyway contiguous.
*/
while (start_slice <= end_slice) {
slice_mask |= BIT(start_slice);
@ -3204,7 +3204,7 @@ adjust_wm_latency(struct drm_i915_private *i915,
* WaWmMemoryReadLatency
*
* punit doesn't take into account the read latency so we need
* to add proper adjustement to each valid level we retrieve
* to add proper adjustment to each valid level we retrieve
* from the punit when level 0 response data is 0us.
*/
if (wm[0] == 0) {

2
drivers/gpu/drm/i915/display/vlv_dsi.c
View File

@ -59,7 +59,7 @@ static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
8 * 100), lane_count);
}
/* return pixels equvalent to txbyteclkhs */
/* return pixels equivalent to txbyteclkhs */
static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
u16 burst_mode_ratio)
{

2
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
View File

@ -459,7 +459,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
/*
* rx divider value needs to be updated in the
* two differnt bit fields in the register hence splitting the
* two different bit fields in the register hence splitting the
* rx divider value accordingly
*/
rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;