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ASoC: dt-bindings: meson: convert axg tdm formatters to schema
Convert the DT binding documentation for the Amlogic tdm formatters to schema. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230206153449.596326-3-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
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* Amlogic Audio TDM formatters
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Required properties:
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- compatible: 'amlogic,axg-tdmin' or
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'amlogic,axg-tdmout' or
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'amlogic,g12a-tdmin' or
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'amlogic,g12a-tdmout' or
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'amlogic,sm1-tdmin' or
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'amlogic,sm1-tdmout
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- reg: physical base address of the controller and length of memory
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mapped region.
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- clocks: list of clock phandle, one for each entry clock-names.
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- clock-names: should contain the following:
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* "pclk" : peripheral clock.
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* "sclk" : bit clock.
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* "sclk_sel" : bit clock input multiplexer.
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* "lrclk" : sample clock
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* "lrclk_sel": sample clock input multiplexer
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Optional property:
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- resets: phandle to the dedicated reset line of the tdm formatter.
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Example of TDMOUT_A on the S905X2 SoC:
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tdmout_a: audio-controller@500 {
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compatible = "amlogic,axg-tdmout";
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reg = <0x0 0x500 0x0 0x40>;
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resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
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clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
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clock-names = "pclk", "sclk", "sclk_sel",
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"lrclk", "lrclk_sel";
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};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Audio AXG TDM formatters
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maintainers:
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- Jerome Brunet <jbrunet@baylibre.com>
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properties:
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compatible:
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enum:
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- amlogic,g12a-tdmout
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- amlogic,sm1-tdmout
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- amlogic,axg-tdmout
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- amlogic,g12a-tdmin
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- amlogic,sm1-tdmin
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- amlogic,axg-tdmin
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clocks:
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items:
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- description: Peripheral clock
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- description: Bit clock
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- description: Bit clock input multiplexer
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- description: Sample clock
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- description: Sample clock input multiplexer
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clock-names:
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items:
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- const: pclk
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- const: sclk
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- const: sclk_sel
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- const: lrclk
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- const: lrclk_sel
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reg:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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allOf:
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- $ref: component-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- amlogic,g12a-tdmin
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- amlogic,sm1-tdmin
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- amlogic,g12a-tdmout
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- amlogic,sm1-tdmout
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then:
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required:
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- resets
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else:
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properties:
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resets: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/axg-audio-clkc.h>
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#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
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audio-controller@500 {
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compatible = "amlogic,g12a-tdmout";
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reg = <0x500 0x40>;
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resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
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clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
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clock-names = "pclk", "sclk", "sclk_sel",
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"lrclk", "lrclk_sel";
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};
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