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rk2928: add initial pm support
This commit is contained in:
黄涛
parent
7db28b5ce2
commit
c5066ca248
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@ -14,13 +14,47 @@
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <mach/pmu.h>
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#include <mach/board.h>
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#include <mach/system.h>
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#include <mach/sram.h>
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#include <mach/gpio.h>
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#include <mach/iomux.h>
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#include <mach/cru.h>
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#define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
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#define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
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#define grf_readl(offset) readl_relaxed(RK2928_GRF_BASE + offset)
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#define grf_writel(v, offset) do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
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#define gate_save_soc_clk(val, _save, cons, w_msk) \
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do { \
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(_save) = cru_readl(cons); \
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cru_writel(((~(val) | (_save)) & (w_msk)) | ((w_msk) << 16), cons); \
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} while (0)
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void __sramfunc sram_printch(char byte)
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{
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#ifdef DEBUG_UART_BASE
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u32 clk_gate2, clk_gate4, clk_gate8;
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gate_save_soc_clk(0
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| (1 << CLK_GATE_ACLK_PERIPH % 16)
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| (1 << CLK_GATE_HCLK_PERIPH % 16)
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| (1 << CLK_GATE_PCLK_PERIPH % 16)
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, clk_gate2, CRU_CLKGATES_CON(2), 0
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| (1 << ((CLK_GATE_ACLK_PERIPH % 16) + 16))
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| (1 << ((CLK_GATE_HCLK_PERIPH % 16) + 16))
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| (1 << ((CLK_GATE_PCLK_PERIPH % 16) + 16)));
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gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
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, clk_gate4, CRU_CLKGATES_CON(4),
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(1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
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gate_save_soc_clk((1 << ((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16)),
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clk_gate8, CRU_CLKGATES_CON(8),
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(1 << (((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16) + 16)));
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sram_udelay(1);
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writel_relaxed(byte, DEBUG_UART_BASE);
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dsb();
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@ -28,8 +62,427 @@ void __sramfunc sram_printch(char byte)
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while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
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barrier();
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cru_writel(0xffff0000 | clk_gate2, CRU_CLKGATES_CON(2));
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cru_writel(0xffff0000 | clk_gate4, CRU_CLKGATES_CON(4));
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cru_writel(0xffff0000 | clk_gate8, CRU_CLKGATES_CON(8));
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if (byte == '\n')
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sram_printch('\r');
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#endif
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}
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__weak void __sramfunc ddr_suspend(void) {}
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__weak void __sramfunc ddr_resume(void) {}
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__weak uint32_t __sramfunc ddr_change_freq(uint32_t nMHz) { return nMHz; }
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#ifdef CONFIG_DDR_TEST
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static int ddr_debug=0;
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module_param(ddr_debug, int, 0644);
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static int inline calc_crc32(u32 addr, size_t len)
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{
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return crc32_le(~0, (const unsigned char *)addr, len);
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}
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static void ddr_testmode(void)
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{
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int32_t g_crc1, g_crc2;
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uint32_t nMHz;
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uint32_t n = 0;
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uint32_t min,max;
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extern char _stext[], _etext[];
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if (ddr_debug == 1) {
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max=500;
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min=100;
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for (;;) {
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sram_printascii("\n change freq:");
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g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
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do
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{
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nMHz = min + random32();
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nMHz %= max;
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}while(nMHz < min);
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sram_printhex(nMHz);
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sram_printch(' ');
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nMHz = ddr_change_freq(nMHz);
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sram_printhex(n++);
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sram_printch(' ');
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g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
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if (g_crc1!=g_crc2) {
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sram_printascii("fail\n");
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}
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//ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
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// sram_printascii("change freq success\n");
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}
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} else if(ddr_debug == 2) {
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for (;;) {
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sram_printch(' ');
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sram_printch('9');
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sram_printch('9');
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sram_printch('9');
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sram_printch(' ');
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g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
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nMHz = (random32()>>13);// 16.7s max
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ddr_suspend();
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sram_udelay(nMHz);
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ddr_resume();
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sram_printhex(nMHz);
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sram_printch(' ');
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sram_printhex(n++);
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g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
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if (g_crc1 != g_crc2) {
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sram_printch(' ');
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sram_printch('f');
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sram_printch('a');
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sram_printch('i');
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sram_printch('l');
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}
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// ddr_print("check image crc32 fail!, count:%d\n", n++);
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// sram_printascii("self refresh fail\n");
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//else
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//ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
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// sram_printascii("self refresh success\n");
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}
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} else if (ddr_debug == 3) {
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extern int memtester(void);
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memtester();
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}
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else
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{
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ddr_change_freq(ddr_debug);
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ddr_debug=0;
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}
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}
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#else
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static void ddr_testmode(void) {}
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#endif
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static noinline void rk2928_pm_dump_irq(void)
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{
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u32 irq_gpio = (readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + (IRQ_GPIO0 / 32) * 4) >> (IRQ_GPIO0 % 32)) & 0xF;
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printk("wakeup irq: %08x %08x %08x\n",
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readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 4),
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readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 8),
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readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 12));
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if (irq_gpio & 1)
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printk("wakeup gpio0: %08x\n", readl_relaxed(RK2928_GPIO0_BASE + GPIO_INT_STATUS));
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if (irq_gpio & 2)
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printk("wakeup gpio1: %08x\n", readl_relaxed(RK2928_GPIO1_BASE + GPIO_INT_STATUS));
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if (irq_gpio & 4)
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printk("wakeup gpio2: %08x\n", readl_relaxed(RK2928_GPIO2_BASE + GPIO_INT_STATUS));
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if (irq_gpio & 8)
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printk("wakeup gpio3: %08x\n", readl_relaxed(RK2928_GPIO3_BASE + GPIO_INT_STATUS));
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}
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#define DUMP_GPIO_INTEN(ID) \
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do { \
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u32 en = readl_relaxed(RK2928_GPIO##ID##_BASE + GPIO_INTEN); \
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if (en) { \
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sram_printascii("GPIO" #ID "_INTEN: "); \
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sram_printhex(en); \
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sram_printch('\n'); \
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} \
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} while (0)
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static noinline void rk2928_pm_dump_inten(void)
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{
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DUMP_GPIO_INTEN(0);
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DUMP_GPIO_INTEN(1);
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DUMP_GPIO_INTEN(2);
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DUMP_GPIO_INTEN(3);
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}
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static void pm_pll_wait_lock(int pll_idx)
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{
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u32 pll_state[4] = { 1, 0, 2, 3 };
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u32 bit = 0x10u << pll_state[pll_idx];
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u32 delay = pll_idx == APLL_ID ? 24000000U : 2400000000U;
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while (delay > 0) {
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if (grf_readl(GRF_SOC_STATUS0) & bit)
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break;
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delay--;
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}
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if (delay == 0) {
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//CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
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sram_printch('p');
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sram_printch('l');
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sram_printch('l');
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sram_printhex(pll_idx);
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sram_printch('\n');
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}
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}
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#define power_on_pll(id) \
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cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
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pm_pll_wait_lock((id))
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#define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
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#define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
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static unsigned long save_sp;
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static noinline void interface_ctr_reg_pread(void)
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{
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u32 addr;
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flush_cache_all();
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outer_flush_all();
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local_flush_tlb_all();
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for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)SRAM_DATA_END; addr += PAGE_SIZE)
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readl_relaxed(addr);
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readl_relaxed(RK2928_GRF_BASE);
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readl_relaxed(RK2928_DDR_PCTL_BASE);
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readl_relaxed(RK2928_DDR_PHY_BASE);
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// readl_relaxed(RK2928_I2C1_BASE);
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}
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__weak void board_gpio_suspend(void) {}
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__weak void board_gpio_resume(void) {}
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__weak void __sramfunc board_pmu_suspend(void) {}
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__weak void __sramfunc board_pmu_resume(void) {}
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__weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol) {}
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__weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol) {}
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__weak void rk30_pwm_suspend_voltage_set(void) {}
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__weak void rk30_pwm_resume_voltage_set(void) {}
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__weak void __sramfunc rk30_pwm_logic_suspend_voltage(void) {}
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__weak void __sramfunc rk30_pwm_logic_resume_voltage(void) {}
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static void __sramfunc rk2928_sram_suspend(void)
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{
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u32 cru_clksel0_con;
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u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
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int i;
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sram_printch('5');
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ddr_suspend();
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sram_printch('6');
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rk30_suspend_voltage_set(1000000);
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rk30_pwm_logic_suspend_voltage();
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sram_printch('7');
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for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
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clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
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}
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gate_save_soc_clk(0
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| (1 << CLK_GATE_CORE_PERIPH)
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| (1 << CLK_GATE_DDRPHY_SRC)
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| (1 << CLK_GATE_ACLK_CPU)
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| (1 << CLK_GATE_HCLK_CPU)
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| (1 << CLK_GATE_PCLK_CPU)
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| (1 << CLK_GATE_ACLK_CORE)
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, clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
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if (!(clkgt_regs[8] & (0xf << (CLK_GATE_PCLK_GPIO0 % 16)))) {
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gate_save_soc_clk(0
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| (1 << CLK_GATE_PERIPH_SRC % 16)
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| (1 << CLK_GATE_PCLK_PERIPH % 16)
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, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
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} else {
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gate_save_soc_clk(0, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
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}
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gate_save_soc_clk(0
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| (1 << CLK_GATE_ACLK_STRC_SYS % 16)
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| (1 << CLK_GATE_ACLK_INTMEM % 16)
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, clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
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gate_save_soc_clk(0
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| (1 << CLK_GATE_PCLK_GRF % 16)
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| (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
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, clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
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gate_save_soc_clk(0, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
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gate_save_soc_clk(0
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| (1 << CLK_GATE_CLK_L2C % 16)
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, clkgt_regs[9], CRU_CLKGATES_CON(9), 0x07ff);
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board_pmu_suspend();
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cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
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cru_writel((0x1f << 16) | 0x1f, CRU_CLKSELS_CON(0));
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dsb();
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wfi();
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cru_writel((0x1f << 16) | cru_clksel0_con, CRU_CLKSELS_CON(0));
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board_pmu_resume();
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for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
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cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
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}
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sram_printch('7');
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rk30_pwm_logic_resume_voltage();
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rk30_suspend_voltage_resume(1100000);
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sram_printch('6');
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ddr_resume();
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sram_printch('5');
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}
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static void noinline rk2928_suspend(void)
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{
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DDR_SAVE_SP(save_sp);
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rk2928_sram_suspend();
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DDR_RESTORE_SP(save_sp);
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}
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static int rk2928_pm_enter(suspend_state_t state)
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{
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u32 i;
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u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
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u32 clk_sel0, clk_sel1, clk_sel10;
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u32 cru_mode_con;
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// dump GPIO INTEN for debug
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rk2928_pm_dump_inten();
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sram_printch('0');
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#ifdef CONFIG_DDR_TEST
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// memory tester
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if (ddr_debug != 0)
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ddr_testmode();
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#endif
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sram_printch('1');
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local_fiq_disable();
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for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
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clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
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}
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gate_save_soc_clk(0
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| (1 << CLK_GATE_CORE_PERIPH)
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| (1 << CLK_GATE_DDRPHY_SRC)
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| (1 << CLK_GATE_ACLK_CPU)
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| (1 << CLK_GATE_HCLK_CPU)
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| (1 << CLK_GATE_PCLK_CPU)
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| (1 << CLK_GATE_ACLK_CORE)
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, clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
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gate_save_soc_clk(0, clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
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gate_save_soc_clk(0
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| (1 << CLK_GATE_PERIPH_SRC % 16)
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| (1 << CLK_GATE_PCLK_PERIPH % 16)
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| (1 << CLK_GATE_ACLK_PERIPH % 16)
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, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
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gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xff9f);
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gate_save_soc_clk(0
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| (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16)
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| (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16)
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| (1 << CLK_GATE_ACLK_CPU_PERI % 16)
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| (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16)
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| (1 << CLK_GATE_ACLK_STRC_SYS % 16)
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| (1 << CLK_GATE_ACLK_INTMEM % 16)
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, clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
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gate_save_soc_clk(0
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| (1 << CLK_GATE_PCLK_GRF % 16)
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| (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
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, clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
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gate_save_soc_clk(0, clkgt_regs[6], CRU_CLKGATES_CON(6), 0xffff);
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gate_save_soc_clk(0
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|(1 << CLK_GATE_PCLK_PWM01%16)
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, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
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gate_save_soc_clk(0, clkgt_regs[8], CRU_CLKGATES_CON(8), 0x01ff);
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gate_save_soc_clk(0
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| (1 << CLK_GATE_CLK_L2C % 16)
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| (1 << CLK_GATE_HCLK_PERI_ARBI % 16)
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| (1 << CLK_GATE_ACLK_PERI_NIU % 16)
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, clkgt_regs[9], CRU_CLKGATES_CON(9), 0x07ff);
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sram_printch('2');
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cru_mode_con = cru_readl(CRU_MODE_CON);
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//cpll
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cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
|
||||
|
||||
//gpll
|
||||
clk_sel10 = cru_readl(CRU_CLKSELS_CON(10));
|
||||
cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
|
||||
cru_writel(PERI_SET_ACLK_DIV(1)
|
||||
| PERI_SET_A2H_RATIO(RATIO_11)
|
||||
| PERI_SET_A2P_RATIO(RATIO_11)
|
||||
, CRU_CLKSELS_CON(10));
|
||||
|
||||
//apll
|
||||
clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
|
||||
clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
|
||||
cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
|
||||
cru_writel(CLK_CORE_DIV(1) | ACLK_CPU_DIV(1), CRU_CLKSELS_CON(0));
|
||||
cru_writel(CLK_CORE_PERI_DIV(1) | ACLK_CORE_DIV(1) | HCLK_CPU_DIV(1) | PCLK_CPU_DIV(1), CRU_CLKSELS_CON(1));
|
||||
|
||||
sram_printch('3');
|
||||
rk30_pwm_suspend_voltage_set();
|
||||
|
||||
board_gpio_suspend();
|
||||
|
||||
interface_ctr_reg_pread();
|
||||
|
||||
sram_printch('4');
|
||||
rk2928_suspend();
|
||||
sram_printch('4');
|
||||
|
||||
board_gpio_resume();
|
||||
rk30_pwm_resume_voltage_set();
|
||||
sram_printch('3');
|
||||
|
||||
//apll
|
||||
cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
|
||||
cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
|
||||
cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);
|
||||
|
||||
//gpll
|
||||
cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
|
||||
cru_writel(clk_sel10, CRU_CLKSELS_CON(10));
|
||||
cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
|
||||
|
||||
//cpll
|
||||
cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
|
||||
|
||||
sram_printch('2');
|
||||
|
||||
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
|
||||
cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
|
||||
}
|
||||
|
||||
local_fiq_enable();
|
||||
sram_printch('1');
|
||||
|
||||
sram_printascii("0\n");
|
||||
|
||||
rk2928_pm_dump_irq();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk2928_pm_prepare(void)
|
||||
{
|
||||
/* disable entering idle by disable_hlt() */
|
||||
disable_hlt();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk2928_pm_finish(void)
|
||||
{
|
||||
enable_hlt();
|
||||
}
|
||||
|
||||
static struct platform_suspend_ops rk2928_pm_ops = {
|
||||
.enter = rk2928_pm_enter,
|
||||
.valid = suspend_valid_only_mem,
|
||||
.prepare = rk2928_pm_prepare,
|
||||
.finish = rk2928_pm_finish,
|
||||
};
|
||||
|
||||
static int __init rk2928_pm_init(void)
|
||||
{
|
||||
suspend_set_ops(&rk2928_pm_ops);
|
||||
|
||||
#ifdef CONFIG_EARLYSUSPEND
|
||||
pm_set_vt_switch(0); /* disable vt switch while suspend */
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
__initcall(rk2928_pm_init);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user