From c4fe5a9f379055ce0ec930f6495ae62aad237b89 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 11 Aug 2026 18:44:43 +0300 Subject: [PATCH] phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate Calculating 'sdm' fraction in rk_hdptx_phy_clk_calc_rate_from_pll_cfg() could trigger a divide-by-zero, as it uses div_u64() with a denominator read directly from hardware: the values ropll_hw.sdm_deno, ropll_hw.sdc_deno, ropll_hw.sdc_n, and ropll_hw.sdc_num are populated from PLL registers which, in theory, could be left by the bootloader uninitialized/misconfigured. Provide the necessary sanitization to avoid trusting the hardware state. Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com?part=1 Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from PLL config") Tested-by: Diederik de Haas # NanoPC-T6 LTS Reviewed-by: Dmitry Baryshkov Reviewed-by: Andy Yan Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260811-hdptx-clk-fixes-v6-2-75bca0ee5753@collabora.com Signed-off-by: Vinod Koul --- .../phy/rockchip/phy-rockchip-samsung-hdptx.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 710603afff86..d67ced2bf7b2 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -2270,10 +2270,20 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx) fout = PLL_REF_CLK * ropll_hw.pms_mdiv; if (ropll_hw.sdm_en) { + val = 16U * ropll_hw.sdm_deno * + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num); + if (!val) { + /* + * The PLL config currently stored in hardware can't be + * translated into a rate. The next .set_rate() should + * program a valid configuration and help with recovery. + */ + dev_dbg(hdptx->dev, "Invalid ROPLL hw state: deno == 0\n"); + return 0; + } + sdm = div_u64(PLL_REF_CLK * ropll_hw.sdc_deno * - ropll_hw.pms_mdiv * ropll_hw.sdm_num, - 16 * ropll_hw.sdm_deno * - (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num)); + ropll_hw.pms_mdiv * ropll_hw.sdm_num, val); if (ropll_hw.sdm_num_sign) fout = fout - sdm;