staging: rtl8192e: renamed variable bRegBW40MHz

Coding style issue, checkpatch Avoid CamelCase,
rename it bRegBW40MHz -> reg_bw_40mhz

Signed-off-by: Gary Rookard <garyrookard@fastmail.org>
Link: https://lore.kernel.org/r/20231205231623.23070-4-garyrookard@fastmail.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gary Rookard 2023-12-05 18:16:21 -05:00 committed by Greg Kroah-Hartman
parent 0e3a515206
commit c4dc2c60ce
2 changed files with 6 additions and 6 deletions

View File

@ -94,7 +94,7 @@ enum ht_aggre_mode {
struct rt_hi_throughput {
u8 enable_ht;
u8 current_ht_support;
u8 bRegBW40MHz;
u8 reg_bw_40mhz;
u8 cur_bw_40mhz;
u8 reg_short_gi_40mhz;
u8 bCurShortGI40MHz;

View File

@ -74,9 +74,9 @@ void ht_update_default_setting(struct rtllib_device *ieee)
ht_info->reg_short_gi_20mhz = 1;
ht_info->reg_short_gi_40mhz = 1;
ht_info->bRegBW40MHz = 1;
ht_info->reg_bw_40mhz = 1;
if (ht_info->bRegBW40MHz)
if (ht_info->reg_bw_40mhz)
ht_info->bRegSuppCCK = 1;
else
ht_info->bRegSuppCCK = true;
@ -275,7 +275,7 @@ void HTConstructCapabilityElement(struct rtllib_device *ieee, u8 *posHTCap,
if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))
pCapELE->ChlWidth = 0;
else
pCapELE->ChlWidth = (pHT->bRegBW40MHz ? 1 : 0);
pCapELE->ChlWidth = (pHT->reg_bw_40mhz ? 1 : 0);
pCapELE->MimoPwrSave = pHT->self_mimo_ps;
pCapELE->GreenField = 0;
@ -286,7 +286,7 @@ void HTConstructCapabilityElement(struct rtllib_device *ieee, u8 *posHTCap,
pCapELE->RxSTBC = 0;
pCapELE->DelayBA = 0;
pCapELE->MaxAMSDUSize = (MAX_RECEIVE_BUFFER_SIZE >= 7935) ? 1 : 0;
pCapELE->DssCCk = ((pHT->bRegBW40MHz) ? (pHT->bRegSuppCCK ? 1 : 0) : 0);
pCapELE->DssCCk = ((pHT->reg_bw_40mhz) ? (pHT->bRegSuppCCK ? 1 : 0) : 0);
pCapELE->PSMP = 0;
pCapELE->LSigTxopProtect = 0;
@ -734,7 +734,7 @@ void HTSetConnectBwMode(struct rtllib_device *ieee,
{
struct rt_hi_throughput *ht_info = ieee->ht_info;
if (!ht_info->bRegBW40MHz)
if (!ht_info->reg_bw_40mhz)
return;
if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))