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arm64: dts: qcom: sdm670: add lpi pinctrl

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The Snapdragon 670 has a separate TLMM for audio pins. Add the device
node for it.

Also add reserved GPIOs for the Pixel 3a, which blocks access to the
sensor GPIOs.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Link: https://lore.kernel.org/r/20260331200658.1306-5-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Richard Acayan 2026-03-31 16:06:58 -04:00 committed by Bjorn Andersson
parent 7fb3d0512d
commit c4b423835e
1 changed files with 73 additions and 0 deletions
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73
arch/arm64/boot/dts/qcom/sdm670.dtsi
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@ -2300,5 +2300,78 @@ cpufreq_hw: cpufreq@17d43000 {
#freq-domain-cells = <1>;
};
lpi_tlmm: pinctrl@62b40000 {
compatible = "qcom,sdm670-lpass-lpi-pinctrl";
reg = <0 0x62b40000 0 0x20000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 32>;
cdc_pdm_default: cdc-pdm-default-state {
clk-pins {
pins = "gpio18";
function = "slimbus_clk";
drive-strength = <4>;
output-low;
};
sync-pins {
pins = "gpio19";
function = "pdm_sync";
drive-strength = <4>;
output-low;
};
tx-pins {
pins = "gpio20";
function = "pdm_tx";
drive-strength = <8>;
};
rx-pins {
pins = "gpio21", "gpio23", "gpio25";
function = "pdm_rx";
drive-strength = <4>;
output-low;
};
};
cdc_comp_default: cdc-comp-default-state {
pins = "gpio22", "gpio24";
function = "comp_rx";
drive-strength = <4>;
};
cdc_dmic_default: cdc-dmic-default-state {
clk1-pins {
pins = "gpio26";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
clk2-pins {
pins = "gpio28";
function = "dmic2_clk";
drive-strength = <8>;
output-high;
};
data1-pins {
pins = "gpio27";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
data2-pins {
pins = "gpio29";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
};
};
};