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drm/i915/ddi: Define LT Phy Swing tables

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Define and initialize LT Phy Swing tables for DP 1.4, 2.1 and eDp.
HDMI TMDS is not needed since LT Phy H/w handles that.

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-19-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal 2025-11-01 08:55:06 +05:30
parent 109289252f
commit c4b2da6dc1
2 changed files with 89 additions and 1 deletions
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81
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
View File

@ -10,6 +10,7 @@
#include "intel_display_types.h"
#include "intel_display_utils.h"
#include "intel_dp.h"
#include "intel_lt_phy.h"
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
* them for both DP and FDI transports, allowing those ports to
@ -1115,6 +1116,69 @@ static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
.num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
};
/* DP1.4 */
static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_dp14[] = {
{ .lt = { 1, 0, 0, 21, 0 } },
{ .lt = { 1, 1, 0, 24, 3 } },
{ .lt = { 1, 2, 0, 28, 7 } },
{ .lt = { 0, 3, 0, 35, 13 } },
{ .lt = { 1, 1, 0, 27, 0 } },
{ .lt = { 1, 2, 0, 31, 4 } },
{ .lt = { 0, 3, 0, 39, 9 } },
{ .lt = { 1, 2, 0, 35, 0 } },
{ .lt = { 0, 3, 0, 41, 7 } },
{ .lt = { 0, 3, 0, 48, 0 } },
};
/* DP2.1 */
static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_uhbr[] = {
{ .lt = { 0, 0, 0, 48, 0 } },
{ .lt = { 0, 0, 0, 43, 5 } },
{ .lt = { 0, 0, 0, 40, 8 } },
{ .lt = { 0, 0, 0, 37, 11 } },
{ .lt = { 0, 0, 0, 33, 15 } },
{ .lt = { 0, 0, 2, 46, 0 } },
{ .lt = { 0, 0, 2, 42, 4 } },
{ .lt = { 0, 0, 2, 38, 8 } },
{ .lt = { 0, 0, 2, 35, 11 } },
{ .lt = { 0, 0, 2, 33, 13 } },
{ .lt = { 0, 0, 4, 44, 0 } },
{ .lt = { 0, 0, 4, 40, 4 } },
{ .lt = { 0, 0, 4, 37, 7 } },
{ .lt = { 0, 0, 4, 33, 11 } },
{ .lt = { 0, 0, 8, 40, 0 } },
{ .lt = { 1, 0, 2, 26, 2 } },
};
/* eDp */
static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
{ .lt = { 1, 0, 0, 12, 0 } },
{ .lt = { 1, 1, 0, 13, 1 } },
{ .lt = { 1, 2, 0, 15, 3 } },
{ .lt = { 1, 3, 0, 19, 7 } },
{ .lt = { 1, 1, 0, 14, 0 } },
{ .lt = { 1, 2, 0, 16, 2 } },
{ .lt = { 1, 3, 0, 21, 5 } },
{ .lt = { 1, 2, 0, 18, 0 } },
{ .lt = { 1, 3, 0, 22, 4 } },
{ .lt = { 1, 3, 0, 26, 0 } },
};
static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
.entries = _xe3plpd_lt_trans_dp14,
.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
};
static const struct intel_ddi_buf_trans xe3plpd_lt_trans_uhbr = {
.entries = _xe3plpd_lt_trans_uhbr,
.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_uhbr),
};
static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = {
.entries = _xe3plpd_lt_trans_edp,
.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp),
};
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@ -1707,11 +1771,26 @@ mtl_get_c20_buf_trans(struct intel_encoder *encoder,
return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);
}
static const struct intel_ddi_buf_trans *
xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))
return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
else
return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
}
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
if (DISPLAY_VER(display) >= 14) {
if (HAS_LT_PHY(display)) {
encoder->get_buf_trans = xe3plpd_get_lt_buf_trans;
} else if (DISPLAY_VER(display) >= 14) {
if (intel_encoder_is_c10phy(encoder))
encoder->get_buf_trans = mtl_get_c10_buf_trans;
else

9
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
View File

@ -50,6 +50,14 @@ struct dg2_snps_phy_buf_trans {
u8 post_cursor;
};
struct xe3plpd_lt_phy_buf_trans {
u8 txswing;
u8 txswing_level;
u8 pre_cursor;
u8 main_cursor;
u8 post_cursor;
};
union intel_ddi_buf_trans_entry {
struct hsw_ddi_buf_trans hsw;
struct bxt_ddi_buf_trans bxt;
@ -57,6 +65,7 @@ union intel_ddi_buf_trans_entry {
struct icl_mg_phy_ddi_buf_trans mg;
struct tgl_dkl_phy_ddi_buf_trans dkl;
struct dg2_snps_phy_buf_trans snps;
struct xe3plpd_lt_phy_buf_trans lt;
};
struct intel_ddi_buf_trans {