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arm64: dts: renesas: rzt2h-n2h-evk: Remove unused MII/GMII pins
Remove the unused TXER, RXER, CRS, and COL pinmux configurations from the
gmac1 (ETH3) and gmac2 (ETH2) pin groups.
The Ethernet interfaces on both the RZ/T2H and RZ/N2H EVK boards operate
in RGMII mode, which does not utilize these extra MII/GMII sideband signal
pins. Update the board switch configuration comments to accurately reflect
the pin ranges that are actually in use.
Fixes: b272b94fd2 ("arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260528134752.79813-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
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4e66920563
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c49ad13019
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@ -256,8 +256,7 @@ can0_pins: can0-pins {
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/*
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* GMAC1 Pin Configuration:
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*
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* SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and
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* P35_0-P35_2 for Ethernet port 3
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* SW2[8] ON - use pins P33_2-P33_7 and P34_0-P34_5 for Ethernet port 3
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*/
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gmac1_pins: gmac1-pins {
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pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
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@ -272,10 +271,6 @@ gmac1_pins: gmac1-pins {
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<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
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<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
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<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
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<RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
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<RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
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<RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
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<RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
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<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
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<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
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<RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */
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@ -286,8 +281,7 @@ gmac1_pins: gmac1-pins {
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* GMAC2 Pin Configuration:
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*
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* SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
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* SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5
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* for Ethernet port 2
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* SW2[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2
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*/
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gmac2_pins: gmac2-pins {
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pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
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@ -302,10 +296,6 @@ gmac2_pins: gmac2-pins {
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<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
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<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
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<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
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<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
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<RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
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<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
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<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
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<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
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<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
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<RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */
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@ -339,9 +339,7 @@ can1_pins: can1-pins {
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/*
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* GMAC1 Pin Configuration:
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*
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* DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6
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* for Ethernet port 3
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* DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3
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* DSW5[8] ON - use pins P33_2-P33_7 and P34_0-P34_6 for Ethernet port 3
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*/
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gmac1_pins: gmac1-pins {
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pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
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@ -356,10 +354,6 @@ gmac1_pins: gmac1-pins {
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<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
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<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
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<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
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<RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
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<RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
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<RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
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<RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
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<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
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<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
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<RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */
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@ -370,8 +364,7 @@ gmac1_pins: gmac1-pins {
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* GMAC2 Pin Configuration:
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*
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* DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
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* DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
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* P31_2, P31_4 and P31_5 are used for Ethernet port 2
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* DSW5[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2
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* DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14
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*/
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gmac2_pins: gmac2-pins {
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@ -387,10 +380,6 @@ gmac2_pins: gmac2-pins {
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<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
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<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
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<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
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<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
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<RZT2H_PORT_PINMUX(31, 1, 0xf)>, /* ETH2_RXER */
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<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
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<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
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<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
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<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
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<RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */
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