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scsi: ufs: ufs-pci: Add MCQ support for Intel UFS 4.0 controllers

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The Intel UFS 4.0 PCI variant (PCI ID 8086:D335) advertises MCQ support
in its capability register. However, ufshcd_alloc_mcq() also requires an
.op_runtime_config hook to locate the per-queue operation and runtime
(OPR) register blocks, which was not provided by this variant operations
table.

As a result, MCQ initialization fails and ufshcd_add_scsi_host() prints
"MCQ mode is disabled, err=%d\n" before falling back to legacy
single-doorbell (SDB) mode.

Add ufs_intel_mcq_config_resource() to initialize the MCQ configuration
base and add ufs_intel_op_runtime_config() to set up the OPR register
offsets and stride.

Wire both hooks into the variant operations table so MCQ is enabled when
supported by the hardware.

Fixes: 096cd6b7ad ("scsi: ufs: ufs-pci: Add support for Intel Nova Lake")
Signed-off-by: sangram kumar yerra <sangram.k.y@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Link: https://patch.msgid.link/20260818112830.453402-3-sangram.k.y@intel.com
Signed-off-by: Martin K. Petersen (Oracle) <mkp@kernel.org>
This commit is contained in:
sangram kumar yerra 2026-08-18 16:58:30 +05:30 committed by Martin K. Petersen (Oracle)
parent ef675ea168
commit c46cc9cee3
1 changed files with 39 additions and 0 deletions
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39
drivers/ufs/host/ufshcd-pci.c
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@ -460,6 +460,43 @@ static int ufs_intel_mtl_init(struct ufs_hba *hba)
return ufs_intel_common_init(hba);
}
static int ufs_intel_mcq_config_resource(struct ufs_hba *hba)
{
hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba);
return 0;
}
/*
* This Intel UFS4.0 controller maps MCQ doorbell and interrupt-status
* registers into the same PCI BAR as the legacy HCI space, at this
* fixed offset/stride.
*/
#define UFS_INTEL_SQDAO0 0x2800
#define UFS_INTEL_SQISAO0 0x2814
#define UFS_INTEL_CQDAO0 0x281C
#define UFS_INTEL_CQISAO0 0x2824
#define UFS_INTEL_MCQ_STRIDE 0x30
static int ufs_intel_op_runtime_config(struct ufs_hba *hba)
{
struct ufshcd_mcq_opr_info_t *opr;
int i;
hba->mcq_opr[OPR_SQD].offset = UFS_INTEL_SQDAO0;
hba->mcq_opr[OPR_SQIS].offset = UFS_INTEL_SQISAO0;
hba->mcq_opr[OPR_CQD].offset = UFS_INTEL_CQDAO0;
hba->mcq_opr[OPR_CQIS].offset = UFS_INTEL_CQISAO0;
for (i = 0; i < OPR_MAX; i++) {
opr = &hba->mcq_opr[i];
opr->stride = UFS_INTEL_MCQ_STRIDE;
opr->base = hba->mmio_base + opr->offset;
}
return 0;
}
static int ufs_qemu_get_hba_mac(struct ufs_hba *hba)
{
return MAX_SUPP_MAC;
@ -547,6 +584,8 @@ static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
.hce_enable_notify = ufs_intel_hce_enable_notify,
.link_startup_notify = ufs_intel_link_startup_notify,
.pwr_change_notify = ufs_intel_nvl_pwr_change_notify,
.mcq_config_resource = ufs_intel_mcq_config_resource,
.op_runtime_config = ufs_intel_op_runtime_config,
.resume = ufs_intel_resume,
.device_reset = ufs_intel_device_reset,
};