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arm64: dts: qcom: sm8250: Fix the PCIe iommu-map entries
The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commitccb2fd725d("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes:e53bdfc009("arm64: dts: qcom: sm8250: Add PCIe support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-7-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -2199,8 +2199,8 @@ pcie0: pcie@1c00000 {
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"tbu",
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"ddrss_sf_tbu";
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iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
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<0x100 &apps_smmu 0x1c01 0x1>;
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iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
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<0x100 &apps_smmu 0x1c01 0x0 0x1>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "pci";
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@ -2326,8 +2326,8 @@ pcie1: pcie@1c08000 {
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assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
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<0x100 &apps_smmu 0x1c81 0x1>;
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iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
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<0x100 &apps_smmu 0x1c81 0x0 0x1>;
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resets = <&gcc GCC_PCIE_1_BCR>;
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reset-names = "pci";
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@ -2453,8 +2453,8 @@ pcie2: pcie@1c10000 {
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assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
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<0x100 &apps_smmu 0x1d01 0x1>;
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iommu-map = <0x0 &apps_smmu 0x1d00 0x0 0x1>,
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<0x100 &apps_smmu 0x1d01 0x0 0x1>;
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resets = <&gcc GCC_PCIE_2_BCR>;
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reset-names = "pci";
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