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https://github.com/torvalds/linux.git
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Merge branch 'pci/controller/apple'
- Skip ports disabled in DT when setting up ports (Janne Grunau)
- Add t6020 compatible string (Alyssa Rosenzweig)
- Extract ECAM bridge creation helper from pci_host_common_probe() to
separate driver-specific things like MSI from PCI things (Marc Zyngier)
- Dynamically allocate RID-to_SID bitmap to prepare for SoCs with varying
capabilities (Marc Zyngier)
- Directly set/clear INTx mask bits because T602x dropped the accessors
that could do this without locking (Marc Zyngier)
- Move port PHY registers to their own reg items to accommodate T602x,
which moves them around; retain default offsets for existing DTs that
lack phy%d entries with the reg offsets (Hector Martin)
- Stop polling for core refclk, which doesn't work on T602x and the
bootloader has already done anyway (Hector Martin)
- Use gpiod_set_value_cansleep() when asserting PERST# in probe because
we're allowed to sleep there (Hector Martin)
- Move register offsets into SoC-specific structure (Hector Martin)
- Add T602x PCIe support (Hector Martin)
* pci/controller/apple:
PCI: apple: Add T602x PCIe support
PCI: apple: Abstract register offsets via a SoC-specific structure
PCI: apple: Use gpiod_set_value_cansleep in probe flow
PCI: apple: Drop poll for CORE_RC_PHYIF_STAT_REFCLK
PCI: apple: Move port PHY registers to their own reg items
PCI: apple: Fix missing OF node reference in apple_pcie_setup_port
PCI: apple: Move away from INTMSK{SET,CLR} for INTx and private interrupts
PCI: apple: Dynamically allocate RID-to_SID bitmap
PCI: apple: Move over to standalone probing
PCI: ecam: Allow cfg->priv to be pre-populated from the root port device
PCI: host-generic: Extract an ECAM bridge creation helper from pci_host_common_probe()
dt-bindings: pci: apple,pcie: Add t6020 compatible string
PCI: apple: Set only available ports up
This commit is contained in:
Bjorn Helgaas
commit
c3b2f9dccb
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@ -17,6 +17,10 @@ description: |
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implements its root ports. But the ATU found on most DesignWare
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PCIe host bridges is absent.
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On systems derived from T602x, the PHY registers are in a region
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separate from the port registers. In that case, there is one PHY
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register range per port register range.
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All root ports share a single ECAM space, but separate GPIOs are
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used to take the PCI devices on those ports out of reset. Therefore
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the standard "reset-gpios" and "max-link-speed" properties appear on
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@ -30,16 +34,18 @@ description: |
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properties:
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compatible:
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items:
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- enum:
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- apple,t8103-pcie
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- apple,t8112-pcie
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- apple,t6000-pcie
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- const: apple,pcie
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oneOf:
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- items:
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- enum:
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- apple,t8103-pcie
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- apple,t8112-pcie
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- apple,t6000-pcie
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- const: apple,pcie
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- const: apple,t6020-pcie
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reg:
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minItems: 3
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maxItems: 6
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maxItems: 10
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reg-names:
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minItems: 3
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@ -50,6 +56,10 @@ properties:
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- const: port1
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- const: port2
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- const: port3
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- const: phy0
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- const: phy1
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- const: phy2
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- const: phy3
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ranges:
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minItems: 2
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@ -98,6 +108,15 @@ allOf:
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maxItems: 5
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interrupts:
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maxItems: 3
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- if:
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properties:
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compatible:
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contains:
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const: apple,t6020-pcie
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then:
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properties:
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reg-names:
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minItems: 10
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examples:
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- |
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@ -49,23 +49,17 @@ static struct pci_config_window *gen_pci_init(struct device *dev,
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return cfg;
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}
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int pci_host_common_probe(struct platform_device *pdev)
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int pci_host_common_init(struct platform_device *pdev,
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const struct pci_ecam_ops *ops)
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{
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struct device *dev = &pdev->dev;
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struct pci_host_bridge *bridge;
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struct pci_config_window *cfg;
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const struct pci_ecam_ops *ops;
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ops = of_device_get_match_data(&pdev->dev);
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if (!ops)
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return -ENODEV;
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bridge = devm_pci_alloc_host_bridge(dev, 0);
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if (!bridge)
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return -ENOMEM;
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platform_set_drvdata(pdev, bridge);
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of_pci_check_probe_only();
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/* Parse and map our Configuration Space windows */
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@ -73,6 +67,8 @@ int pci_host_common_probe(struct platform_device *pdev)
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if (IS_ERR(cfg))
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return PTR_ERR(cfg);
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platform_set_drvdata(pdev, bridge);
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bridge->sysdata = cfg;
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bridge->ops = (struct pci_ops *)&ops->pci_ops;
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bridge->enable_device = ops->enable_device;
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@ -81,6 +77,18 @@ int pci_host_common_probe(struct platform_device *pdev)
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return pci_host_probe(bridge);
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}
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EXPORT_SYMBOL_GPL(pci_host_common_init);
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int pci_host_common_probe(struct platform_device *pdev)
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{
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const struct pci_ecam_ops *ops;
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ops = of_device_get_match_data(&pdev->dev);
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if (!ops)
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return -ENODEV;
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return pci_host_common_init(pdev, ops);
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}
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EXPORT_SYMBOL_GPL(pci_host_common_probe);
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void pci_host_common_remove(struct platform_device *pdev)
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@ -18,6 +18,7 @@
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* Author: Marc Zyngier <maz@kernel.org>
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*/
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#include <linux/bitfield.h>
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#include <linux/gpio/consumer.h>
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#include <linux/kernel.h>
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#include <linux/iopoll.h>
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@ -29,6 +30,7 @@
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#include <linux/of_irq.h>
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#include <linux/pci-ecam.h>
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/* T8103 (original M1) and related SoCs */
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#define CORE_RC_PHYIF_CTL 0x00024
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#define CORE_RC_PHYIF_CTL_RUN BIT(0)
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#define CORE_RC_PHYIF_STAT 0x00028
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@ -39,14 +41,18 @@
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#define CORE_RC_STAT_READY BIT(0)
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#define CORE_FABRIC_STAT 0x04000
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#define CORE_FABRIC_STAT_MASK 0x001F001F
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#define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
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#define CORE_LANE_CFG_REFCLK0REQ BIT(0)
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#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
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#define CORE_LANE_CFG_REFCLK0ACK BIT(2)
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#define CORE_LANE_CFG_REFCLK1ACK BIT(3)
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#define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
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#define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port))
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#define CORE_LANE_CTL_CFGACC BIT(15)
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#define CORE_PHY_DEFAULT_BASE(port) (0x84000 + 0x4000 * (port))
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#define PHY_LANE_CFG 0x00000
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#define PHY_LANE_CFG_REFCLK0REQ BIT(0)
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#define PHY_LANE_CFG_REFCLK1REQ BIT(1)
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#define PHY_LANE_CFG_REFCLK0ACK BIT(2)
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#define PHY_LANE_CFG_REFCLK1ACK BIT(3)
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#define PHY_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
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#define PHY_LANE_CFG_REFCLKCGEN (BIT(30) | BIT(31))
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#define PHY_LANE_CTL 0x00004
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#define PHY_LANE_CTL_CFGACC BIT(15)
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#define PORT_LTSSMCTL 0x00080
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#define PORT_LTSSMCTL_START BIT(0)
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@ -100,7 +106,7 @@
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#define PORT_REFCLK_CGDIS BIT(8)
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#define PORT_PERST 0x00814
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#define PORT_PERST_OFF BIT(0)
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#define PORT_RID2SID(i16) (0x00828 + 4 * (i16))
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#define PORT_RID2SID 0x00828
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#define PORT_RID2SID_VALID BIT(31)
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#define PORT_RID2SID_SID_SHIFT 16
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#define PORT_RID2SID_BUS_SHIFT 8
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@ -118,7 +124,15 @@
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#define PORT_TUNSTAT_PERST_ACK_PEND BIT(1)
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#define PORT_PREFMEM_ENABLE 0x00994
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#define MAX_RID2SID 64
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/* T602x (M2-pro and co) */
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#define PORT_T602X_MSIADDR 0x016c
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#define PORT_T602X_MSIADDR_HI 0x0170
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#define PORT_T602X_PERST 0x082c
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#define PORT_T602X_RID2SID 0x3000
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#define PORT_T602X_MSIMAP 0x3800
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#define PORT_MSIMAP_ENABLE BIT(31)
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#define PORT_MSIMAP_TARGET GENMASK(7, 0)
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/*
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* The doorbell address is set to 0xfffff000, which by convention
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@ -129,10 +143,45 @@
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*/
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#define DOORBELL_ADDR CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR
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struct hw_info {
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u32 phy_lane_ctl;
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u32 port_msiaddr;
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u32 port_msiaddr_hi;
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u32 port_refclk;
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u32 port_perst;
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u32 port_rid2sid;
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u32 port_msimap;
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u32 max_rid2sid;
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};
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static const struct hw_info t8103_hw = {
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.phy_lane_ctl = PHY_LANE_CTL,
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.port_msiaddr = PORT_MSIADDR,
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.port_msiaddr_hi = 0,
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.port_refclk = PORT_REFCLK,
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.port_perst = PORT_PERST,
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.port_rid2sid = PORT_RID2SID,
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.port_msimap = 0,
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.max_rid2sid = 64,
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};
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static const struct hw_info t602x_hw = {
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.phy_lane_ctl = 0,
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.port_msiaddr = PORT_T602X_MSIADDR,
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.port_msiaddr_hi = PORT_T602X_MSIADDR_HI,
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.port_refclk = 0,
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.port_perst = PORT_T602X_PERST,
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.port_rid2sid = PORT_T602X_RID2SID,
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.port_msimap = PORT_T602X_MSIMAP,
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/* 16 on t602x, guess for autodetect on future HW */
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.max_rid2sid = 512,
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};
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struct apple_pcie {
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struct mutex lock;
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struct device *dev;
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void __iomem *base;
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const struct hw_info *hw;
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struct irq_domain *domain;
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unsigned long *bitmap;
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struct list_head ports;
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@ -142,12 +191,14 @@ struct apple_pcie {
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};
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struct apple_pcie_port {
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raw_spinlock_t lock;
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struct apple_pcie *pcie;
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struct device_node *np;
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void __iomem *base;
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void __iomem *phy;
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struct irq_domain *domain;
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struct list_head entry;
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DECLARE_BITMAP(sid_map, MAX_RID2SID);
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unsigned long *sid_map;
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int sid_map_sz;
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int idx;
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};
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@ -261,14 +312,16 @@ static void apple_port_irq_mask(struct irq_data *data)
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{
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struct apple_pcie_port *port = irq_data_get_irq_chip_data(data);
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writel_relaxed(BIT(data->hwirq), port->base + PORT_INTMSKSET);
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guard(raw_spinlock_irqsave)(&port->lock);
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rmw_set(BIT(data->hwirq), port->base + PORT_INTMSK);
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}
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static void apple_port_irq_unmask(struct irq_data *data)
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{
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struct apple_pcie_port *port = irq_data_get_irq_chip_data(data);
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writel_relaxed(BIT(data->hwirq), port->base + PORT_INTMSKCLR);
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guard(raw_spinlock_irqsave)(&port->lock);
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rmw_clear(BIT(data->hwirq), port->base + PORT_INTMSK);
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}
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static bool hwirq_is_intx(unsigned int hwirq)
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@ -372,7 +425,9 @@ static void apple_port_irq_handler(struct irq_desc *desc)
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static int apple_pcie_port_setup_irq(struct apple_pcie_port *port)
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{
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struct fwnode_handle *fwnode = &port->np->fwnode;
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struct apple_pcie *pcie = port->pcie;
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unsigned int irq;
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u32 val = 0;
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/* FIXME: consider moving each interrupt under each port */
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irq = irq_of_parse_and_map(to_of_node(dev_fwnode(port->pcie->dev)),
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@ -387,20 +442,31 @@ static int apple_pcie_port_setup_irq(struct apple_pcie_port *port)
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return -ENOMEM;
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/* Disable all interrupts */
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writel_relaxed(~0, port->base + PORT_INTMSKSET);
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writel_relaxed(~0, port->base + PORT_INTMSK);
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writel_relaxed(~0, port->base + PORT_INTSTAT);
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writel_relaxed(~0, port->base + PORT_LINKCMDSTS);
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irq_set_chained_handler_and_data(irq, apple_port_irq_handler, port);
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/* Configure MSI base address */
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BUILD_BUG_ON(upper_32_bits(DOORBELL_ADDR));
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writel_relaxed(lower_32_bits(DOORBELL_ADDR), port->base + PORT_MSIADDR);
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writel_relaxed(lower_32_bits(DOORBELL_ADDR),
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port->base + pcie->hw->port_msiaddr);
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if (pcie->hw->port_msiaddr_hi)
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writel_relaxed(0, port->base + pcie->hw->port_msiaddr_hi);
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/* Enable MSIs, shared between all ports */
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writel_relaxed(0, port->base + PORT_MSIBASE);
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writel_relaxed((ilog2(port->pcie->nvecs) << PORT_MSICFG_L2MSINUM_SHIFT) |
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PORT_MSICFG_EN, port->base + PORT_MSICFG);
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if (pcie->hw->port_msimap) {
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for (int i = 0; i < pcie->nvecs; i++)
|
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writel_relaxed(FIELD_PREP(PORT_MSIMAP_TARGET, i) |
|
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PORT_MSIMAP_ENABLE,
|
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port->base + pcie->hw->port_msimap + 4 * i);
|
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} else {
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writel_relaxed(0, port->base + PORT_MSIBASE);
|
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val = ilog2(pcie->nvecs) << PORT_MSICFG_L2MSINUM_SHIFT;
|
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}
|
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|
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writel_relaxed(val | PORT_MSICFG_EN, port->base + PORT_MSICFG);
|
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return 0;
|
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}
|
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|
||||
|
|
@ -467,43 +533,47 @@ static int apple_pcie_setup_refclk(struct apple_pcie *pcie,
|
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u32 stat;
|
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int res;
|
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|
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res = readl_relaxed_poll_timeout(pcie->base + CORE_RC_PHYIF_STAT, stat,
|
||||
stat & CORE_RC_PHYIF_STAT_REFCLK,
|
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if (pcie->hw->phy_lane_ctl)
|
||||
rmw_set(PHY_LANE_CTL_CFGACC, port->phy + pcie->hw->phy_lane_ctl);
|
||||
|
||||
rmw_set(PHY_LANE_CFG_REFCLK0REQ, port->phy + PHY_LANE_CFG);
|
||||
|
||||
res = readl_relaxed_poll_timeout(port->phy + PHY_LANE_CFG,
|
||||
stat, stat & PHY_LANE_CFG_REFCLK0ACK,
|
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100, 50000);
|
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if (res < 0)
|
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return res;
|
||||
|
||||
rmw_set(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
|
||||
rmw_set(CORE_LANE_CFG_REFCLK0REQ, pcie->base + CORE_LANE_CFG(port->idx));
|
||||
|
||||
res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
|
||||
stat, stat & CORE_LANE_CFG_REFCLK0ACK,
|
||||
100, 50000);
|
||||
if (res < 0)
|
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return res;
|
||||
|
||||
rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
|
||||
res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
|
||||
stat, stat & CORE_LANE_CFG_REFCLK1ACK,
|
||||
rmw_set(PHY_LANE_CFG_REFCLK1REQ, port->phy + PHY_LANE_CFG);
|
||||
res = readl_relaxed_poll_timeout(port->phy + PHY_LANE_CFG,
|
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stat, stat & PHY_LANE_CFG_REFCLK1ACK,
|
||||
100, 50000);
|
||||
|
||||
if (res < 0)
|
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return res;
|
||||
|
||||
rmw_clear(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
|
||||
if (pcie->hw->phy_lane_ctl)
|
||||
rmw_clear(PHY_LANE_CTL_CFGACC, port->phy + pcie->hw->phy_lane_ctl);
|
||||
|
||||
rmw_set(CORE_LANE_CFG_REFCLKEN, pcie->base + CORE_LANE_CFG(port->idx));
|
||||
rmw_set(PORT_REFCLK_EN, port->base + PORT_REFCLK);
|
||||
rmw_set(PHY_LANE_CFG_REFCLKEN, port->phy + PHY_LANE_CFG);
|
||||
|
||||
if (pcie->hw->port_refclk)
|
||||
rmw_set(PORT_REFCLK_EN, port->base + pcie->hw->port_refclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __iomem *port_rid2sid_addr(struct apple_pcie_port *port, int idx)
|
||||
{
|
||||
return port->base + port->pcie->hw->port_rid2sid + 4 * idx;
|
||||
}
|
||||
|
||||
static u32 apple_pcie_rid2sid_write(struct apple_pcie_port *port,
|
||||
int idx, u32 val)
|
||||
{
|
||||
writel_relaxed(val, port->base + PORT_RID2SID(idx));
|
||||
writel_relaxed(val, port_rid2sid_addr(port, idx));
|
||||
/* Read back to ensure completion of the write */
|
||||
return readl_relaxed(port->base + PORT_RID2SID(idx));
|
||||
return readl_relaxed(port_rid2sid_addr(port, idx));
|
||||
}
|
||||
|
||||
static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
||||
|
|
@ -512,6 +582,8 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
|||
struct platform_device *platform = to_platform_device(pcie->dev);
|
||||
struct apple_pcie_port *port;
|
||||
struct gpio_desc *reset;
|
||||
struct resource *res;
|
||||
char name[16];
|
||||
u32 stat, idx;
|
||||
int ret, i;
|
||||
|
||||
|
|
@ -524,6 +596,10 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
|||
if (!port)
|
||||
return -ENOMEM;
|
||||
|
||||
port->sid_map = devm_bitmap_zalloc(pcie->dev, pcie->hw->max_rid2sid, GFP_KERNEL);
|
||||
if (!port->sid_map)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_property_read_u32_index(np, "reg", 0, &idx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -533,14 +609,28 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
|||
port->pcie = pcie;
|
||||
port->np = np;
|
||||
|
||||
port->base = devm_platform_ioremap_resource(platform, port->idx + 2);
|
||||
raw_spin_lock_init(&port->lock);
|
||||
|
||||
snprintf(name, sizeof(name), "port%d", port->idx);
|
||||
res = platform_get_resource_byname(platform, IORESOURCE_MEM, name);
|
||||
if (!res)
|
||||
res = platform_get_resource(platform, IORESOURCE_MEM, port->idx + 2);
|
||||
|
||||
port->base = devm_ioremap_resource(&platform->dev, res);
|
||||
if (IS_ERR(port->base))
|
||||
return PTR_ERR(port->base);
|
||||
|
||||
snprintf(name, sizeof(name), "phy%d", port->idx);
|
||||
res = platform_get_resource_byname(platform, IORESOURCE_MEM, name);
|
||||
if (res)
|
||||
port->phy = devm_ioremap_resource(&platform->dev, res);
|
||||
else
|
||||
port->phy = pcie->base + CORE_PHY_DEFAULT_BASE(port->idx);
|
||||
|
||||
rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);
|
||||
|
||||
/* Assert PERST# before setting up the clock */
|
||||
gpiod_set_value(reset, 1);
|
||||
gpiod_set_value_cansleep(reset, 1);
|
||||
|
||||
ret = apple_pcie_setup_refclk(pcie, port);
|
||||
if (ret < 0)
|
||||
|
|
@ -550,8 +640,8 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
|||
usleep_range(100, 200);
|
||||
|
||||
/* Deassert PERST# */
|
||||
rmw_set(PORT_PERST_OFF, port->base + PORT_PERST);
|
||||
gpiod_set_value(reset, 0);
|
||||
rmw_set(PORT_PERST_OFF, port->base + pcie->hw->port_perst);
|
||||
gpiod_set_value_cansleep(reset, 0);
|
||||
|
||||
/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
|
||||
msleep(100);
|
||||
|
|
@ -563,7 +653,11 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
|||
return ret;
|
||||
}
|
||||
|
||||
rmw_clear(PORT_REFCLK_CGDIS, port->base + PORT_REFCLK);
|
||||
if (pcie->hw->port_refclk)
|
||||
rmw_clear(PORT_REFCLK_CGDIS, port->base + pcie->hw->port_refclk);
|
||||
else
|
||||
rmw_set(PHY_LANE_CFG_REFCLKCGEN, port->phy + PHY_LANE_CFG);
|
||||
|
||||
rmw_clear(PORT_APPCLK_CGDIS, port->base + PORT_APPCLK);
|
||||
|
||||
ret = apple_pcie_port_setup_irq(port);
|
||||
|
|
@ -571,7 +665,7 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
|||
return ret;
|
||||
|
||||
/* Reset all RID/SID mappings, and check for RAZ/WI registers */
|
||||
for (i = 0; i < MAX_RID2SID; i++) {
|
||||
for (i = 0; i < pcie->hw->max_rid2sid; i++) {
|
||||
if (apple_pcie_rid2sid_write(port, i, 0xbad1d) != 0xbad1d)
|
||||
break;
|
||||
apple_pcie_rid2sid_write(port, i, 0);
|
||||
|
|
@ -584,6 +678,9 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
|
|||
list_add_tail(&port->entry, &pcie->ports);
|
||||
init_completion(&pcie->event);
|
||||
|
||||
/* In the success path, we keep a reference to np around */
|
||||
of_node_get(np);
|
||||
|
||||
ret = apple_pcie_port_register_irqs(port);
|
||||
WARN_ON(ret);
|
||||
|
||||
|
|
@ -716,7 +813,7 @@ static void apple_pcie_disable_device(struct pci_host_bridge *bridge, struct pci
|
|||
for_each_set_bit(idx, port->sid_map, port->sid_map_sz) {
|
||||
u32 val;
|
||||
|
||||
val = readl_relaxed(port->base + PORT_RID2SID(idx));
|
||||
val = readl_relaxed(port_rid2sid_addr(port, idx));
|
||||
if ((val & 0xffff) == rid) {
|
||||
apple_pcie_rid2sid_write(port, idx, 0);
|
||||
bitmap_release_region(port->sid_map, idx, 0);
|
||||
|
|
@ -730,34 +827,14 @@ static void apple_pcie_disable_device(struct pci_host_bridge *bridge, struct pci
|
|||
|
||||
static int apple_pcie_init(struct pci_config_window *cfg)
|
||||
{
|
||||
struct apple_pcie *pcie = cfg->priv;
|
||||
struct device *dev = cfg->parent;
|
||||
struct platform_device *platform = to_platform_device(dev);
|
||||
struct apple_pcie *pcie;
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->dev = dev;
|
||||
|
||||
mutex_init(&pcie->lock);
|
||||
|
||||
pcie->base = devm_platform_ioremap_resource(platform, 1);
|
||||
if (IS_ERR(pcie->base))
|
||||
return PTR_ERR(pcie->base);
|
||||
|
||||
cfg->priv = pcie;
|
||||
INIT_LIST_HEAD(&pcie->ports);
|
||||
|
||||
ret = apple_msi_init(pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for_each_child_of_node_scoped(dev->of_node, of_port) {
|
||||
for_each_available_child_of_node_scoped(dev->of_node, of_port) {
|
||||
ret = apple_pcie_setup_port(pcie, of_port);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "Port %pOF setup fail: %d\n", of_port, ret);
|
||||
dev_err(dev, "Port %pOF setup fail: %d\n", of_port, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
|
@ -776,14 +853,44 @@ static const struct pci_ecam_ops apple_pcie_cfg_ecam_ops = {
|
|||
}
|
||||
};
|
||||
|
||||
static int apple_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct apple_pcie *pcie;
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->dev = dev;
|
||||
pcie->hw = of_device_get_match_data(dev);
|
||||
if (!pcie->hw)
|
||||
return -ENODEV;
|
||||
pcie->base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(pcie->base))
|
||||
return PTR_ERR(pcie->base);
|
||||
|
||||
mutex_init(&pcie->lock);
|
||||
INIT_LIST_HEAD(&pcie->ports);
|
||||
dev_set_drvdata(dev, pcie);
|
||||
|
||||
ret = apple_msi_init(pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return pci_host_common_init(pdev, &apple_pcie_cfg_ecam_ops);
|
||||
}
|
||||
|
||||
static const struct of_device_id apple_pcie_of_match[] = {
|
||||
{ .compatible = "apple,pcie", .data = &apple_pcie_cfg_ecam_ops },
|
||||
{ .compatible = "apple,t6020-pcie", .data = &t602x_hw },
|
||||
{ .compatible = "apple,pcie", .data = &t8103_hw },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, apple_pcie_of_match);
|
||||
|
||||
static struct platform_driver apple_pcie_driver = {
|
||||
.probe = pci_host_common_probe,
|
||||
.probe = apple_pcie_probe,
|
||||
.driver = {
|
||||
.name = "pcie-apple",
|
||||
.of_match_table = apple_pcie_of_match,
|
||||
|
|
|
|||
|
|
@ -84,6 +84,8 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
|
|||
goto err_exit_iomap;
|
||||
}
|
||||
|
||||
cfg->priv = dev_get_drvdata(dev);
|
||||
|
||||
if (ops->init) {
|
||||
err = ops->init(cfg);
|
||||
if (err)
|
||||
|
|
|
|||
|
|
@ -97,6 +97,8 @@ extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
|
|||
#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
|
||||
/* for DT-based PCI controllers that support ECAM */
|
||||
int pci_host_common_probe(struct platform_device *pdev);
|
||||
int pci_host_common_init(struct platform_device *pdev,
|
||||
const struct pci_ecam_ops *ops);
|
||||
void pci_host_common_remove(struct platform_device *pdev);
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user