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ASoC: tlv320aic32x4: clean up driver code formatting and logging
Clean up coding style, SPDX comments, logging calls, and macro definitions across the tlv320aic32x4 driver files: - Convert SPDX comment blocks to // style in bus and clk drivers. - Replace printk(KERN_ERR/DEBUG ...) calls with dev_err/dev_dbg. - Replace msleep(10) with usleep_range(10000, 20000) in the clock driver. - Parenthesize parameters in AIC32X4_REG macro. - Clean up double blank lines and null pointer checks. Assisted-by: Antigravity:gemini-3.5-flash Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Link: https://patch.msgid.link/20260726010519.117805-7-dmitry.torokhov@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Dmitry Torokhov
Mark Brown
parent
e86ba7c5f2
commit
c3ac0aa6c3
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock Tree for the Texas Instruments TLV320AIC32x4
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*
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* Copyright 2019 Annaliese McDermond
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@ -9,6 +9,7 @@
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/device.h>
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@ -57,7 +58,7 @@ static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLLEN, 0);
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AIC32X4_PLLEN, 0);
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}
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static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
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@ -75,7 +76,7 @@ static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
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}
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static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
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struct clk_aic32x4_pll_muldiv *settings)
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struct clk_aic32x4_pll_muldiv *settings)
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{
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/* Change to use regmap_bulk_read? */
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unsigned int val;
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@ -106,19 +107,19 @@ static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
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}
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static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
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struct clk_aic32x4_pll_muldiv *settings)
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struct clk_aic32x4_pll_muldiv *settings)
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{
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int ret;
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/* Change to use regmap_bulk_write for some if not all? */
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ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLL_R_MASK, settings->r);
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AIC32X4_PLL_R_MASK, settings->r);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLL_P_MASK,
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settings->p << AIC32X4_PLL_P_SHIFT);
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AIC32X4_PLL_P_MASK,
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settings->p << AIC32X4_PLL_P_SHIFT);
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if (ret < 0)
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return ret;
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@ -136,23 +137,21 @@ static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
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return 0;
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}
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static unsigned long clk_aic32x4_pll_calc_rate(
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struct clk_aic32x4_pll_muldiv *settings,
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unsigned long parent_rate)
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static unsigned long clk_aic32x4_pll_calc_rate(struct clk_aic32x4_pll_muldiv *settings,
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unsigned long parent_rate)
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{
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u64 rate;
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/*
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* We scale j by 10000 to account for the decimal part of P and divide
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* it back out later.
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*/
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rate = (u64) parent_rate * settings->r *
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((settings->j * 10000) + settings->d);
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rate = (u64)parent_rate * settings->r * ((settings->j * 10000) + settings->d);
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return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
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return (unsigned long)DIV_ROUND_UP_ULL(rate, settings->p * 10000);
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}
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static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
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unsigned long rate, unsigned long parent_rate)
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unsigned long rate, unsigned long parent_rate)
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{
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u64 multiplier;
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@ -165,14 +164,14 @@ static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
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* of the multiplier. This is because we can't do floating point
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* math in the kernel.
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*/
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multiplier = (u64) rate * settings->p * 10000;
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multiplier = (u64)rate * settings->p * 10000;
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do_div(multiplier, parent_rate);
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/*
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* J can't be over 64, so R can scale this.
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* R can't be greater than 4.
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*/
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settings->r = ((u32) multiplier / 640000) + 1;
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settings->r = ((u32)multiplier / 640000) + 1;
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if (settings->r > 4)
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return -1;
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do_div(multiplier, settings->r);
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@ -184,14 +183,14 @@ static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
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return -1;
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/* Figure out the integer part, J, and the fractional part, D. */
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settings->j = (u32) multiplier / 10000;
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settings->d = (u32) multiplier % 10000;
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settings->j = (u32)multiplier / 10000;
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settings->d = (u32)multiplier % 10000;
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return 0;
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}
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static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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struct clk_aic32x4_pll_muldiv settings;
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@ -220,8 +219,8 @@ static int clk_aic32x4_pll_determine_rate(struct clk_hw *hw,
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}
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static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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struct clk_aic32x4_pll_muldiv settings;
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@ -236,7 +235,7 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
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return ret;
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/* 10ms is the delay to wait before the clocks are stable */
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msleep(10);
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usleep_range(10000, 20000);
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return 0;
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}
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@ -261,7 +260,6 @@ static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
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return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
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}
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static const struct clk_ops aic32x4_pll_ops = {
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.prepare = clk_aic32x4_pll_prepare,
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.unprepare = clk_aic32x4_pll_unprepare,
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@ -311,11 +309,11 @@ static void clk_aic32x4_div_unprepare(struct clk_hw *hw)
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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regmap_update_bits(div->regmap, div->reg,
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AIC32X4_DIVEN, 0);
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AIC32X4_DIVEN, 0);
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}
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static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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u8 divisor;
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@ -342,7 +340,7 @@ static int clk_aic32x4_div_determine_rate(struct clk_hw *hw,
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}
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static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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unsigned int val;
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@ -399,7 +397,7 @@ static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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{
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.name = "pll",
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.parent_names =
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(const char* []) { "mclk", "bclk", "gpio", "din" },
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(const char *[]) { "mclk", "bclk", "gpio", "din" },
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.num_parents = 4,
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.ops = &aic32x4_pll_ops,
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.reg = 0,
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@ -414,28 +412,28 @@ static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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},
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{
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.name = "ndac",
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.parent_names = (const char * []) { "codec_clkin" },
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.parent_names = (const char *[]) { "codec_clkin" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_NDAC,
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},
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{
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.name = "mdac",
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.parent_names = (const char * []) { "ndac" },
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.parent_names = (const char *[]) { "ndac" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_MDAC,
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},
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{
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.name = "nadc",
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.parent_names = (const char * []) { "codec_clkin" },
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.parent_names = (const char *[]) { "codec_clkin" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_NADC,
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},
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{
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.name = "madc",
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.parent_names = (const char * []) { "nadc" },
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.parent_names = (const char *[]) { "nadc" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_MADC,
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@ -451,7 +449,7 @@ static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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};
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static struct clk *aic32x4_register_clk(struct device *dev,
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struct aic32x4_clkdesc *desc)
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struct aic32x4_clkdesc *desc)
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{
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struct clk_init_data init;
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struct clk_aic32x4 *priv;
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@ -464,8 +462,8 @@ static struct clk *aic32x4_register_clk(struct device *dev,
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init.flags = 0;
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priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
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if (priv == NULL)
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return (struct clk *) -ENOMEM;
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if (!priv)
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return ERR_PTR(-ENOMEM);
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priv->dev = dev;
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priv->hw.init = &init;
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@ -1,11 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2011-2019 NW Digital Radio
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*
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* Author: Annaliese McDermond <nh6z@nh6z.net>
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*
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* Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
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*
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*/
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#include <linux/i2c.h>
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@ -1,11 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2011-2019 NW Digital Radio
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*
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* Author: Annaliese McDermond <nh6z@nh6z.net>
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*
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* Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
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*
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*/
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#include <linux/spi/spi.h>
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@ -1,7 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* linux/sound/soc/codecs/tlv320aic32x4.c
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*
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* Copyright 2011 Vista Silicon S.L.
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*
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* Author: Javier Martin <javier.martin@vista-silicon.com>
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@ -75,7 +73,7 @@ static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
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};
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static int mic_bias_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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@ -83,25 +81,23 @@ static int mic_bias_event(struct snd_soc_dapm_widget *w,
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case SND_SOC_DAPM_POST_PMU:
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/* Change Mic Bias Registor */
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snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
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AIC32x4_MICBIAS_MASK,
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AIC32X4_MICBIAS_LDOIN |
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AIC32X4_MICBIAS_2075V);
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printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
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AIC32x4_MICBIAS_MASK,
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AIC32X4_MICBIAS_LDOIN |
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AIC32X4_MICBIAS_2075V);
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dev_dbg(component->dev, "Mic Bias will be turned ON\n");
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break;
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case SND_SOC_DAPM_PRE_PMD:
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snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
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AIC32x4_MICBIAS_MASK, 0);
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printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
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__func__);
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AIC32x4_MICBIAS_MASK, 0);
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dev_dbg(component->dev, "Mic Bias will be turned OFF\n");
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break;
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}
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return 0;
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}
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static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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@ -114,7 +110,7 @@ static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
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};
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static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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@ -123,8 +119,7 @@ static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
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val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
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gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
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if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
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printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
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__func__);
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dev_err(component->dev, "MFP2 is not configure as a GPIO output\n");
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return -EINVAL;
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}
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@ -142,7 +137,7 @@ static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
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};
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static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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@ -155,7 +150,7 @@ static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
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};
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static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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@ -164,8 +159,7 @@ static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
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val = snd_soc_component_read(component, AIC32X4_MISOCTL);
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gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
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if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
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printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
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__func__);
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dev_err(component->dev, "MFP4 is not configure as a GPIO output\n");
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return -EINVAL;
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}
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@ -183,7 +177,7 @@ static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
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};
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static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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@ -195,7 +189,7 @@ static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
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};
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static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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@ -204,8 +198,7 @@ static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
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val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
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gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
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if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
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printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
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__func__);
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dev_err(component->dev, "MFP5 is not configure as a GPIO output\n");
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return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -276,53 +269,42 @@ static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
|
|||
|
||||
static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
|
||||
SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
|
||||
AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
|
||||
AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
|
||||
SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
|
||||
SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
|
||||
SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
|
||||
AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
|
||||
tlv_driver_gain),
|
||||
AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, tlv_driver_gain),
|
||||
SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
|
||||
AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
|
||||
tlv_driver_gain),
|
||||
AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, tlv_driver_gain),
|
||||
SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
|
||||
AIC32X4_HPRGAIN, 6, 0x01, 1),
|
||||
AIC32X4_HPRGAIN, 6, 0x01, 1),
|
||||
SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
|
||||
AIC32X4_LORGAIN, 6, 0x01, 1),
|
||||
AIC32X4_LORGAIN, 6, 0x01, 1),
|
||||
SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
|
||||
SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
|
||||
AIC32X4_RMICPGAVOL, 7, 0x01, 1),
|
||||
AIC32X4_RMICPGAVOL, 7, 0x01, 1),
|
||||
|
||||
SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
|
||||
SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
|
||||
|
||||
SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
|
||||
AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
|
||||
AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
|
||||
SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
|
||||
AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
|
||||
AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
|
||||
|
||||
SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
|
||||
|
||||
SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
|
||||
SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
|
||||
SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
|
||||
4, 0x07, 0),
|
||||
SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
|
||||
0, 0x03, 0),
|
||||
SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
|
||||
6, 0x03, 0),
|
||||
SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
|
||||
1, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
|
||||
0, 0x7F, 0),
|
||||
SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
|
||||
3, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
|
||||
3, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
|
||||
0, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
|
||||
0, 0x0F, 0),
|
||||
SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 4, 0x07, 0),
|
||||
SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 0, 0x03, 0),
|
||||
SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 6, 0x03, 0),
|
||||
SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 1, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 0, 0x7F, 0),
|
||||
SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 3, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 3, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 0, 0x1F, 0),
|
||||
SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 0, 0x0F, 0),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
|
||||
|
|
@ -360,21 +342,27 @@ static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_te
|
|||
static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
|
||||
};
|
||||
|
|
@ -391,21 +379,27 @@ static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_te
|
|||
static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
|
||||
};
|
||||
|
|
@ -434,38 +428,38 @@ static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
|
|||
|
||||
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
|
||||
SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in1r_to_rmixer_controls),
|
||||
in1r_to_rmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in2r_to_rmixer_controls),
|
||||
in2r_to_rmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in3r_to_rmixer_controls),
|
||||
in3r_to_rmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in2l_to_rmixer_controls),
|
||||
in2l_to_rmixer_controls),
|
||||
SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
|
||||
cmr_to_rmixer_controls),
|
||||
cmr_to_rmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in1l_to_rmixer_controls),
|
||||
in1l_to_rmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in3l_to_rmixer_controls),
|
||||
in3l_to_rmixer_controls),
|
||||
|
||||
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
|
||||
SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in1l_to_lmixer_controls),
|
||||
in1l_to_lmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in2l_to_lmixer_controls),
|
||||
in2l_to_lmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in3l_to_lmixer_controls),
|
||||
in3l_to_lmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in1r_to_lmixer_controls),
|
||||
in1r_to_lmixer_controls),
|
||||
SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
|
||||
cml_to_lmixer_controls),
|
||||
cml_to_lmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in2r_to_lmixer_controls),
|
||||
in2r_to_lmixer_controls),
|
||||
SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
|
||||
in3r_to_lmixer_controls),
|
||||
in3r_to_lmixer_controls),
|
||||
|
||||
SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
|
||||
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
|
||||
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
|
||||
|
||||
SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
|
||||
|
||||
|
|
@ -624,7 +618,7 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
|
|||
case SND_SOC_DAIFMT_CBC_CFC:
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "aic32x4: invalid clock provider\n");
|
||||
dev_err(component->dev, "invalid clock provider\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -651,19 +645,20 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
|
|||
AIC32X4_IFACE1_DATATYPE_SHIFT);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
|
||||
dev_err(component->dev, "invalid DAI interface format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
aic32x4->fmt = fmt;
|
||||
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE1,
|
||||
AIC32X4_IFACE1_DATATYPE_MASK |
|
||||
AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
|
||||
AIC32X4_IFACE1_DATATYPE_MASK |
|
||||
AIC32X4_IFACE1_MASTER_MASK,
|
||||
iface_reg_1);
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE2,
|
||||
AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
|
||||
AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE3,
|
||||
AIC32X4_BCLKINV_MASK, iface_reg_3);
|
||||
AIC32X4_BCLKINV_MASK, iface_reg_3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -676,14 +671,13 @@ static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
|
|||
static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
|
||||
{
|
||||
snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
|
||||
snd_soc_component_write(component, AIC32X4_DOSRLSB,
|
||||
(dosr & 0xff));
|
||||
snd_soc_component_write(component, AIC32X4_DOSRLSB, dosr & 0xff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
|
||||
u8 r_block, u8 p_block)
|
||||
u8 r_block, u8 p_block)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
|
||||
|
||||
|
|
@ -794,50 +788,39 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
|
|||
(min_mdac * dosr * sample_rate);
|
||||
for (mdac = min_mdac; mdac <= 128; ++mdac) {
|
||||
for (ndac = max_ndac; ndac > 0; --ndac) {
|
||||
dac_clock_rate = ndac * mdac * dosr *
|
||||
sample_rate;
|
||||
if (dac_clock_rate == adc_clock_rate) {
|
||||
if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
|
||||
continue;
|
||||
dac_clock_rate = ndac * mdac * dosr * sample_rate;
|
||||
if (dac_clock_rate != adc_clock_rate)
|
||||
continue;
|
||||
|
||||
clk_set_rate(clocks[0].clk,
|
||||
dac_clock_rate);
|
||||
if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
|
||||
continue;
|
||||
|
||||
clk_set_rate(clocks[1].clk,
|
||||
sample_rate * aosr *
|
||||
madc);
|
||||
clk_set_rate(clocks[2].clk,
|
||||
sample_rate * aosr);
|
||||
aic32x4_set_aosr(component,
|
||||
aosr);
|
||||
clk_set_rate(clocks[0].clk, dac_clock_rate);
|
||||
|
||||
clk_set_rate(clocks[3].clk,
|
||||
sample_rate * dosr *
|
||||
mdac);
|
||||
clk_set_rate(clocks[4].clk,
|
||||
sample_rate * dosr);
|
||||
aic32x4_set_dosr(component,
|
||||
dosr);
|
||||
clk_set_rate(clocks[1].clk, sample_rate * aosr * madc);
|
||||
clk_set_rate(clocks[2].clk, sample_rate * aosr);
|
||||
aic32x4_set_aosr(component, aosr);
|
||||
|
||||
clk_set_rate(clocks[5].clk,
|
||||
sample_rate * channels *
|
||||
bit_depth);
|
||||
clk_set_rate(clocks[3].clk, sample_rate * dosr * mdac);
|
||||
clk_set_rate(clocks[4].clk, sample_rate * dosr);
|
||||
aic32x4_set_dosr(component, dosr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
clk_set_rate(clocks[5].clk,
|
||||
sample_rate * channels * bit_depth);
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dev_err(component->dev,
|
||||
"Could not set clocks to support sample rate.\n");
|
||||
dev_err(component->dev, "Could not set clocks to support sample rate.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int aic32x4_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct snd_soc_component *component = dai->component;
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
|
||||
|
|
@ -850,24 +833,20 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
|
|||
|
||||
switch (params_physical_width(params)) {
|
||||
case 16:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_16BITS << AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
case 20:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
case 24:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
case 32:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
}
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE1,
|
||||
AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
|
||||
AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
|
||||
|
||||
if (params_channels(params) == 1) {
|
||||
dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
|
||||
|
|
@ -878,7 +857,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
|
|||
dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
|
||||
}
|
||||
snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
|
||||
AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
|
||||
AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -888,7 +867,7 @@ static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
|
|||
struct snd_soc_component *component = dai->component;
|
||||
|
||||
snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
|
||||
AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
|
||||
AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1004,7 +983,7 @@ static int aic32x4_component_probe(struct snd_soc_component *component)
|
|||
/* Power platform configuration */
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
|
||||
snd_soc_component_write(component, AIC32X4_MICBIAS,
|
||||
AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
|
||||
AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
|
||||
}
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
|
||||
snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
|
||||
|
|
@ -1023,16 +1002,16 @@ static int aic32x4_component_probe(struct snd_soc_component *component)
|
|||
/* Mic PGA routing */
|
||||
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
|
||||
snd_soc_component_write(component, AIC32X4_LMICPGANIN,
|
||||
AIC32X4_LMICPGANIN_IN2R_10K);
|
||||
AIC32X4_LMICPGANIN_IN2R_10K);
|
||||
else
|
||||
snd_soc_component_write(component, AIC32X4_LMICPGANIN,
|
||||
AIC32X4_LMICPGANIN_CM1L_10K);
|
||||
AIC32X4_LMICPGANIN_CM1L_10K);
|
||||
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
|
||||
snd_soc_component_write(component, AIC32X4_RMICPGANIN,
|
||||
AIC32X4_RMICPGANIN_IN1L_10K);
|
||||
AIC32X4_RMICPGANIN_IN1L_10K);
|
||||
else
|
||||
snd_soc_component_write(component, AIC32X4_RMICPGANIN,
|
||||
AIC32X4_RMICPGANIN_CM1R_10K);
|
||||
AIC32X4_RMICPGANIN_CM1R_10K);
|
||||
|
||||
/*
|
||||
* Workaround: for an unknown reason, the ADC needs to be powered up
|
||||
|
|
@ -1040,8 +1019,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component)
|
|||
* a HW BUG or some kind of behavior not documented in the datasheet.
|
||||
*/
|
||||
tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
|
||||
snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
|
||||
AIC32X4_LADC_EN | AIC32X4_RADC_EN);
|
||||
snd_soc_component_write(component, AIC32X4_ADCSETUP,
|
||||
tmp_reg | AIC32X4_LADC_EN | AIC32X4_RADC_EN);
|
||||
snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
|
||||
|
||||
/*
|
||||
|
|
@ -1084,13 +1063,13 @@ static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
|
|||
SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
|
||||
|
||||
SOC_SINGLE_TLV("HP Driver Gain Volume",
|
||||
AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
|
||||
AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
|
||||
SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
|
||||
|
||||
SOC_SINGLE_TLV("Speaker Driver Playback Volume",
|
||||
TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
|
||||
TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
|
||||
SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
|
||||
TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
|
||||
TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
|
||||
|
||||
SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
|
||||
};
|
||||
|
|
@ -1126,11 +1105,12 @@ static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
|
|||
static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
|
||||
.name = "tas2505-hifi",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_96000,
|
||||
.formats = AIC32X4_FORMATS,},
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_96000,
|
||||
.formats = AIC32X4_FORMATS,
|
||||
},
|
||||
.ops = &aic32x4_ops,
|
||||
.symmetric_rate = 1,
|
||||
};
|
||||
|
|
@ -1173,7 +1153,7 @@ static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
|
|||
snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
|
||||
|
||||
/*
|
||||
* Enable the fast charging feature and ensure the needed 40ms ellapsed
|
||||
* Enable the fast charging feature and ensure the needed 40ms elapsed
|
||||
* before using the analog circuits.
|
||||
*/
|
||||
snd_soc_component_write(component, TAS2505_REFPOWERUP,
|
||||
|
|
@ -1199,8 +1179,7 @@ static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 =
|
|||
.endianness = 1,
|
||||
};
|
||||
|
||||
static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
|
||||
struct device_node *np)
|
||||
static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, struct device_node *np)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
|
@ -1243,7 +1222,7 @@ static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
|
|||
}
|
||||
|
||||
static int aic32x4_setup_regulators(struct device *dev,
|
||||
struct aic32x4_priv *aic32x4)
|
||||
struct aic32x4_priv *aic32x4)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
|
|
@ -1333,9 +1312,8 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap,
|
|||
struct device_node *np = dev->of_node;
|
||||
int ret;
|
||||
|
||||
aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
|
||||
GFP_KERNEL);
|
||||
if (aic32x4 == NULL)
|
||||
aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), GFP_KERNEL);
|
||||
if (!aic32x4)
|
||||
return -ENOMEM;
|
||||
|
||||
aic32x4->dev = dev;
|
||||
|
|
@ -1379,11 +1357,13 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap,
|
|||
switch (aic32x4->type) {
|
||||
case AIC32X4_TYPE_TAS2505:
|
||||
ret = devm_snd_soc_register_component(dev,
|
||||
&soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
|
||||
&soc_component_dev_aic32x4_tas2505,
|
||||
&aic32x4_tas2505_dai, 1);
|
||||
break;
|
||||
default:
|
||||
ret = devm_snd_soc_register_component(dev,
|
||||
&soc_component_dev_aic32x4, &aic32x4_dai, 1);
|
||||
&soc_component_dev_aic32x4,
|
||||
&aic32x4_dai, 1);
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
* tlv320aic32x4.h
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _TLV320AIC32X4_H
|
||||
#define _TLV320AIC32X4_H
|
||||
|
||||
|
|
@ -24,7 +23,7 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
|
|||
|
||||
/* tlv320aic32x4 register space (in decimal to match datasheet) */
|
||||
|
||||
#define AIC32X4_REG(page, reg) ((page * 128) + reg)
|
||||
#define AIC32X4_REG(page, reg) (((page) * 128) + (reg))
|
||||
|
||||
#define AIC32X4_PSEL AIC32X4_REG(0, 0)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user