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soc: qcom: llcc: Add LLCC configuration for Nord

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Add the sub-cache table for Nord, derived from the Nord AU (Safe IVI)
SCT table and limited to the POR use cases that have a unique SCID and a
usecase ID in llcc-qcom.h. Nord has the CFG0/CFG1 pairs and the full
ALGO_ALLOC0..3 set, so it uses the v6 register offsets.

num_banks is set explicitly because LLCC_LB_CNT in LLCC_COMMON_STATUS0
is four bits wide and cannot report sixteen banks; a wrong count makes
the driver map a bank aperture in place of the broadcast region and abort
on the first broadcast read. no_edac is set because the bootloader
leaves the LLCC EDAC registers locked, as on Glymur.

Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Tested-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260910-nord_llcc-v1-2-30fd1cca65fe@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
This commit is contained in:
Anurag Pateriya 2026-09-10 18:30:44 +05:30 committed by Bjorn Andersson
parent 02171d1103
commit c3a652c41a
2 changed files with 141 additions and 0 deletions
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139
drivers/soc/qcom/llcc-qcom.c
View File

@ -1054,6 +1054,128 @@ static const struct llcc_slice_config kaanapali_data[] = {
},
};
static const struct llcc_slice_config nord_data[] = {
{
.usecase_id = LLCC_CPUSS,
.slice_id = 1,
.max_cap = 3072,
.priority = 0,
.bonus_ways = 0xff,
.activate_on_init = true,
.write_scid_en = true,
.write_scid_cacheable_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CMPT,
.slice_id = 34,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPUHTW,
.slice_id = 11,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPU,
.slice_id = 12,
.max_cap = 2048,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.write_scid_en = true,
.write_scid_cacheable_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_MMUHWT,
.slice_id = 13,
.max_cap = 1024,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CAMFW,
.slice_id = 20,
.max_cap = 512,
.priority = 2,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_ECC,
.slice_id = 26,
.max_cap = 1536,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.write_scid_en = true,
.write_scid_cacheable_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_WRCACHE,
.slice_id = 31,
.max_cap = 2048,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_LCPDARE,
.slice_id = 30,
.max_cap = 512,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.alloc_oneway_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_COMPUTE1,
.slice_id = 22,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_PCIE_TCU,
.slice_id = 15,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPU_LITTLE,
.slice_id = 9,
.max_cap = 2048,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.write_scid_en = true,
.write_scid_cacheable_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPUHTW_LITTLE,
.slice_id = 14,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
},
};
static const struct llcc_slice_config sa8775p_data[] = {
{
.usecase_id = LLCC_CPUSS,
@ -4484,6 +4606,17 @@ static const struct qcom_llcc_config glymur_cfg[] = {
},
};
static const struct qcom_llcc_config nord_cfg[] = {
{
.sct_data = nord_data,
.size = ARRAY_SIZE(nord_data),
.reg_offset = llcc_v6_reg_offset,
.edac_reg_offset = &llcc_v6_edac_reg_offset,
.num_banks = 16,
.no_edac = true,
},
};
static const struct qcom_llcc_config qcs615_cfg[] = {
{
.sct_data = qcs615_data,
@ -4751,6 +4884,11 @@ static const struct qcom_sct_config glymur_cfgs = {
.num_config = ARRAY_SIZE(glymur_cfg),
};
static const struct qcom_sct_config nord_cfgs = {
.llcc_config = nord_cfg,
.num_config = ARRAY_SIZE(nord_cfg),
};
static const struct qcom_sct_config qcs615_cfgs = {
.llcc_config = qcs615_cfg,
.num_config = ARRAY_SIZE(qcs615_cfg),
@ -5693,6 +5831,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,hawi-llcc", .data = &hawi_sct_cfgs },
{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},
{ .compatible = "qcom,nord-llcc", .data = &nord_cfgs},
{ .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs},
{ .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs},
{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},

2
include/linux/soc/qcom/llcc-qcom.h
View File

@ -74,6 +74,7 @@
#define LLCC_CAMSRTIP 73
#define LLCC_CAMRTRF 74
#define LLCC_CAMSRTRF 75
#define LLCC_GPU_LITTLE 80
#define LLCC_OOBM_NS 81
#define LLCC_OOBM_S 82
#define LLCC_VIDEO_APV 83
@ -85,6 +86,7 @@
#define LLCC_CAM_OFE_STROV 93
#define LLCC_CPUSS_HEU 94
#define LLCC_PCIE_TCU 97
#define LLCC_GPUHTW_LITTLE 98
#define LLCC_MDM_PNG_FIXED 100
#define LLCC_PPE_RXDESC 101
#define LLCC_PPE_RXFILL 102