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https://github.com/torvalds/linux.git
synced 2026-09-13 15:40:03 +02:00
ASoC: ux500: Fix MSP stream lifecycle handling
The trigger stop path drops the direction busy flag even though ALSA
still owns the stream until shutdown. A later trigger cannot reliably
restart it, shutdown may leave the block configured, and a second
stream may overwrite shared duplex configuration.
Keep configured and running directions as separate state. Program
shared settings only for the first direction, require a compatible
configuration for the other half of a duplex stream, and enable the
frame generator only while a provider stream is running. Also fix the
RX-disable direction test and preserve the other direction multichannel
setup.
Fixes: 3592b7f69a ("ASoC: Ux500: Add MSP I2S-driver")
Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
Link: https://patch.msgid.link/20260902-ux500-msp-fixes-v2-1-4b60b002d55a@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Linus Walleij
Mark Brown
parent
cee9395acd
commit
c37ba8fe00
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@ -34,8 +34,10 @@ static int setup_pcm_multichan(struct snd_soc_dai *dai,
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if (drvdata->slots > 1) {
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msp_config->multichannel_configured = 1;
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multi->tx_multichannel_enable = true;
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multi->rx_multichannel_enable = true;
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multi->tx_multichannel_enable =
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msp_config->direction & MSP_DIR_TX;
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multi->rx_multichannel_enable =
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msp_config->direction & MSP_DIR_RX;
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multi->rx_comparison_enable_mode = MSP_COMPARISON_DISABLED;
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multi->tx_channel_0_enable = drvdata->tx_mask;
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@ -192,6 +194,7 @@ static int setup_clocking(struct snd_soc_dai *dai,
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case SND_SOC_DAIFMT_BC_FC:
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dev_dbg(dai->dev, "%s: Codec is master.\n", __func__);
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msp_config->clock_provider = false;
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msp_config->iodelay = 0x20;
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msp_config->rx_fsync_sel = 0;
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msp_config->tx_fsync_sel = 1 << TFSSEL_SHIFT;
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@ -204,6 +207,7 @@ static int setup_clocking(struct snd_soc_dai *dai,
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case SND_SOC_DAIFMT_BP_FP:
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dev_dbg(dai->dev, "%s: Codec is slave.\n", __func__);
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msp_config->clock_provider = true;
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msp_config->tx_clk_sel = TX_CLK_SEL_SRG;
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msp_config->tx_fsync_sel = TX_SYNC_SRG_PROG;
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msp_config->rx_clk_sel = RX_CLK_SEL_SRG;
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@ -344,20 +344,27 @@ static int configure_multichannel(struct ux500_msp *msp,
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return 0;
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}
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static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
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static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config,
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bool first)
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{
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int status = 0;
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u32 reg_val_DMACR, reg_val_GCR;
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int status;
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u32 reg_val_DMACR;
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/* Configure msp with protocol dependent settings */
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configure_protocol(msp, config);
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setup_bitclk(msp, config);
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status = configure_protocol(msp, config);
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if (status)
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return status;
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if (first && config->clock_provider) {
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status = setup_bitclk(msp, config);
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if (status)
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return status;
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}
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if (config->multichannel_configured == 1) {
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status = configure_multichannel(msp, config);
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if (status)
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dev_warn(msp->dev,
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"%s: WARN: configure_multichannel failed (%d)!\n",
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__func__, status);
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return status;
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}
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reg_val_DMACR = readl(msp->registers + MSP_DMACR);
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@ -369,11 +376,7 @@ static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
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writel(config->iodelay, msp->registers + MSP_IODLY);
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/* Enable frame generation logic */
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
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return status;
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return 0;
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}
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static void flush_fifo_rx(struct ux500_msp *msp)
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@ -411,12 +414,36 @@ static void flush_fifo_tx(struct ux500_msp *msp)
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writel(reg_val_GCR, msp->registers + MSP_GCR);
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}
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static bool ux500_msp_config_compatible(struct ux500_msp *msp,
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struct ux500_msp_config *config)
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{
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struct ux500_msp_config *active = &msp->config;
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return active->f_inputclk == config->f_inputclk &&
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active->tx_clk_sel == config->tx_clk_sel &&
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active->rx_clk_sel == config->rx_clk_sel &&
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active->srg_clk_sel == config->srg_clk_sel &&
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active->rx_fsync_pol == config->rx_fsync_pol &&
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active->tx_fsync_pol == config->tx_fsync_pol &&
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active->rx_fsync_sel == config->rx_fsync_sel &&
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active->tx_fsync_sel == config->tx_fsync_sel &&
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active->default_protdesc == config->default_protdesc &&
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active->protocol == config->protocol &&
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active->frame_freq == config->frame_freq &&
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active->data_size == config->data_size &&
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active->def_elem_len == config->def_elem_len &&
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active->clock_provider == config->clock_provider &&
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!memcmp(&active->protdesc, &config->protdesc,
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sizeof(active->protdesc));
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}
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int ux500_msp_i2s_open(struct ux500_msp *msp,
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struct ux500_msp_config *config)
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{
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u32 old_reg, new_reg, mask;
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int res;
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unsigned int tx_sel, rx_sel, tx_busy, rx_busy;
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bool first;
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if (in_interrupt()) {
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dev_err(msp->dev,
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@ -444,40 +471,66 @@ int ux500_msp_i2s_open(struct ux500_msp *msp,
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return -EBUSY;
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}
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msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
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first = !msp->dir_busy;
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if (!first && !ux500_msp_config_compatible(msp, config)) {
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dev_err(msp->dev, "%s: Incompatible duplex configuration\n",
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__func__);
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return -EBUSY;
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}
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/* First do the global config register */
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mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
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TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
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RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK |
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LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
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if (first) {
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/* First do the global config register */
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mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
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TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
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RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK |
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SRG_CLK_SEL_MASK | LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
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new_reg = (config->tx_clk_sel | config->rx_clk_sel |
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config->rx_fsync_pol | config->tx_fsync_pol |
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config->rx_fsync_sel | config->tx_fsync_sel |
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config->rx_fifo_config | config->tx_fifo_config |
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config->srg_clk_sel | config->loopback_enable |
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config->tx_data_enable);
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new_reg = config->tx_clk_sel | config->rx_clk_sel |
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config->rx_fsync_pol | config->tx_fsync_pol |
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config->rx_fsync_sel | config->tx_fsync_sel |
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config->rx_fifo_config | config->tx_fifo_config |
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config->srg_clk_sel | config->loopback_enable |
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config->tx_data_enable;
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old_reg = readl(msp->registers + MSP_GCR);
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old_reg &= ~mask;
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new_reg |= old_reg;
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writel(new_reg, msp->registers + MSP_GCR);
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old_reg = readl(msp->registers + MSP_GCR);
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old_reg &= ~mask;
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new_reg |= old_reg;
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writel(new_reg, msp->registers + MSP_GCR);
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}
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res = enable_msp(msp, config);
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res = enable_msp(msp, config, first);
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if (res < 0) {
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dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
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__func__, res);
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return -EBUSY;
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if (tx_sel)
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writel(0, msp->registers + MSP_TCF);
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if (rx_sel)
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writel(0, msp->registers + MSP_RCF);
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if (first) {
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writel(0, msp->registers + MSP_GCR);
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writel(0, msp->registers + MSP_DMACR);
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writel(0, msp->registers + MSP_SRG);
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writel(0, msp->registers + MSP_MCR);
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}
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return res;
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}
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msp->dir_busy |= config->direction;
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if (first) {
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msp->config = *config;
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msp->clock_provider = config->clock_provider;
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}
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if (config->loopback_enable & 0x80)
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msp->loopback_enable = 1;
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/* Flush FIFOs */
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flush_fifo_tx(msp);
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flush_fifo_rx(msp);
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if (tx_sel)
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flush_fifo_tx(msp);
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if (rx_sel)
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flush_fifo_rx(msp);
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msp->msp_state = MSP_STATE_CONFIGURED;
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if (!msp->dir_running)
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msp->msp_state = MSP_STATE_CONFIGURED;
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return 0;
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}
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@ -494,7 +547,6 @@ static void disable_msp_rx(struct ux500_msp *msp)
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~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT),
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msp->registers + MSP_IMSC);
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msp->dir_busy &= ~MSP_DIR_RX;
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}
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static void disable_msp_tx(struct ux500_msp *msp)
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@ -510,7 +562,6 @@ static void disable_msp_tx(struct ux500_msp *msp)
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~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT),
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msp->registers + MSP_IMSC);
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msp->dir_busy &= ~MSP_DIR_TX;
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}
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static int disable_msp(struct ux500_msp *msp, unsigned int dir)
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@ -520,7 +571,7 @@ static int disable_msp(struct ux500_msp *msp, unsigned int dir)
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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disable_tx = dir & MSP_DIR_TX;
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disable_rx = dir & MSP_DIR_TX;
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disable_rx = dir & MSP_DIR_RX;
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if (disable_tx && disable_rx) {
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR | LOOPBACK_MASK,
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@ -553,7 +604,15 @@ static int disable_msp(struct ux500_msp *msp, unsigned int dir)
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int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
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{
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u32 reg_val_GCR, enable_bit;
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u32 reg_val_DMACR, reg_val_GCR, dma_enable_bit, enable_bit;
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unsigned int dir;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK)
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dir = MSP_DIR_TX;
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else if (direction == SNDRV_PCM_STREAM_CAPTURE)
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dir = MSP_DIR_RX;
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else
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return -EINVAL;
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if (msp->msp_state == MSP_STATE_IDLE) {
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dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
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@ -565,21 +624,44 @@ int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (direction == SNDRV_PCM_STREAM_PLAYBACK)
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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enable_bit = TX_ENABLE;
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else
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dma_enable_bit = TX_DMA_ENABLE;
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} else {
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enable_bit = RX_ENABLE;
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dma_enable_bit = RX_DMA_ENABLE;
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}
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if (!(msp->dir_busy & dir))
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return -EINVAL;
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reg_val_DMACR = readl(msp->registers + MSP_DMACR);
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writel(reg_val_DMACR | dma_enable_bit,
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msp->registers + MSP_DMACR);
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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if (msp->clock_provider)
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enable_bit |= FRAME_GEN_ENABLE;
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writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
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msp->dir_running |= dir;
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msp->msp_state = MSP_STATE_RUNNING;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (direction == SNDRV_PCM_STREAM_PLAYBACK)
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if (!(msp->dir_busy & dir))
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return -EINVAL;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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disable_msp_tx(msp);
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else
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msp->dir_running &= ~MSP_DIR_TX;
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} else {
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disable_msp_rx(msp);
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msp->dir_running &= ~MSP_DIR_RX;
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}
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if (!msp->dir_running) {
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR & ~FRAME_GEN_ENABLE,
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msp->registers + MSP_GCR);
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msp->msp_state = MSP_STATE_CONFIGURED;
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}
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break;
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default:
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return -EINVAL;
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@ -594,7 +676,18 @@ int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
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dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
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if (!dir || dir & ~(MSP_DIR_TX | MSP_DIR_RX) ||
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(msp->dir_busy & dir) != dir)
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return -EINVAL;
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status = disable_msp(msp, dir);
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msp->dir_busy &= ~dir;
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msp->dir_running &= ~dir;
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if (msp->dir_busy && !msp->dir_running) {
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writel(readl(msp->registers + MSP_GCR) & ~FRAME_GEN_ENABLE,
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msp->registers + MSP_GCR);
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msp->msp_state = MSP_STATE_CONFIGURED;
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}
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if (msp->dir_busy == 0) {
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/* disable sample rate and frame generators */
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msp->msp_state = MSP_STATE_IDLE;
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@ -618,6 +711,8 @@ int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
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writel(0, msp->registers + MSP_RCE1);
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writel(0, msp->registers + MSP_RCE2);
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writel(0, msp->registers + MSP_RCE3);
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memset(&msp->config, 0, sizeof(msp->config));
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msp->clock_provider = false;
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}
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return status;
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@ -460,6 +460,7 @@ struct ux500_msp_config {
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enum msp_data_size data_size;
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unsigned int def_elem_len;
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unsigned int iodelay;
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bool clock_provider;
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};
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struct ux500_msp {
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@ -470,8 +471,11 @@ struct ux500_msp {
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enum msp_state msp_state;
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int def_elem_len;
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unsigned int dir_busy;
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unsigned int dir_running;
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int loopback_enable;
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unsigned int f_bitclk;
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bool clock_provider;
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struct ux500_msp_config config;
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};
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int ux500_msp_i2s_init_msp(struct platform_device *pdev,
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