From c36461825469a9ceee2346a2e89286c522525da7 Mon Sep 17 00:00:00 2001 From: Ivan Vecera Date: Fri, 14 Aug 2026 10:26:54 +0200 Subject: [PATCH] dpll: zl3073x: scale poll interval proportionally to timeout Replace the fixed 10 us poll sleep in zl3073x_poll_zero_u8() with timeout_us / 50, scaling the sleep interval proportionally to the timeout for all callers. Testing showed that existing callers (mailbox, HWREG, DF read, frequency measurement and phase error polls with 25-50 ms timeouts) typically completed in low hundreds of sleep cycles with the fixed 10 us interval. With the scaled interval the cycle count drops to single digits. The longer PTP-related timeouts (up to 3000 ms for phase step) added in the following patches benefit most, avoiding on the order of 10^5 bus transactions per wait. Reviewed-by: Vadim Fedorenko Signed-off-by: Ivan Vecera Link: https://patch.msgid.link/20260814082656.306534-2-ivecera@redhat.com Signed-off-by: Jakub Kicinski --- drivers/dpll/zl3073x/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dpll/zl3073x/core.c b/drivers/dpll/zl3073x/core.c index 5b2d77f2c228..2e8b52c8de5e 100644 --- a/drivers/dpll/zl3073x/core.c +++ b/drivers/dpll/zl3073x/core.c @@ -322,7 +322,7 @@ int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val) int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 mask, unsigned int timeout_us) { -#define ZL_POLL_SLEEP_US 10 + unsigned int sleep_us = timeout_us / 50; unsigned int val; /* Check the register is 8bit */ @@ -336,7 +336,7 @@ int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; return regmap_read_poll_timeout(zldev->regmap, reg, val, !(val & mask), - ZL_POLL_SLEEP_US, timeout_us); + sleep_us, timeout_us); } int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val,