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dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets

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Document two optional cells in eswin,hsp-sp-csr for the TXD and RXD
delay control register offsets.

These registers are used by the driver to clear any residual delay
configuration left by the bootloader, ensuring that MAC-side RGMII delay
settings are applied solely according to the kernel configuration.

Add a reference to the EIC7700X SoC Technical Reference Manual for
background information about the HSP CSR block.

Fixes: 888bd0eca9 ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260518022023.427-1-lizhi2@eswincomputing.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Zhi Li 2026-05-18 10:20:23 +08:00 committed by Paolo Abeni
parent 48f6a5356a
commit c36069c6f4
1 changed files with 12 additions and 1 deletions
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13
Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
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@ -73,6 +73,15 @@ properties:
HSP CSR is to control and get status of different high-speed peripherals HSP CSR is to control and get status of different high-speed peripherals
(such as Ethernet, USB, SATA, etc.) via register, which can tune (such as Ethernet, USB, SATA, etc.) via register, which can tune
board-level's parameters of PHY, etc. board-level's parameters of PHY, etc.
Additional background information about the High-Speed Subsystem
and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
of the EIC7700X SoC Technical Reference Manual, Part 4
(EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
publicly available at
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
This reference is provided for background information only.
$ref: /schemas/types.yaml#/definitions/phandle-array $ref: /schemas/types.yaml#/definitions/phandle-array
items: items:
- items: - items:
@ -82,6 +91,8 @@ properties:
- description: Offset of AXI clock controller Low-Power request - description: Offset of AXI clock controller Low-Power request
register register
- description: Offset of register controlling TX/RX clock delay - description: Offset of register controlling TX/RX clock delay
- description: Optional offset of register controlling TXD delay
- description: Optional offset of register controlling RXD delay
required: required:
- compatible - compatible
@ -116,7 +127,7 @@ examples:
reset-names = "stmmaceth"; reset-names = "stmmaceth";
rx-internal-delay-ps = <200>; rx-internal-delay-ps = <200>;
tx-internal-delay-ps = <200>; tx-internal-delay-ps = <200>;
eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>; eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
snps,axi-config = <&stmmac_axi_setup>; snps,axi-config = <&stmmac_axi_setup>;
snps,aal; snps,aal;
snps,fixed-burst; snps,fixed-burst;