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dt-bindings: media: camss: Add qcom,sm8550-camss binding
Add bindings for qcom,sm8550-camss in order to support the camera subsystem for sm8550. Co-developed-by: Yongsheng Li <quic_yon@quicinc.com> Signed-off-by: Yongsheng Li <quic_yon@quicinc.com> Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Depeng Shao
Hans Verkuil
parent
2f1361f862
commit
c35ad8e3c5
597
Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml
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597
Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml
Normal file
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@ -0,0 +1,597 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8550 Camera Subsystem (CAMSS)
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maintainers:
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- Depeng Shao <quic_depengs@quicinc.com>
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description:
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The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
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properties:
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compatible:
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const: qcom,sm8550-camss
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reg:
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maxItems: 19
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reg-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csid_lite0
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- const: csid_lite1
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- const: csid_wrapper
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: csiphy5
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- const: csiphy6
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- const: csiphy7
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- const: vfe0
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- const: vfe1
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- const: vfe2
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- const: vfe_lite0
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- const: vfe_lite1
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clocks:
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maxItems: 36
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clock-names:
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items:
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- const: camnoc_axi
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- const: cpas_ahb
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- const: cpas_fast_ahb_clk
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- const: cpas_ife_lite
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- const: cpas_vfe0
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- const: cpas_vfe1
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- const: cpas_vfe2
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- const: csid
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- const: csiphy0
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- const: csiphy0_timer
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- const: csiphy1
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- const: csiphy1_timer
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- const: csiphy2
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- const: csiphy2_timer
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- const: csiphy3
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- const: csiphy3_timer
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- const: csiphy4
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- const: csiphy4_timer
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- const: csiphy5
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- const: csiphy5_timer
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- const: csiphy6
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- const: csiphy6_timer
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- const: csiphy7
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- const: csiphy7_timer
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- const: csiphy_rx
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- const: gcc_axi_hf
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- const: vfe0
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- const: vfe0_fast_ahb
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- const: vfe1
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- const: vfe1_fast_ahb
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- const: vfe2
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- const: vfe2_fast_ahb
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- const: vfe_lite
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- const: vfe_lite_ahb
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- const: vfe_lite_cphy_rx
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- const: vfe_lite_csid
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interrupts:
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maxItems: 18
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interrupt-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csid_lite0
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- const: csid_lite1
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: csiphy5
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- const: csiphy6
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- const: csiphy7
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- const: vfe0
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- const: vfe1
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- const: vfe2
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- const: vfe_lite0
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- const: vfe_lite1
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: ahb
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- const: hf_0_mnoc
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iommus:
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maxItems: 1
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power-domains:
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items:
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- description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
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power-domain-names:
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items:
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- const: ife0
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- const: ife1
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- const: ife2
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- const: top
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vdda-phy-supply:
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description:
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Phandle to a regulator supply to PHY core block.
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vdda-pll-supply:
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description:
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Phandle to 1.2V regulator supply to PHY refclk pll block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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CSI input ports.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI0.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI1.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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port@2:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI2.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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port@3:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI3.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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port@4:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI4.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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port@5:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI5.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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port@6:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI6.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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port@7:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSI7.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- clock-lanes
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- data-lanes
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- interconnects
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- interconnect-names
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- iommus
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- power-domains
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- power-domain-names
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- vdda-phy-supply
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- vdda-pll-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm8550-camcc.h>
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#include <dt-bindings/clock/qcom,sm8550-gcc.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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isp@acb7000 {
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compatible = "qcom,sm8550-camss";
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reg = <0 0x0acb7000 0 0xd00>,
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<0 0x0acb9000 0 0xd00>,
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<0 0x0acbb000 0 0xd00>,
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<0 0x0acca000 0 0xa00>,
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<0 0x0acce000 0 0xa00>,
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<0 0x0acb6000 0 0x1000>,
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<0 0x0ace4000 0 0x2000>,
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<0 0x0ace6000 0 0x2000>,
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<0 0x0ace8000 0 0x2000>,
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<0 0x0acea000 0 0x2000>,
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<0 0x0acec000 0 0x2000>,
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<0 0x0acee000 0 0x2000>,
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<0 0x0acf0000 0 0x2000>,
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<0 0x0acf2000 0 0x2000>,
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<0 0x0ac62000 0 0xf000>,
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<0 0x0ac71000 0 0xf000>,
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<0 0x0ac80000 0 0xf000>,
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<0 0x0accb000 0 0x1800>,
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<0 0x0accf000 0 0x1800>;
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reg-names = "csid0",
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"csid1",
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"csid2",
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"csid_lite0",
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"csid_lite1",
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"csid_wrapper",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"csiphy4",
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"csiphy5",
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"csiphy6",
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"csiphy7",
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"vfe0",
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"vfe1",
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"vfe2",
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"vfe_lite0",
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"vfe_lite1";
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
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<&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
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<&camcc CAM_CC_CPAS_IFE_0_CLK>,
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<&camcc CAM_CC_CPAS_IFE_1_CLK>,
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<&camcc CAM_CC_CPAS_IFE_2_CLK>,
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<&camcc CAM_CC_CSID_CLK>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY3_CLK>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY4_CLK>,
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<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY5_CLK>,
|
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<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
|
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<&camcc CAM_CC_CSIPHY6_CLK>,
|
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<&camcc CAM_CC_CSI6PHYTIMER_CLK>,
|
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<&camcc CAM_CC_CSIPHY7_CLK>,
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<&camcc CAM_CC_CSI7PHYTIMER_CLK>,
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<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
|
||||
<&gcc GCC_CAMERA_HF_AXI_CLK>,
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<&camcc CAM_CC_IFE_0_CLK>,
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<&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_1_CLK>,
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<&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
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<&camcc CAM_CC_IFE_2_CLK>,
|
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<&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CLK>,
|
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<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
|
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<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
|
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clock-names = "camnoc_axi",
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"cpas_ahb",
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||||
"cpas_fast_ahb_clk",
|
||||
"cpas_ife_lite",
|
||||
"cpas_vfe0",
|
||||
"cpas_vfe1",
|
||||
"cpas_vfe2",
|
||||
"csid",
|
||||
"csiphy0",
|
||||
"csiphy0_timer",
|
||||
"csiphy1",
|
||||
"csiphy1_timer",
|
||||
"csiphy2",
|
||||
"csiphy2_timer",
|
||||
"csiphy3",
|
||||
"csiphy3_timer",
|
||||
"csiphy4",
|
||||
"csiphy4_timer",
|
||||
"csiphy5",
|
||||
"csiphy5_timer",
|
||||
"csiphy6",
|
||||
"csiphy6_timer",
|
||||
"csiphy7",
|
||||
"csiphy7_timer",
|
||||
"csiphy_rx",
|
||||
"gcc_axi_hf",
|
||||
"vfe0",
|
||||
"vfe0_fast_ahb",
|
||||
"vfe1",
|
||||
"vfe1_fast_ahb",
|
||||
"vfe2",
|
||||
"vfe2_fast_ahb",
|
||||
"vfe_lite",
|
||||
"vfe_lite_ahb",
|
||||
"vfe_lite_cphy_rx",
|
||||
"vfe_lite_csid";
|
||||
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "csid0",
|
||||
"csid1",
|
||||
"csid2",
|
||||
"csid_lite0",
|
||||
"csid_lite1",
|
||||
"csiphy0",
|
||||
"csiphy1",
|
||||
"csiphy2",
|
||||
"csiphy3",
|
||||
"csiphy4",
|
||||
"csiphy5",
|
||||
"csiphy6",
|
||||
"csiphy7",
|
||||
"vfe0",
|
||||
"vfe1",
|
||||
"vfe2",
|
||||
"vfe_lite0",
|
||||
"vfe_lite1";
|
||||
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "ahb",
|
||||
"hf_0_mnoc";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x20>;
|
||||
|
||||
power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
|
||||
<&camcc CAM_CC_IFE_1_GDSC>,
|
||||
<&camcc CAM_CC_IFE_2_GDSC>,
|
||||
<&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
power-domain-names = "ife0",
|
||||
"ife1",
|
||||
"ife2",
|
||||
"top";
|
||||
|
||||
vdda-phy-supply = <&vreg_l1e_0p88>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csiphy_ep0: endpoint@0 {
|
||||
reg = <0>;
|
||||
clock-lanes = <7>;
|
||||
data-lanes = <0 1>;
|
||||
remote-endpoint = <&sensor_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user