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drm/xe/irq: Handle msix vector0 interrupt

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Current gu2host handler registered as MSI-X vector 0 and as per bspec for
a msix vector 0 interrupt, the driver must check the legacy registers
190008(TILE_INT_REG), 190060h (GT INTR Identity Reg 0) and other registers
mentioned in "Interrupt Service Routine Pseudocode" otherwise it will block
the next interrupts. To overcome this issue replacing guc2host handler
with legacy xe_irq_handler.

Fixes: da889070be ("drm/xe/irq: Separate MSI and MSI-X flows")
Bspec: 62357
Signed-off-by: Venkata Ramana Nayana <venkata.ramana.nayana@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patch.msgid.link/20251107083141.2080189-1-venkata.ramana.nayana@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Venkata Ramana Nayana 2025-11-07 14:01:41 +05:30 committed by Matt Roper
parent 78ff838a8a
commit c34a14bce7
1 changed files with 1 additions and 17 deletions
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18
drivers/gpu/drm/xe/xe_irq.c
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@ -897,22 +897,6 @@ static int xe_irq_msix_init(struct xe_device *xe)
return 0;
}
static irqreturn_t guc2host_irq_handler(int irq, void *arg)
{
struct xe_device *xe = arg;
struct xe_tile *tile;
u8 id;
if (!atomic_read(&xe->irq.enabled))
return IRQ_NONE;
for_each_tile(tile, xe, id)
xe_guc_irq_handler(&tile->primary_gt->uc.guc,
GUC_INTR_GUC2HOST);
return IRQ_HANDLED;
}
static irqreturn_t xe_irq_msix_default_hwe_handler(int irq, void *arg)
{
unsigned int tile_id, gt_id;
@ -1029,7 +1013,7 @@ int xe_irq_msix_request_irqs(struct xe_device *xe)
u16 msix;
msix = GUC2HOST_MSIX;
err = xe_irq_msix_request_irq(xe, guc2host_irq_handler, xe,
err = xe_irq_msix_request_irq(xe, xe_irq_handler(xe), xe,
DRIVER_NAME "-guc2host", false, &msix);
if (err)
return err;