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media: qcom: camss: Add CSIPHY 2.2.0 lane configuration for SM8650

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Add a configuration for all CSI lanes into D-PHY bus mode on Qualcomm
SM8650 CAMSS CSIPHY IPs.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Vladimir Zapolskiy 2025-10-17 06:11:30 +03:00 committed by Hans Verkuil
parent 6a0b9d3f11
commit c33f7e61a1
1 changed files with 102 additions and 0 deletions
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102
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
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@ -587,6 +587,102 @@ csiphy_lane_regs lane_regs_sm8550[] = {
{0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
};
/* GEN2 2.2.0 2PH 4 lane DPHY mode */
static const struct
csiphy_lane_regs lane_regs_sm8650[] = {
{0x0e94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0ea0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
{0x0e30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e0c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e38, 0x1f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e2c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e34, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e1c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e3c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e04, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0e08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0e10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x00a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0000, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0038, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x002c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x003c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x04a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0400, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0438, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x042c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x08a0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0838, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x082c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0834, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x081c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x083c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0804, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0ca0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
{0x0c30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c00, 0x8e, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c38, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c2c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c34, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c1c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c3c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c04, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0c08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
};
/* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
static const struct
csiphy_lane_regs lane_regs_x1e80100[] = {
@ -914,6 +1010,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_8300:
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
ret = true;
@ -1018,6 +1115,11 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
regs->offset = 0x1000;
break;
case CAMSS_8650:
regs->lane_regs = &lane_regs_sm8650[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
regs->offset = 0x1000;
break;
case CAMSS_8300:
case CAMSS_8775P:
regs->lane_regs = &lane_regs_sa8775p[0];